Organization of this Dissertation - 新型PHINES和PREM快閃記憶體及氮化矽型發光電晶體之研究

Chapter 1 Introduction

1.5 Organization of this Dissertation

1.4 Introduction of Light Emitting Devices

Electrical wires meet a fundamental limitation of aspect ratio, and capacitive coupling, which reduces the bit rate. Below 0.13um, interconnect delay starts to dominate over gate delay in Si CMOS. The scaling limitations of electrical wires give an opportunity for optical interconnects. Optical interconnection avoids the issue of aspect ratio. They can replace global wires to provide high data rates. III-V based optical devices are widely accepted due to its direct bandgap and high photon emission efficiency. Silicon is not considered as a good light-emitting source due to its indirect bandgap induced low emission efficiency.

Although silicon optical devices suffer lower light emission efficiency, their applications are numerous (see Fig.1.7) due to the ease of integration in CMOS-based ultralarge scale integrated circuit (ULSI) as shown in Fig.1.8. Silicon light emitting devices can also be used in massively parallel optical interconnects and cross connects for microprocessor and digital-signal processor applications. Traditionally, silicon LEDs have been regarded as a difficult candidate for light emission since they suffer low light emitting efficiency due to the indirect band-gap of silicon. Recently, many attempts including p-n diodes [1.21], MIS diodes [1.22], and nanocrystal LEDs [1.23]

have shown that light emission from silicon materials is readily obtained.

1.5 Organization of this Dissertation

In this dissertation, a novel PHINES (Programming by hot Hole Injection Nitride Electron Storage) flash memory cell is investigated. PHINES uses the nitride storage cell structure. PHINES cell, with its superior reliability, 2 bits-per-cell storage and low

reliability characteristics. In chapter 3, a novel BTB sensing scheme and a new modified NAND-type array are introduced to eliminate the issue of 2-bit interaction.

Chapter 4 discusses the scaling challenges of PHINES memory cell.

In chapter 5, we construct another novel non-volatile flash memory cell named Programmable Resistor with Erase-less Non-Volatile Memory (PREM). PREM can realize multi-time programming, multi-level cell operation, non-volatility, and low voltage operation, and can meet some applications in SOC and embedded areas.

In chapter 6, we develop a novel Silicon-Nitride based Light-Emitting Transistor (SiNLET) with high light emission efficiency, low current consumption and a small device area. The fabrication process of SiNLET is compatible to CMOS technology.

SiNLET demonstrates its high feasibility for the application of optical interconnects in ULSI.

Finally, a conclusion will be given in chapter 7.

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CAMERAS MP3

Mobile

Cell Size 5.5

(F²) Cell Size 0.16

(µm²) Cell Size 10

(F²) Technology node 130

(nm) Cell Size 5.5

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Fig.1.5 Schematic representation of a NROM cell with physically 2-bits

Bit 2

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Fig.1.6 Schematic representation of the chip architecture with embedded flash memory array, high voltage periphery control circuit, and low voltage logic circuit.

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Denotes potential paths of optical interconnects.

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Denotes potential paths of optical interconnects.

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Fig.1.7 Illustration of applications and insertion of optical interconnections.

CMOS

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Fig.1.8 Illustration of integration of CMOS and silicon optical devices.

PHINES Flash Memory Cell with Low Power Program/Erase, Backward-Read Scheme and 2-bit-per-cell Storage

2.1 Introduction

Interest in nitride based localized trapping storage flash memory cells has revived for 2-bits-per-cell operation, which can double the memory density [2.1-2.3].

Besides, they also show better scalability since charges are stored in the nitride traps rather than a poly-silicon floating gate in conventional flash memory cells. Nitride storage memories do not have floating gate induced drain turn-on and coupling issues that are believed to be the scaling limitations of conventional floating gate memories [2.4,2.5]. Various operation schemes were proposed based on the nitride-storage cell structure. SONOS flash memory with modified Fowler-Nordheim-tunneling programming by electrons and direct-tunneling erasing by holes was proposed long time ago [2.6]. The absence of erratic bits and low power operation make SONOS a good candidate for next generation flash technology. However, the cell retention is still an issue now [2.7]. Besides, its large cell size (6F² per bit [6]) and slow program/erase speed limits its applications. Recently, NROM cell with channel-hot-electron (CHE) programming and band-to-band tunneling induced hot-hole (BTBT HH) erasing [2.2] has demonstrated excellent intrinsic cell performance. NROM cell is suitable for code flash applications, and CHE programming is widely accepted in NOR-type architecture. In spite of many advantages, previous works [2.8-2.13] reveal that reliability issues including read disturb, over erase, and cell retention after cycling are major challenges of NROM cell. C.T. Swift et al proposed to use uniform tunneling for erasing [2.3] instead of the hot-hole injection to reduce the stress of high energetic holes in the erase operation.

However, for mass storage and data flash applications, CHE programming is still not suitable due to its high power consumption.

Here, a novel flash memory cell named PHINES (Programming by hot Hole Injection Nitride Electron Storage) [2.1] is investigated. PHINES uses the nitride storage cell structure and can be arranged in both NOR-type and NAND-type array for code and data flash applications. The operation principles, cell characteristics, and cell reliability will be studied and characterized in this chapter.

2.2 PHINES Cell Structure

PHINES memory cell is a NMOSFET with an ONO stack as the gate dielectric

gate length and gate width are 0.19µm and 0.14µm, respectively. The thickness of each ONO layer is 9nm, 6nm, and 6nm from top to bottom. The top oxide and bottom oxide are formed by thermal oxidation while nitride is performed by CVD deposition.

A double poly technology, novel low-temperature dielectric film fill-in and planarization process is introduced to form a sufficiently thick insulating layer between the local buried-diffusion (BD) bit-lines and the word-lines (WLs) [2.14].

Figure 2.3 (a) and (b) show the TEM pictures of the cell, in which the X-pitch and Y-pitch are 0.33µm and 0.28µm, respectively.

2.3 PHINES Cell Operation Condition, and Cell Characteristics

2.3.1 PHINES Cell Operation Condition

PHINES cell uses gate FN electron injection (negative gate-to-substrate bias) and BTBT HH injection as the erase and program methods, respectively. Schematic representations of PHINES cell operation are shown in Fig.2.4. The bias conditions are given in Table.2.2. Figure 2.5 shows the erasing characteristics and the Vt saturates after 1ms. As shown in Fig.2.6 (a), electrons are injected from the gate via tunneling through the top oxide (path 1) in the erase operation. Some of the tunnel electrons are captured by the nitride traps (path 2, either deep traps or shallow traps), while the others will inject into the substrate (path 3). Electrons in the shallow traps will easily be drawn out due to the high electric field (path 4) and only electrons in deep traps remain in the nitride. Accordingly, the erase saturation may be caused by the limited amount of deep nitride traps, and cell Vt will saturate while all deep traps are filled with electrons. PHINES cell does not have an over-erasure problem due to the self-convergent behavior of FN injection, which can improve the uniformity and tighten the Vt distribution of the erased cells.

The program of a PHINES cell is done by lowering the local Vt through edge BTBT HH injection. Fig.2.6 (b) shows the band structure of PHINES cell during program operation. Figure 2.7 shows the program characteristics of the two bits. In Fig.2.7 (a), bit-1 is programmed to a low Vt, while bit-2 is in the erased state. Bit-2 is subsequently programmed in Fig.2.7 (b). Since the program is performed by bit-by-bit and shot-by-shot tracking, a verification step is applied after each program shot to well control the program behavior of each bit. The program of each bit stops as its Vt or current passes the program verification. Over-program induced leakage current in the low Vt state between two columns can be suppressed, and a narrow Vt distribution

bias is applied to reduce the channel potential near bit-2 (bit-1). The IV characteristics of each state are shown in Fig.2.8.

2.3.2 The Charge Distribution

In Fig.2.9, the charge pumping technique [2.15] is utilized to monitor the charge variation in the nitride. The open circles and solid circles represent the initial and erased conditions. The Vt shift after erase is around 2.5V. The solid up-triangles and down-triangles represent the charge distribution in nitride after 1µs and 200µs programming. After FN electron erasing and hot-hole programming, a tail of charge pumping current (Icp) is observed. The turn-on Vt (Vgh) of the Icp tail is proportional to the number of storage holes in a programmed bit while the amount of the Icp tail is proportional to the length of the programmed holes in the channel region. As program time increases, the increase of Icp in the portion of 1V<Vgh<3.5V represents that hot holes are injected into the nitride from junction edge toward channel wherein a bit is programmed.

2.3.3 2-bit Interaction Effect

Two-bit interaction effect is a unique phenomenon in physical 2-bit storage memory cell, which is caused by the interaction between bit-1 and bit-2 during backward read operation. Similar to NROM cell [2.16], PHINES cell suffers 2-bit interaction effect and operation Vt window reduction due to the channel current sensing and the backward read scheme. Fig.2.10 (a) shows the program characteristics.

In the initial state (condition A), two bits are in high Vt states. Figure 2.10 (b) and (c) illustrate the channel potential of condition A during read operation. As bit-1 is intentionally programmed to a low Vt state, a slight Vt decrease is observed in bit-2 (condition B in Fig.2.10 (a)), which induces Vt window reduction. Fig.2.10 (d) and (e) illustrate the channel potential of condition B (bit-1 is in a low Vt state while bit-2 is in a high Vt state). In condition B, as bit-1 is read (see Fig.2.10 (d)), a high read Vd is used to pull down the channel potential near bit-2, and a low Vt of bit-1 is thus sensed.

To read bit-2 (see Fig.2.10 (e)), the high read Vd and the local/narrow electron distribution of bit-2 after bit-1 programming will enhance the Drain-Induced-Barrier- Lowering (DIBL) effect and lower the channel potential. Compared to the condition A (Fig.2.10 (c)), a lower Vt of bit-2 is obtained, and a reduced Vt operation window is caused. Since the Vt of bit-2 is very sensitive to the programmed condition of bit-1, we name this phenomenon ì 2-bit interaction effectî .

Device simulation is used to characterize the effects of cell parameters on the Vt operation window. The definitions of the simulated cell parameters are descried in

and the density of the stored electrons. In Fig.2.12, as the length of the residual electron distribution decreases (the length of the programmed hole distribution increases), Vt window increases under a fixed read Vd and, in other words, read Vd can be reduced to maintain a constant Vt window. Besides, higher stored electron density can also increase Vt window without increasing the read bias as shown in Fig.2.13. A narrower electron distribution, a higher electron density, and a lower read Vd could suppress the DIBL effect enhanced Vt reduction and enlarge the Vt window.

Accordingly, 2-bit interaction effect can be suppressed by optimizing the charge profiles and the operation schemes. As mentioned in Section 2.3.1, PHINES can determine the stored electrons via erase operation and well control the injected amount of holes to modulate the length of residual electrons via program and program verification, separately. Although we can suppress Vt window reduction via better operation algorithms and carrier injection processes to manage the charge distribution, the 2-bit interaction effect cannot be eliminated completely in the backward read scheme. Besides, 2-bit interaction effect will get worse in the next generation due to the enhanced DIBL in a scaled device. In chapter 3, a novel BTB-PHINES memory cell and BTB-sensing (band-to-band sensing) scheme are developed to solve this issue completely.

2.3.4 PHINES Cell Endurance and Vt Operation Window

Figure 2.14 and Fig. 2.15 show the P/E cycling endurance of 1-bit-per-cell and 2-bits-per-cell operation, respectively. The Vt window is almost unchanged up to 10K P/E cycles. A slight window closure is observed after 100K cycles. This phenomenon is widely observed in flash memory cells, which should result from the stress-induced bottom/top oxide degradation [2.17]. The Vt operation window of 1-bit-per-cell and 2-bit-per-cell operation is around 2V and 1.2V, respectively.

2.3.4 PHINES Cell Performance

The electrical performance of a PHINES cell is summarized in Table 2.3.

Program can be finished within 200µs and erase can be done in 2ms. Vt-windows of 2V and 1.2V are obtained for 1-bit-per-cell and 2-bits-per-cell operation. Since the program current is less than 50nA/bit, high programming rate can be achieved by parallel programming. Besides, FN-erase also consumes extremely low current (10fA/cell). Both program and erase are low power operations, which makes it suitable for mass storage (data flash) applications.

2.4.1 Data Retention

Fig.2.16 shows the data retention characteristics of three program/erase states. Vt loss is less than 0.5V and 0.2V for high-Vt bits and low-Vt bits, respectively, after 150C, 168 hours bake in 10K P/E cycled cells. Fig.2.17 shows the temperature effect on data retention in a high Vt state. Three storage temperatures are compared: 25C, 85C, and 150C. Excellent data retention is observed. In previous studies [2.18], hot electron injection tends to fill traps with shallower energy in a stressed oxide film. We also use this characterization method to monitor the characteristics of electrons in the nitride traps. High Vt state charge loss behavior of two electron injection techniques (FN injection and substrate hot electron injection) is compared in Fig.2.18. Two devices are stressed by constant voltage stress (Vg=-24V, Vd=Vs=Vb=0V) for 1000s.

After stress, hot-hole injection is performed to lower the Vt of the devices. Finally, FN injection and substrate hot electron (SHE) injection are used to inject electrons into two devices to raise Vt to 5V, respectively. Vt shift is measured in the high temperature condition (150C). As shown in Fig.2.18, the device with FN electron injection shows less charge loss than the device with SHE injection. It is surmised that hot electrons in SHE will jump over the oxide barrier and are randomly captured by deep and shallow traps of nitride as shown in Fig.2.19 (a). Electrons in shallower traps will easily escape during a storage period and charge loss is observed as shown in Fig.2.19 (b). However, tunnel electrons by FN injection tend to stay in deep traps of nitride since electrons in shallow traps will be drawn out by high electric field as shown in Fig.2.20 (a). According to the Frenkel-Poole model, electrons in deeper traps have longer emission time and good data retention is obtained accordingly as shown in Fig.2.20 (b).

2.4.2 Read Disturbance

Read disturbance is another reliability issue of flash memory devices. As the device is in a low Vt state, continuously reading the device will induce disturbance due to the high channel current and hot electron injection. Vt will increase and the read current will degrade accordingly. We also evaluate the read disturbance characteristics of a PHINES cell. As shown in Fig.2.21, the read condition (Vg=3V, Vd=1.6V, and Vs=0V to read Bit-2) is applied to the device while two bits are both at low Vt states (Vt is around 2V). The Vt shifts of both bits are measured. Vt drift of 0.2V is observed in Bit-1 by continuous read of 10000s while there is almost no disturbance in Bit-2. The reason is that a high voltage is applied on the drain, which induces hot electron injection at the drain side. Accordingly, the Vt of Bit-1 increases

injection at the source side, which will cause read disturbance in Bit-2.

Read disturbance is a potential scaling issue due to enhanced hot carrier effect in a scaled device [2.19]. Higher substrate doping concentration, shorter channel length and cycling induced damages will degrade read disturbance and the only solution is to reduce read Vd. In section 2.3.3, the effects of read Vd, length of residual electron distribution and density of stored electrons have been discussed. As shown in Fig.2.12, read Vd can be reduced without degrading the Vt window by optimizing the length of the residual electron distribution. PHINES can determine the stored electrons via erase verify step and well control the injected amount of holes to modulate the length of residual electrons via program verify step, separately. Accordingly, by managing electron profile, hole profile and stored electron density, a large Vt window and reduced read disturbance (by lowering read Vd) can be realized in future scaled devices.

2.5 PHINES Array Architecture

2.5.1 PHINES Operation in Virtual Ground Array (NOR-type) Architecture PHINES cells can be arranged in the virtual ground array (NOR-type) as shown in Fig.2.22. In NOR-type array architecture, the cells are connected in parallel. Fig.

2.22 (a), (b) and (c) show the array erase, program and read operations, respectively.

In array erase operation, a negative bias (-9V) and a positive bias (10V) are applied on the selected WLs and P-well, respectively. Electron injection via Fowler-Nordheim tunneling from the gate is used to erase the selected cells to high Vt states. In order to program PHINES cells in a high-density virtual ground array, a technique to inhibit the program disturbance in the adjacent cell is necessary. As shown in Fig.2.22 (b), to program the bit-1 in cell-A, a positive bias (5V), a grounded bias, and a negative bias (-7V) is applied on the BL2, BL1, and the selected WL, respectively. The program disturbance of the adjacent cell-B sharing the same bit-line (BL) and word-line (WL) is inhibited by properly biasing the unselected BL3 (ex: 3V). The programming behavior of cell-A and disturbance behavior of cell-B and cell-C are shown in Fig.2.23. The channel potential of cell-A and cell-B are plotted in Fig.2.24. Dramatic reduction of hot-hole injection by an inhibitive BL bias is due to a less lateral electric field [2.20]. Likewise, in cell-C sharing the same BL, but a different WL, grounding the unselected WL reduces the program disturbance because of the less vertical field.

Fig.2.22 (c) shows the operation condition of the backward read scheme in array

current of the selected cell is sensed to determine the storage state of bit-1. To program and read the storage state of bit-2, similar operations can be applied by interchanging the role of BL1 and BL2.

2.5.2 PHINES Operation in NAND-type Array Architecture

PHINES cells can be also arranged in NAND-type array. In NAND-type array architecture, one NAND string contains 32 memory cells and 2 select-transistors (SLG1 and SLG2) that are arranged in series as shown in Fig.2.25 [2.21]. Fig.2.25 (a), (b) and (c) show the array erase, program, and read operations, respectively. In array erase operation as shown in Fig.2.25 (a), a negative bias (-9V) and a positive bias (10V) are applied on the selected WLs and P-well, respectively. Electron injection via Fowler-Nordheim tunneling from the gate is used to erase the selected cells to high Vt states. Fig.2.25 (b) shows the array program operation. To program bit-1 of the selected WL (WL3), a positive bias (5V), a grounded bias, and a negative bias (-7V) are applied on the drain, source, and the selected WL, respectively. The non-selected WLs are turned on (10V), which serves as pass transistors to pass the drain and source voltages. To read bit-1 of the selected WL (WL4) as shown in Fig.2.25 (c), a positive bias (1.6V), a grounded bias, and another positive bias (3V) are applied on the source, drain, and the selected WL, respectively. The non-selected WLs also serve as pass transistors to pass the read current, and the storage state of bit-1 is determined accordingly. To program and read the storage state of bit-2, similar operations can be applied by interchanging the role of the source and the drain.

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