Chapter 6 A novel Silicon-Nitride based Light-Emitting Transistor (SiNLET)
6.3 Electrical and Optical Properties
6.2.3 Light Spectrum and CCD Image
Fig.6.4 (a) and (b) show the light spectrum and CCD image of SiNLET, respectively. SiNLET shows peak intensity at the wavelength of around 700nm (~1.8eV), and its light spectrum contains infrared ray and visible ray (1100nm ~ 400nm). To further investigate the detail of SiNLET, the light spectrums of several bias conditions and device structures are compared. As shown in Fig.6.4, if we just apply a negative bias on the poly with FN-E supply only, no light emission is observed. Similar result is obtained as we only supply BTBT HH without electron injection. When a MOS structure without nitride traps is used to replace the SONOS structure, we still donít observe light emission (see Fig.6.4 (a) and (c)).
Fig.6.5 compares the light spectrums of a reverse-biased junction and a forward-biased junction. In the reverse-biased junction, a shorter wavelength and lower current consumption are obtained, which results from the scattering, trapping, and recombination of high energetic electrons and holes via nitride traps. In contrast, the forward-biased junction functions as a pure p-n-junction LED, and shows peak intensity at around 1000nm. The photon energy is around 1.2eV, which should be caused by the electron/hole pair recombination in the bulk substrate via silicon band-gap. Table 5.1 summarizes the results of light emission in various bias conditions and device structures. High energetic electrons, hot holes and nitride traps (quantum dots for carrier scattering, trapping and recombination) are essential for SiNLET to emit high energetic photons.
6.3 Electrical and Optical Properties
Fig.6.6 (a) and Fig.6.7 (a) show the light spectrum of SiNLET operated in different Ve and Vh. Higher Ve or Vh shows larger output light intensity due to the increased input vertical and lateral electrical field. Fig.6.6 (b) and Fig.6.7 (b) show the supply current from the n+ junction to the p-well (Ih=-Ic), which is induced by band-to-band tunneling. In the normal operation condition, the current from the poly
SiNLET can function as a three-terminal light-emitting transistor as shown in Fig.6.8. The poly (Ve) and n+ junction (Vh) serves as the Source and the Drain to supply electrons and holes, respectively. The control voltage (Vc) in the p-well can control the lateral electrical field to modulate the output light intensity, which serves as the Gate. Fig.6.9 shows the output light intensity versus the supply current, and they have nearly linearly dependence. Fig.6.10 shows the output light intensity as a function of Vc. Fig.6.11 demonstrates the characteristics of output light intensity as a function of input Ve and Vh. The threshold voltage of Vc is around 2V to switch SiNLET. Fig.6.12 shows the voltage stress effect on SiNLET. After continuously stress for 10 hours, a little degradation of light intensity is observed, which should result from the stress induced deterioration of the ONO film. The wavelength of peak intensity after electrical stress is still 700nm.
6.4 Conclusion
We have reported a novel SiNLET with high light emission efficiency and low current consumption (<10-7A/µm) in a small device area (~0.616µm2), and its process is compatible to standard CMOS. SiNLET shows peak intensity at around 700nm, and its light spectrum contains infrared and visible light. SiNLET can modulate the output light intensity by controlling the input voltages, and functions as a light-emitting transistor. SiNLET can be integrated with CMOS devices easily as shown in Fig.6.13 and has demonstrated its high feasibility for the application of optical interconnects in ULSI.
h
υ
ElectronHole
h
υ
ElectronHole
Poly
h
υ
Oxide Nitride Oxide n+
Electron Hole
BTBT-HH FN-E
Fig.6.3 Schematic representation of the band diagram of SiNLET in the operation condition of light emission.
Fig.6.4 (a) Light spectrum of various bias conditions and device structures.
Squares represent the spectrum of the normal operation condition of SiNLET.
Circles and up-triangles represent the spectrum with FN-E supply only and BTBT-HH supply only in SONOS structure, respectively. Down-triangles represent the spectrum of the normal operation condition in MOS structure (oxide thickness is 18nm). (b) CCD image of SiNLET in the normal operation condition. (c) CCD image of MOS structure in the normal operation condition (Vc/Ve/Vh=0/-16/5.8).
(a)
200 400 600 800 1000 1200 -500
0 500 1000 1500 2000 2500 3000
Intensity (a.u.)
Wave Length (nm)
SONOS structure
Ve=-16, Vh=5.8 (normal condition) Ve=-23, Vh=0 (FN-E only)
Ve=0, Vh=5.8 (BTBT-HH only) MOS structure Ve=-16, Vh=5.8 (without nitride traps)
(b) (c)
Fig.6.5 Light spectrum of SiNLET in the operation condition of forward-biased junction (circles) and reverse-biased junction (squares).
Reverse-biased junction shows shorter wavelength and higher photon energy, and the supply current is 3 orders less than the forward-biased junction.
200 400 600 800 1000 1200 0
500 1000 1500 2000 2500 3000 3500
Inte ns it y (a .u .)
Wave Length (nm)
Vh=-0.85, Ve=0
current supply ~3x10
-5A/ µ m Vh=5.8, Ve=-16
current supply ~7.5x10
-8A/ µ m
Table 6.1 Summary of various test-bias conditions and test-device structures in Fig.5.4 and Fig.5.5.
O X
X X
Photon O Emission
Photon O Emission
Fig.6.6 (a) Light spectrum of SiNLET in various Ve (Vh=5.8V). Higher Ve shows larger intensity. The peak intensity is at 700~800nm in all conditions.
(b) The supply current (Ih) versus the operation voltage of poly (Ve) with a constant Vh of 5.8V. In all bias conditions, the current at n+junction is equal to p-well (Ih=Ic) and the current at the poly (Ie) is negligible.
(a)
(b)
200 400 600 800 1000 1200 0
500 1000 1500 2000 2500
In tens ity (a.u.)
Wave Length (nm)
Ve=-13 Ve=-14 Ve=-15 Ve=-16
-17 -16 -15 -14 -13 -12
0.0 2.0x10-8 4.0x10-8 6.0x10-8 8.0x10-8 1.0x10-7
Ih (A/
µm)
Ve (V)
Vh=5.8
(a)
Fig.6.7 (a) Light spectrum of SiNLET in various Vh (Ve=-16V). Higher Vh shows larger intensity. The peak intensity is at 600~700nm in all conditions.
(b) The supply current (Ih) versus the operation voltage of n+ junction (Vh) with a constant Ve of -16V. In all bias conditions, the current at n+ junction is equal to p-well (Ih=Ic) and the current at the poly (Ie) is negligible.
200 400 600 800 1000 1200 0
500 1000 1500 2000 2500 3000
In te ns it y (a .u .)
Wave Length (nm)
Ve=-16Vh=4.6 Vh=5 Vh=5.4 Vh=5.8
4.5 5.0 5.5 6.0
0.0 2.0x10-8 4.0x10-8 6.0x10-8 8.0x10-8 1.0x10-7
Ih (A /
µm)
Vh (V)
Ve=-16
Fig.6.8 Schematic illustration of SiNLET to function as a three-terminal transistor. The poly supplying electrons serves as the Drain. The n+ junction supplying holes serves as the Source. The p-well controlling the lateral field serves as the Gate. The nitride traps serve as quantum dots for carrier trapping and recombination.
Fig.6.9 The supply current density versus output light intensity. The data are extracted from Fig.5.6 and Fig.5.7.
0.0 2.0x10
-84.0x10
-86.0x10
-88.0x10
-80
2000 4000 6000 8000 10000
Intensity (a.u .)
Ih (A/ µ m)
Fig.6.10 The light intensity as a function of Vc (Vh=5.8V, Ve=-16V). The threshold voltage of Vc is around 2V to switch SiNLET.
0 1 2 3 4
0 2000 4000 6000 8000 10000
Intensi ty ( a.u .)
Vc (V)
Vh=5.8, Ve=-16
Fig.6.11 The light intensity as a function of Ve and Vh (Vc=0V).
4.5 0 5.0 5.5 6.0
2000 4000 6000 8000 10000
In tens ity ( a.u.)
Vh (V)
Ve=-16
Ve=-15
Ve=-14
Ve=-13
Fig.6.12 The light spectrum before and after stress. The stress condition and light emission measurement condition are both Vc/Ve/Vh=0/-16/5.8V.
200 400 600 800 1000 1200 0
500 1000 1500 2000 2500 3000
Intensity (a. u .)
Wave Length (nm)
Ve=-16, Vh=5.8 Stress time=0
Stress time=1 hours
Stress time=10 hours
CMOS
h ν
SiNLET
Fig.6.13 Illustration of integration of CMOS and SiNLET devices.
Conclusion
We investigated a novel flash memory cell named PHINES (Programming by hot Hole Injection Nitride Electron Storage). PHINES uses a nitride trapping storage cell structure. Channel FN erasing is performed to raise Vt while programming is done by lowering local Vt through band-to-band hot-hole injection. PHINES uses backward read scheme with low power program/erase operation, and physically 2-bits-per-cell storage is achieved. PHINES cell also shows good retention and cell reliability and can be arranged in both NOR-type and NAND-type array architectures for code flash and data flash applications.
However, PHINES cell suffers the issue of 2-bit interaction due to the backward read scheme. Two-bit interaction effect caused by the local storage carriers and the DIBL will result in the reduction of the Vt operation window. The effects of the charge profile on the Vt operation window are also studied and characterized.
Although a narrower electron distribution, higher electron storage density, better program/erase algorithms, and a lower read-Vd can be used to increase the operation window, 2-bit interaction effect can not be eliminated completely and will get worse in a scaled device. To overcome this issue, a novel BTB sensing scheme and a new modified NAND-type array are introduced in chapter 3. Since BTB current is generated locally between the drain (or source) and P-well, the sensing currents of two bits are independent and will not affect each other. BTB-PHINES eliminates the 2-bit interaction effect and a large operation window can be obtained by BTB sensing scheme. We also construct a novel modified NAND-type array to realize 2-bits-per-cell operation and high-density storage. BTB-PHINES memory cell demonstrates a fast cell programming speed (≦60µs) with a low programming current (≦100nA/cell), and a high programming throughput can be achieved. Besides, the sensing current shows weak temperature dependence, and good cell reliability is demonstrated.
In chapter 4, we compare the scaling challenges of PHINES and floating gate technologies. PHINES technology can achieve compatible performance and bit size to floating gate technologies for most data flash memory applications. According to our evaluations, 1-bit PHINES suffers the scaling challenges of few storage carriers, inter-WL leakage/breakdown, and cell punch beyond 15nm CMOS generation.
Two-bit PHINES suffers scaling challenges of the distribution of a programmed bit,
scalability, and 15nm generation for 1-bit-per-cell storage and 30nm generation for 2-bits-per-cell storage are feasible in NAND-type array architecture.
In chapter 5, a novel non-volatile memory cell named PREM (Programmable Resistor with Erase-less Memory) is constructed for SOC and embedded flash memory applications. Instead of the conventional ì eraseî operation, PREM adjusts the reference level to reset the data. By utilizing the progressive breakdown of ultra-thin oxide and the new ì Erase-lessî operation, PREM can realize MTP and/or MLC. Only one extra or none mask is needed with CMOS standard process. No degradation of cell retention, no program disturbance, and no read disturbance are observed, and the cell reliability is guaranteed. PREMís low voltage operation, high scalability and simple process are superior for SOC or very low cost and high-density storage applications.
In chapter 6, we reported a novel SiNLET (Silicon-Nitride based Light-Emitting Transistor) with high light emission efficiency and low current consumption (<10-7A/µm) in a small device area (~0.616µm2). This three-terminal electroluminescence device uses a SONOS-type device structure, and its process is compatible to standard CMOS devices. Photons are generated by Fowler-Nordheim electron tunnel-injection, band-to-band tunneling induced hot-hole injection, and carrier scattering/trapping/recombination via nitride traps. SiNLET shows peak intensity at around 700nm, and its light spectrum contains infrared and visible light.
SiNLET can modulate the output light intensity by controlling the input voltages, and functions as a light-emitting transistor. SiNLET has demonstrated its high feasibility for the application of optical interconnects in ULSI.
Chapter 1
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Chapter 3
[3.1] Y.S. Yim, K.S. Shin, S.H. Hur, J.D. Lee, I.G. Baik, H.S. Kim, S.J. Chai, E.Y.
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Chapter 4
[4.1] Y.S. Shin, “Non-volatile Memory Technologies for Beyond 2010,” Symposium on VLSI Cir. Dig., pp.156-159, 2005
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Parent, M. Wei, B.J. Woo, A. Fazio, “Flash ETOXTM Virtual Ground Architecture: A Future Scaling Direction,” Symposium on VLSI Tech. Dig., pp.204-205, 2005
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Memory of 64Mb and Beyond,” IEEE IEDM Tech. Dig., pp. 907-910, 2004 [4.5] C.C. Hung, M.J. Kao, Y.S. Chen, Y.H. Wang, H.H. Hsu, C.M. Chen, Y.J. Lee,
W.C. Chen, J.Y. Lee, W.S. Chen, W.C. Lin, K.H. Shen, J.H. Wei, L.C. Wang, K.L. Chen, S. Chao, D.D. Tang, and M.J. Tsai, “High Density and Low Power Design of MRAM,” IEEE IEDM Tech. Dig., pp. 575-578, 2004
[4.6] J.H. Park, H.J. Joo, S.K. Kang, Y.M. Kang, H.S. Rhie, B.J. Koo, S.Y. Lee, B.J.
Bae, J.E. Lim, H.S. Jeong, and Kinam Kim, “Fully Logic Compatible (1.6V Vcc, 2 Additional FRAM Masks) Highly Reliable sub 10F2 Embedded FRAM with Advanced Firect Via Technology and Robust 100nm Thick MOCVD PZT Technology),” IEEE IEDM Tech. Dig., pp. 591-594, 2004
[4.7] C. Chen, and T.P. Ma, “Direct Lateral Profiling of Hot-carrier induced Oxide Charge and Interface Traps in Thin MOSFET’s,” IEEE Trans. on Elect. Dev., vol.45, pp.512-520, 1998
Chapter 5
[5.1] C. de Graaf, P.H. Woerlee, C.M. Hart, H. Lifka, P.W.H de Vreede, P.J.M.
Janssen, F.J. Sluijs, and G.M. Paulzen, “A Novel High-Density Low-Cost Diode Programmable Read Only Memory,” IEEE IEDM Tech. Dig., pp.189-192, 1996
[5.2] S.B. Herner, A. Bandyopadhyay, S.V. Dunton, V. Eckert, J. Gu, K.J. Hsia, S.
Hu, C. Jahn, D. Kidwell, M. Konevecki, M. Mahajani, K. Park, C. Petti, S.R.
Hu, C. Jahn, D. Kidwell, M. Konevecki, M. Mahajani, K. Park, C. Petti, S.R.