Outline of this work

The target of this work is to investigate the generation / propagation of substrate

coupling noise prediction and finally to figure out a new solution that can effectively alleviate the substrate coupling noise problem in modern mixed-signal SoC designs.

This thesis will be organized as follows: Chapter 2 discusses the substrate noise issue in mixed-signal circuits, which mainly talks about the generation, propagation of substrate coupling noise and also the substrate coupling noise impact on analog/mixed-signal/RF circuits. In Chapter 3, previous techniques for substrate coupling noise suppression are introduced, classified as passive and active methods. Substrate characterization is done in this work to find out and compare the isolation abilities of conventional guard rings, Substrate networks are also extracted in this process for future utilizations. In the end, we will propose an active guarding technique for substrate coupling noise suppression that combines the advantages of both passive and active methods. Chapter 4 presents the details about the active guarding technique, which includes the design, analyses, implementation and experimental results of active guarding circuits. In Chapter 5, the proposed active guarding technique is implemented on a LC-tank oscillator to verify the feasibility in real applications. Finally, Chapter 6 gives the conclusions and future works.

Chapter 2

Substrate Noise in Mixed-Signal Integrated Circuits

2.1 Introduction

Continuous down-scaling of CMOS technology has led VLSI design to “System-on-Chip”

(SoC) design, a mixed-signal single chip solution for both digital and analog circuits.

However, such integration causes substrate coupling noise which results in the degradation of signal integrity. Digital switching noise couples through the parasitic capacitance of substrate and then corrupts sensitive analog circuits. This problem becomes more and more critical as the supply voltage decreases, the operation frequency increases, and also when the more densely the components are placed on a chip. The substrate noise problem in mixed-signal ICs is going to be discussed here by three classified topics as: the noise generation mechanisms, the propagation mechanisms and the impact on analog/RF circuits.

2.2 Generation Mechanisms 2.2.1 Impact Ionization

When a MOS device is biased in saturation region, a high electric field in the depletion region of the channel is formed close to the drain node. Due to this high electric field, the channel carriers are accelerated and gain enough energy to generate electron-hole pairs by scattering in the crystal lattice. The electrons are subsequently swept into the drain, but the holes flow through the substrate and are collected by the P+ substrate contacts connected to

GND or VSS, causing a current generation. For NMOS transistors, the generated holes are swept to the substrate generating a drain-to-substrate impact ionization current. This current produces IR drops on the substrate resistance which appear as dynamic voltage variations in the substrate. While in PMOS transistors, the magnitude of the generated current is about an order smaller than the impact ionization current generated by the NMOS transistors due to the lower hole mobility.

In addition, PMOS transistors are physically situated in a N-well, which tend to reduce coupling of currents to the surrounding p-type substrate due to its capacitive impedance. Thus it is expected that PMOS devices cause / suffer from lower substrate noise than comparably sized NMOS devices. This phenomenon is insignificant in older technologies but should be considered in deep-submicron CMOS processes [7], [8]. However in general, it remains as a minor role among substrate noise sources because the power supply/ground noise and capacitive coupling are normally much larger since they increase with scaling [9].

2.2.2 Capacitive Coupling

There are two types of coupling paths: The first is capacitive coupling through PN-junctions capacitors; the second is capacitive coupling of interconnects.

2.2.2.1 Junction Capacitances

Junction capacitances in CMOS circuits are at the source and drain nodes of transistors, where the P-N junctions are formed due to the reverse biasing. The reverse-biased P-N junctions form non-linear and voltage-dependent capacitors therefore create a capacitive coupling path to inject and receive substrate noise. This capacitance can be approximated to:

m respectively. The gradient coefficient is denoted as m, q is the elementary charge andεsi is the permittivity of silicon.

2.2.2.2 Interconnects

Figure 3 Capacitive coupling of adjacent interconnects

The on-chip interconnects are capacitively coupled to the substrate and adjacent interconnects as illustrated in Figure 3. The capacitive coupling between two interconnects and substrate are modeled with capacitors C1 and C2. This capacitive coupling of interconnects depends on the location of the metal lines, the length, width and the distance to other objects. For interconnects in the lower metal layers, the coupling is more serious to the substrate than interconnects in the upper layers.

2.2.2.3 Power Supply and Ground grids

Power supply and ground bounce noises are created when displacement currents flow through the parasitics associated with the power supply networks. The power distribution path includes on-chip metal lines, bond wires, package wires and pins and PCB tracks to the ideal power supplies; there is also mutual capacitance and inductance between lines. Parasitics associated with external ports (bond wires, package pins, board tracks, etc.) are typically modeled as lumped-elements of series inductances and resistances. An example of CMOS inverter with equivalent power grid and external ports’ parasitics is shown in Figure 4.

Simultaneous switching of digital gates produces transient current spikes which result in transient voltage drops in those inductive and resistive paths of supply lines. The voltage drops on the VDD and GND paths can be expressed by the following equation:

dt LdI RI

V_drop   (2)

where R and L are relevant parasitics. Equation 2 shows the resistive and inductive voltage drops increase as the switching current increases and its first derivative increases, respectively.

The second term, known as di/dt noise, also creates ringing in the parasitic RLC networks associated with power supply rails and output drivers [4]. Therefore, not only the local digital VDD and GND grids are not at their ideal voltages, but the grids in sensitive analog/RF parts in the same IC are affected due to the distribution of the coupled switching noise. If this ground grid is connected to the p-type substrate, this ground bounce will propagate directly to the substrate through ohmic contacts and parasitic junction capacitances. On the other hand, as the operating frequency increases with the technology shrinking, the di/dt noise increases;

therefore, larger noise spikes will couple through the resistance of substrate contacts, the capacitance of metal interconnects and the reverse-biased junction capacitors and cause more serious substrate coupling noise problems.

Figure 4 Switching coupling noise of an inverter to the analog/ RF parts in a IC through substrate [11].

2.3 Impact on Analog/Mixed-Signal/RF Circuits

Various researches have been done about the impact of substrate coupling noise on analog/mixed-signal/RF circuits, such as low noise amplifier (LNA) [15]-[18], voltage controlled oscillator (VCO) and phase lock loop (PLL) [19]-[25], analog-to-digital converter (ADC) [26]-[30], digital-to-analog converter (DAC) [31]-[33]. We will provide some survey on these.

2.3.1 Low Noise Amplifier

The influence of substrate noise coupling on the performance of a low-noise amplifier for a CMOS GPS receiver has been investigated both analytically and experimentally in [15].

It was shown that the spectral distribution of substrate noise greatly affects its impact in such a system. With the LNA as an example, both analysis and measurements indicate that substrate noise components located in specific frequency ranges can degrade the LNA performance.

As shown in Figure 5, the output spectrum of the LNA was measured under a 60dBm, 1.575GHz sinusoidal input. When a digital circuit emulator was activated with fclock = 39.825MHz, trise/fall = 0.9ns and fed to the substrate with a 32.6pF capacitor, the LNA output spectrum is seriously affected. It was proved in the paper that the noise tones are the results of digital switching noise at the harmonics of fclock and the intermodulation (IM) between the 1.575GHz RF signal and the substrate noise at fclock and its harmonics. It is also shown in the paper that the measured power of the largest IM tone in the LNA output is a function of the rise/fall time of the noise emulator, the substrate noise coupling capacitance value and the power of the substrate noise tone that causes this noise.

On the other hand, a frequency-domain approach has been presented in the paper to model both noise injections into the substrate from digital circuitry integrated on the same chip. The mechanisms about how that noise affects analog circuit behavior are also being presented. The results shown in this paper reveal that substrate noise can modulate the LNA input signal as well as couple directly to the amplifier’s output.

Figure 5 Measured LNA output spectrum: (a) without substrate noise injected. (b) with substrate noise injected. [15]

2.3.2 Oscillator

Oscillator is a very sensitive and common building block in a RF transceiver for the important role of generating the reference frequency for phase-locked loop. Substrate noise signal can couple to the oscillator and modulate the oscillator signal in both frequency and amplitude. This causes sideband spurs around the local frequency and its harmonics. Also, the noise signal can also directly couple to the output in a linear way without frequency modulation which also induces sideband spurs. Those sideband spurs around the local frequency degrade the phase noise performance of the oscillator thus is fatal to a wireless communication system.

Many papers have already been published to show the related issues of substrate noise effect on VCOs including [19]-[25]. Here we are going to show some important experiment results from them.

Figure 6 Differential output VCO phase noise degradation due to substrate noise. [20]

As presented in [20], a conventional 2.65 GHz differential LC-tank VCO and a digital circuit used as the substrate noise emulator with independent power supplies is fabricated on the same chip. When the on chip digital circuit is activated, the phase noise of the VCO degrades significantly. Figure 6 shows an example of this effect for a fclk=10MHz. Many spurs appear at the sidebands of the oscillator fundamental frequency f0 and destroy the phase noise performance. These spurs are originated from the substrate noise coupled to the analog

ground, then to each active devices and passives local substrate nodes in the VCO. The various spurs appearing in Fig. 6 are labeled according to its origin, classified as group A, B and C. For the spurs come from low frequency substrate noise harmonics up-converted from close to DC to close to f0 due to indirect AM to FM modulation, they are classified as group B.

For the spurs results from high frequency substrate noise harmonics converted from around f0 to phase noise sidebands, they are classified as group A and group C. Detailed analyses of the generation mechanisms of these groups can be found in the paper.

In short, it is proved that both noises at low frequencies and at high frequencies can significantly degrade the phase noise performance of a VCO. The low frequency substrate noise produces phase noise spurs at the output of VCOs due to resistive coupling between the injection point and the VCO ground followed by FM modulation. For the high frequency substrate noise harmonics, they result in additional spurs close to the VCO fundamental; the substrate noise harmonics around f0 are transformed into phase noise at the VCO output due to mixing with the second harmonic of the differential pair output current.

2.3.3 Analog-to-Digital Converter

Modern wireless communication systems are developing rapidly in recent years in order to fulfill the demands for high speed data transformation as in WLAN, WPAN, UWB and multimedia experiences in portable devices as in 3G and 4G systems. The increase of bandwidth in those communication systems requires not only ultra high frequency radio frequency blocks, but also very high speed interfaces as ADCs and DACs. In this part, we are going to reveal the substrate coupling noise effect on ADCs from previous studies.

There are many different kinds of ADCs such as flash ADC, successive-approximation ADC, integrating (multi-slope) ADC, pipeline ADC, oversampling (sigma-delta) ADC, etc…among those architectures, there are always digital building blocks included. Therefore, as the

operation frequency demand for an ADC increases, the substrate coupling between the analog and digital building blocks becomes an important role that limits its performance. Studies had been done for the effect of substrate coupling noise issue on an oversampling ADC [27] and a flash ADC [28].

In [27], experimental results of the switching noise effect in an oversampling sigma-delta modulator are presented. A test chip is fabricated in 1m CMOS technology including a third-order two-stage cascade modulator surrounded by eleven substrate noise emulators composed of tapered CMOS buffers that connected to the substrate via 6pF capacitors. The resulting substrate voltage fluctuations affect the transistors’ threshold voltage via body effect and directly capacitive coupled into the transistors’ gate, drain and source nodes in the modulator. The performance of the test circuit is evaluated by driving the analog input with a differential sinusoid, acquiring the 1-bit output code from each of the two stages, and transferring the acquired data to a work station for subsequent processing.

Figure 7 shows the experimental results of the output spectrum with and without the noise sources activated. The output spectrum with the noise sources off overlies the output spectrum with all of the noise sources activated. These measurements are taken with the rising edge of the noise clock occurring at the same time as the modulator sampling edge for a sinusoidal input level 10dB below overload. With no substrate noise, the SNDR and SNR are both 93dB. When the noise sources are activated, the SNDR and SNR drop to 52dB and 86dB, respectively. The performance decrease is due to the extra harmonics resulted from the injected substrate noise.

Figure 7 Output spectrum of a -10dB 2KHz input with/without noise sources activated. [27]

In [28], a 4-bit flash ADC is chosen to be investigated about the impact of substrate noise since normally the flash ADC can achieve highest operation speed among all types of ADCs.

However, due to the highest possible operation speed, flash ADC also suffers from the substrate coupling noise problem most. Among the building blocks in a flash ADC, comparators are normally the most critical ones which limit the overall accuracy and speed. In order to test the impact of noise on the regeneration time or decision of individual comparator blocks, a comparator is used in a toggling test structure, configured in a positive feedback loop hence oscillates with half of the clock frequency. The outputs of the comparator are

attenuated to the minimum resolution of the ADC before connecting them back to the inputs.

In this structure, the variation in the regeneration time of the latch can be observed as jitter in zero-crossing points of the toggling output. In order to investigate this problem, a flash ADC with two Digital Noise Emulators (DNEs) composed of chains of inverters that drive a large capacitance connected to the substrate is fabricated in 0.18um BiCMOS process.

The comparator’s output jitter versus noise frequency for two different clock frequencies are plotted in Figure 8(a), which is measured in time domain using the horizontal histogram in a digitizing oscilloscope to evaluate the impact of noise on the comparator decision time. As shown in the figure, as the noise frequency increases, the comparator’s jitter also increases;

and this problem become very serious for clock frequency higher than 100MHz. On the other

hand, in order to investigate the effect of distance on the sensitivity of a comparator block to substrate noise, the toggle test structure is tested separately with two DNEs on the chip. The comparator’s output jitter versus noise frequency for the two DNEs is plotted in Figure 8(b).

As shown in the figure, the closer DNE (DNE1) has significantly larger impact on the comparator than the farther ones. For example at 100MHz noise frequency, the comparator’s jitter due to DNE1 is twice larger than due to DNE2.

Figure 8 Comparator output jitter vs. noise frequency for (a) two clock frequencies, (b) DNEs at two different locations. [28]

Figure 9 SNDR of the ADC vs. noise frequency. [28]

To see the performance degradation due to substrate coupling noise on a flash ADC, both DNEs are turned on and the SNDR are measured at output. Incorrect codes are observed at the output that degrades the SNDR as shown in Figure 9, which SNDR of the ADC versus noise frequency for sampling speed of 262MHz at 5MHz input frequency are presented. The SNDR degradation is around 2 dB (10%) when noise frequencies are above 200MHz.

2.3.4 Digital-to-Analog Converter

In this part, we are going to reveal the substrate coupling noise effect on DACs from previous studies. As mentioned in last part, as the needs of high speed operation for modern wireless communication systems, high speed DACs and ADCs are demanded as interfaces.

For high speed DACs’ architectures, current-steering is the most popular one that are being used these years, for its highest achievable operation speed and moderate resolution. It is also a perfect candidate for the investigation of substrate coupling noise issue since it is composed of both the fast switching digital parts and the sensitive analog parts. In [32], the substrate coupling noise effect on a 14-bit 100MHz current-steering DAC implemented in 0.35m CMOS process on a high-resistivity p-substrate is investigated. Differential sensors are placed to measure the voltage between the positive power supply and ground nodes at the clock driver and DAC logic power supplies.

The substrate noise generated by the digital parts of the DAC is measured and proved to be the cause of glitches of several LSBs of amplitude at the output. As shown in Figure 10, the upper trace corresponds to the output of the single-ended substrate noise sensor and the lower graph to one of the DAC outputs for a few data samples around the cross-over of a full scale 500kHz sinusoidal generated with a 25MHz clock. The glitches appearing during the hold intervals of the DAC are due to noise produced by the input code changes. These changes generate substrate noise that is coupled to the DAC output just before the clock signal

switches. The clock switching generates also substrate noise that is coupled to the output.

To find the origin of the different noise components found in the substrate noise when the samples of a sinusoidal signals are applied to the DAC input, substrate noise is measured with the single-ended sensor in three different situations: first, the clock signal is applied to the DAC and the data inputs are held constant; secondly the data bits are switched and the clock signal is stopped, and finally, both data and clock are switched. The results of this experiment are shown in Figure 10 and can be explained as follows. The data changes generate di/dt noise at the digital power supply lines, which is directly coupled to the substrate by the digital substrate biasing contacts. Another source for noise coupling to the substrate is through the parasitic capacitances, which are mainly in the large pad area.

Figure 10 Substrate noise (upper trace) and output glitches (lower trace). [32]

Figure 10 Substrate noise (upper trace) and output glitches (lower trace). [32]