Implementation and results

As mentioned in 4.5.1.3, the high frequency performance of the proposed active guarding circuit is degraded mainly due to the poor ground plane resulting from the lack of parallel ground bonding wires on the test board. Therefore, in order to get rid of those unwanted loading effects, another tape-out is made and designed for on-wafer measurement with UMC

180nm Process. The layout and zoom-in view of the fabricated chip is shown in Figure 44.

Four different conditions are measured as following: A. The isolation performance in Control Group; B. The isolation performance in Experimental Group, without giving any DC voltage to the active guarding circuit; C. The isolation performance in Experimental Group, give only the DC bias voltages of Vbias1 in Figure 33, but doesn’t give the supply voltage to the active guarding circuit; D. The isolation performance in Experimental Group, give all the DC voltages needed for the full operation of the active guarding circuit.

Condition A is used as a reference, which measures the isolation performance of the substrate for two P+ diffusion pick-ups placed with 30m distance in between. As to Condition B and C, they are used to investigate the effect of the gate parasitic of transistor M1

(in Figure 33), which is used to decouple high frequency substrate noise, in combination with both isolation performance increased by the sense and injection rings. Finally, Condition D evaluates the overall performance of the proposed active guarding technique, including the circuit performance of the active guarding circuit and the physical protection of two rings of sense and injection. The simulation and measurement results of the conditions are shown in Figure 46 to Figure 48 and will be discussed below.

Figure 45 Test plans and measurement setup for the fabricated chip.

   

Figure 46 Isolation performances of condition A and D.

Figure 46 shows the simulation and measurement results of condition A and D in the Control and Experimental Groups. The isolation performance difference between the two conditions gives the absolute performance of the proposed active guarding technique in UMC 180nm process. As a result, the isolation performance of the proposed active guarding

technique is -18.65dB to -11dB with more than 20GHz bandwidth (from DC to more than 20GHz). The power consumption is around 2mA from 1.8V supply and the core size of the active guarding circuit is 20m x 40m.

   

Figure 47 Isolation performances of conditions A and B

   

Figure 48 Isolation performances of conditions A and C.

Moreover, in order to investigate the increasing behavior of the isolation performance shown in Fig. 46, as frequency gets higher than around 9GHz; conditions of A, B and C are measured and plotted in Figure 47 and Figure 48. As shown in the pictures, we can find that actually when frequency gets higher than around 2GHz; the isolation performance starts to be affected by the parasitic capacitance of the input transistor M1, which gives a decoupling ability that increases with the frequency. And as frequency goes higher than around 9GHz, the isolation performance will be dominated by the decoupling mechanism.

4.5.2.2 Performance Analyses and Summary

In this version, although an older CMOS technology as 180nm process is used rather than last version in 90nm process, the performance is much more improved due to a better designed ground plane. The proposed active guarding technique achieves 18.65dB to 11dB noise suppression performance from DC to more than 20GHz. In addition, different conditions are designed and tested to find out the performance contributions of the whole active guarding technique. As a result, we can find out that: first, around 7dB performance is contributed from Sense & Injection Ring. Second, the feed-forward compensation mechanism is only effective below few giga-hertz in this design. Last, from about 2GHz, the M1’s parasitic capacitance, Cgs, which is about 150fF starts to provide decoupling ability since its impedance approaches the low frequency input resistance 1/gm, which is about 100ohm.

The performance summary and comparison to our’s and others’ previous works is given in Table II. Characteristics of the power consumption, the circuit area and the wide suppression bandwidth of the proposed active guarding circuit are discussed below.

The power consumption of the proposed active guarding circuit can be expressed as equation (18).

   

ID4 based on the characteristic of current mirror. From Equation (6), given the substrate impedance Zin_sub, the circuit input impedance Zin_ckt (1/gm1 ) can be chosen according to a designed decoupling factor FD; and gm7 can be determined from Equation (11); also, (VGS1-Vt) and (VGS7-Vt) can be easily designed in the same value no matter what technology is chosen.

Therefore, all these design parameters for power consumption can be equally designed in any technologies (given that Zin_sub does not vary much in different technologies). Moreover, previous researches on CMOS transistors scaling effect [50] had concluded that the transconductance-to-current ratio, i.e. gm/ID is almost technology independent for saturated transistors. As a result, the current consumption of the proposed active guarding circuit is almost the same over different CMOS technologies and the power consumption is thus proportional to the supply voltage for different technologies. By comparing this work with the previous literature [45] of 0.13m process with 1.2V supply voltage, the normalized power consumption of this work (4mW/1.81.2 = 2.67mW) is much lower than that of [45]

(9.9mW).The main contribution of the small area comes from the architecture of the proposed active guarding circuit and can be even small in advance technologies since the chip area is highly related to the process. By comparing to [45], which requires 3 high gain amplifiers and three large capacitors, this work requires only eight active devices of MOS transistors, and no area-consuming high-gain, wideband amplifiers or capacitors is needed. Therefore, to the best of authors’ knowledge, this work achieves an area of 20m x 41m that is much smaller than any previous design. For the characteristic of wide noise suppression bandwidth, it is due to the bandwidth extension technique introduced in 4.3.2 to enhance noise suppression at giga-hertz frequency. To summarize, this work achieves the highest noise suppression

performance and widest noise suppression bandwidth with smallest area and moderate power consumption. The overall performance is achieved by the circuit architecture and mechanisms / techniques proposed. In addition, the proposed circuit benefits better performance and lower power consumption as the technology scaling down.

Table II

Performance Summary

4.6 Chapter Summary

In this chapter, the design details of the proposed active guarding technique are given, including noise decoupling mechanism and feed-forward compensation mechanism which performs the phase-inversion, amplitude control and bandwidth extension. Several chips were fabricated to verify the proposed technique. Experimental results show that by employing the active guarding technique, substrate noise can be effectively suppressed in a wide frequency range from DC to 20GHz with at least 11dB noise suppression performance, at the cost of 2mA current consumption from 1.8V supply and small core area as 20m x 40m.

In conclusion, this is the first active substrate noise suppression circuit with wideband characteristics that is ever proposed with measurement results. As shown in Table II, the area

requirement and power consumption are the smallest, comparing to any other previous works as referenced, to the best of authors’ knowledge. Moreover, the proposed circuit benefits better performance and lower power consumption as the technology scaling down. Therefore, the proposed active guarding circuit is very suitable for future applications in the industry of highly integrated SoC designs with continuous down-scaling CMOS technology.

Chapter 5

Application Verification

5.1 Introduction

In this chapter, we are going to demonstrate the proposed active guarding technique on a LC-tank oscillator. The reason to choose LC-tank oscillator as an application to verify the effectiveness of the active guarding technique is for its high sensitivity to noises and also for the common and important role of generating the reference frequency for phase-locked loop (PLL), which makes it one of the most crucial building blocks among a wireless communication system.

Two 180nm CMOS chips were fabricated for a complete experiment. The first one simply contains an active guarding circuit to evaluate the performance itself. The second chip integrates this active guarding circuit together with a LC-tank oscillator to verify the applicability for real applications. Sideband spurs and phase noise performance are measured to evaluate the effectiveness of the proposed technique.

The substrate noise coupling mechanism on a conventional LC-tank oscillator will first be briefly introduced. The experimental setup of the LC-tank oscillator with and without the protection of the active guarding technique will be explained later, along with implementation results. Chapter summary will be given in the end.

5.2 LC-Tank Oscillator and Substrate Coupling

Noise Mechanisms

A conventional complementary negative transconductance LC-tank oscillator is designed in this work, as shown in Figure 49. Substrate noise can couple into the oscillator through many ways, as from the p+ contacts that connect the substrate to the on-chip ground, the active devices’ back gates and also the components made of metal layers like inductors and capacitors. The dominant mechanism that converts substrate noise to the output of the LC-tank oscillator will be AM modulation of the bias transistor current due to the noise coupled to its ground. Both the AM sidebands from low frequency substrate noise harmonics and the impact of indirect AM to FM conversion due to the substrate noise on bias transistor are described in the following equation from [32]:

   

where is the substrate noise signal at, is the resonant frequency, Q is the quality factor of the tank, and are the current and transconductance of bias transistor, respectively.

Consequently, to minimize the substrate noise impact on the bias transistor that modulates the output of the oscillator, the active substrate noise suppression technique is applied to guard the bias transistors M1 and M2, thus the parameters of and (also ) of both transistors will be more stable to substrate noise. In addition, transistors M3 and M4 which composes the cross-coupled pair are also being protected, since they suffer from the substrate noise through their back gate that modulates their threshold voltages, too.

Figure 49 Schematic of the LC-tank oscillator.

5.3 LC-Tank Oscillator with Active Guarding Technique

As shown in Figure 50, an active guarding circuit and a LC-tank oscillator are integrated in a single chip to evaluate the effectiveness of the proposed technique on real applications.

The LC-tank oscillator is verified with measurement results to operate at 1GHz and offers a phase noise performance of more than -95dBc/Hz at 100kHz offset frequency. It consumes 1.1mA from a 1.8V supply.

Two different kinds of noise sources are applied for the experiment. Noise source 1 (NS1) injects single tone signals from an external source as signal generator into the substrate through substrate taps, with 15m distance from the guarded devices. Noise source 2 (NS2) is the digital signal output from an on-chip inverter chain, which is commonly used as clock buffers, for the emulation of the substrate noise source in practical cases. The output of the inverter chain is fed to the substrate with 25m distance from the guarded devices, through a 5pF capacitor to pass signals below several giga-hertz and also to block the DC signal from interfering the substrate. Noise frequencies of either low as 100kHz to 10MHz or high as

around the resonant frequency of 1GHz are injected to the substrate to see the impact of substrate coupling and the suppression ability of the active guarding circuit.

Figure 50 Layout and zoom-in view of the fabricated chip.

DC Pads

Input Pads

NS2

Injection DC

Pads

Output Pads Active Guarding

Circuit Guarded

Active Devices

Inverter Chain

NS1 Injection

Power Supply Power Supply

Signal Generator

Signal Source Analyzer

5.4 Implementation and Results

To evaluate the effectiveness of the active guarding technique on LC-tank oscillator, the phase noise and sideband spurs are measured under three different conditions as follows:

 Original: The active guarding circuit is off and no noise is injected.

 CKT-OFF: The active guarding circuit is off and noise is injected either from NS1 or NS2.

 CKT-ON: The active guarding circuit is on and noise is injected either from NS1 or NS2.

The performance of the active guarding technique is obtained by comparing the performance differences between Original, CKT-OFF and CKT-ON for noise injections of various frequencies. For low frequency range of interested, experimental results of 100 KHz and 10 MHz single tone noise injections from NS1 with -5 dBm input power are presented from Figure 52 to Figure 57 as examples. As shown in Figure 52, the original phase noise at 100kHz is -98.59dBc/Hz. After a single tone noise at 100kHz is injected from NS1, a corresponding spurs at 100kHz offset showed and the phase noise performance becomes -69.66dBc/Hz at 100kHz, as shown in Figure 53. By switching the active guarding circuit on, the phase noise performance at 100kHz becomes -88.47dBc/Hz in Figure 54, which shows an 18.81dB improvement. Figure 55 shows another measurement with around -142dBc/Hz original phase noise at 10MHz. After a single tone noise at 10MHz is injected from NS1, a corresponding spurs at 10MHz offset showed and the phase noise performance becomes -117.29dBc/Hz at 10MHz, as shown in Figure 56. By switching the active guarding circuit on, the phase noise performance at 10MHz becomes -134.02dBc/Hz in Figure 57, which shows a 16.73dB improvement. To be mentioned, two spurs in 60kHz and 70kHz in Figure 52 to Figure 57 are not resulting from substrate noise therefore cannot be suppressed. Similar results are obtained for noise frequencies between 100kHz to 10MHz.

For high frequency experiments, here we show a result of the noise injection from NS2 as an example since the phase noise degradations due to the injections of digital noise are more severe than single tone noise for the same frequencies. A 990MHz high frequency noise, which is close to the resonant frequency of the oscillator, is injected to the substrate from NS2 as a digital noise to see the phase noise performance difference. Noise amplitude which reaches the guarded devices in the oscillator is calculated to be around 30mV to emulate the actual possible substrate noise.

Wireless standard of DCS-1800 is chosen as an example application for the oscillator design thus both transmission (Tx) and reception (Rx) spurious suppression specifications calculated in [51] are being plotted in Figure 58 for comparison. As shown in the figure, the oscillator output is suffered from AM/FM modulations and the puling effect by the injected noise that the phase noise performance are degraded seriously therefore failed to fulfill the mask specifications of both Rx and Tx, from offset frequencies of 500kHz and 1.1MHz, respectively. After the active guarding circuit is switched on, the pulling effect is reduced hence the phase noise performances are improved substantially to pass both Tx and Rx spurious suppression masks in the whole frequency range of interest.

Figure 52 Measurement results – without noise injection.

Figure 53 Measurement results – 100kHz noise injection, circuit off.

Figure 54 Measurement results – 100kHz noise injection, circuit on.

Original –

Without Noise Injection

100kHz_Noise – CKT_OFF

-69.66 dBc/Hz

-88.47 dBc/Hz

100kHz_Noise – CKT_ON

Figure 55 Measurement results – without noise injection.

Figure 56 Measurement results – 10MHz noise injection, circuit off.

Figure 57 Measurement results – 10MHz noise injection, circuit on.

Original –

Without Noise Injection

10MHz_Noise -CKT_OFF

-117.29 dBc/Hz

10MHz_Noise -CKT_ON

-134.02 dBc/Hz

Figure 58 Comparison of the phase noise differences among the Original/CKT-ON/CKT-OFF after 990MHz noise injection from NS2 with DCS-1800 spurious suppression masks.

5.5 Chapter Summary

In this chapter, we demonstrate the active guarding technique to improve the substrate noise immunity on analog/RF circuits with real application. By applying the active guarding circuit to a LC-tank oscillator, more than 16.73dB spur suppression performance is obtained in the frequency range of interest as either low frequencies below 10MHz or high frequencies around the resonant frequency of 1GHz. As a result, the 1GHz oscillator can fulfill the spurious suppression masks of DCS-1800 even in the adjacent of 990MHz strong noise signals.

10³ 10⁴ 10⁵ 10⁶ 10⁷

-150 -100 -50 0 50

Offest Frequency (Hz)

Phase Noise (dBc/Hz)

DCS-1800 spurious suppression mask (Tx) DCS-1800 spurious suppression mask (Rx) Original

CKT-OFF with 990 MHz Noise injection CKT-ON with 990 MHz Noise injection

Chapter 6

Conclusions and Future Works

This dissertation presents a new active guarding technique for wideband substrate coupling noise suppression in SoC applications. We surveyed on substrate noise issue in mixed-signal integrated circuits. The generation and propagation mechanisms of substrate noise are briefly introduced; the experimental results of substrate coupling noise impact on analog/nixed-signal and RF circuits including LNA, Oscillator, ADC and DAC selected from other people’s works are also presented to show the performance degradations in real cases.

After knowing the seriousness of substrate coupling noise problem, we also investigated on substrate coupling noise suppression techniques. Existing techniques are classified into passive and active methods; for passive methods, test-keys of different guard ring schemes are designed, fabricated and measured to see the effectiveness of the conventional physical methods. Substrate characterization is also done for further utilizations. For active methods, we selected five different techniques from published papers, showed their way of implementation and then made comparisons. In the end, we proposed a new technique that takes both the advantages of passive and active methods, which includes noise decoupling and feed-forward compensation mechanisms. The detailed of design, analyses and implementation of this technique are given. By employing this technique, wideband substrate noise suppression up to giga-hertz range can be achieved. The final circuit implementation results in UMC 180nm CMOS technology show that more than 14dB noise suppression performance is achieved in a wide frequency range from DC to 1GHz and 11dB until 20GHz, by the cost of a small chip area of 20m x 40m and 2mA current consumption from a 1.8V supply. This is

the first active substrate noise suppression circuit with wideband characteristics that is ever proposed with measurement results. Moreover, the proposed technique benefits better performance and lower power consumption as the technology scaling down. Therefore, the active guarding circuit is very suitable for future applications in the industry of highly integrated SoC designs with continuous down-scaling CMOS technology. To prove the feasibility on real applications, the proposed active guarding technique is demonstrated for substrate immunity improvement on LC-tank oscillators. Experimental results showed that by applying the active guarding technique to a LC-tank oscillator, more than 16.73dB spur suppression performance is obtained in the frequency range of interest as either low frequencies below 10MHz or high frequencies around the resonant frequency of 1GHz. As a result, the 1GHz oscillator can fulfill the spurious suppression masks of DCS-1800 even in the adjacent of 990MHz strong noise signals.

We have presented a new technique for wideband substrate noise suppression with best performance among the previously published papers. However, the drawback to use this technique is: the design of an active guarding circuit always needs a parameter extracted from the substrate. As shown in Equation (6), (8) and (11), the design of the decoupling factor and the amplitude controller depends on the parameter Zin_sub, which is extracted from the substrate. Consequently, if a user wants to design an active guarding circuit for a certain technology, they need to get the substrate model first. In our case, we have cooperation with

We have presented a new technique for wideband substrate noise suppression with best performance among the previously published papers. However, the drawback to use this technique is: the design of an active guarding circuit always needs a parameter extracted from the substrate. As shown in Equation (6), (8) and (11), the design of the decoupling factor and the amplitude controller depends on the parameter Zin_sub, which is extracted from the substrate. Consequently, if a user wants to design an active guarding circuit for a certain technology, they need to get the substrate model first. In our case, we have cooperation with

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