Overview of this Dissertation

We developed the controller chips design for the high-speed high-capacity solid-state drive. The solid-state drive is a quite important I/O device for the mass data storage in the mobile computers. The more advanced controller chip architecture and design for the high-speed high-capacity solid-state drive is necessary for covering the deficiencies of the more advanced high-density NAND flash memory. Although the continuously rapid process technology shrinking and the novel MLC (Multi-Level Cell) technology has increased the bit density of NAND flash memory dramatically, meanwhile it generates the higher BER (Bit Error Rate) during the data accessing, much

less program / erase endurance cycles, and more severe disturbances and interferences during the operation of reading, programming, and erasing of the NAND flash memory.

The presented stronger controller architecture is required to overcome such difficulties or deficiencies as using the advanced high-density NAND flash memory to compose a high-speed and high-capacity solid-state drive. The chips implementations and experiments show the effectiveness and good performance of the controller architectures we presented.

In this dissertation, the key architectures of the controller chip design for high-speed high-capacity solid-state drive have been investigated and developed. We presented: the t-EC w-bit parallel BCH (Bose-Chaudhuri-Hocquengham) ECC (Error-Correction Code) construction for covering the higher bit error rate of the advanced high-density NAND Flash memory, the multi-mode BCH ECC for hybrid multi-channel flash memory storage system, which can provide the optimal cost-performance by combining the different characteristics among different kinds of flash memory devices, the high efficient hardware architecture to provide the guaranteed maximum bandwidth utilization of the host interface even though the single flash memory device accessing speed is quite limited, the hardware accelerator based CPRM (Content Protection for Recordable Media) implementation to provide the content protection of the stored data in the solid-state drive, and the configurations of hybrid multi-channel non-volatile solid-state memory array and its controller architecture to gain more excellent performance and reliability as combining with the other types of non-volatile solid-state memory.

A t-EC w-bit parallel BCH (Bose-Chaudhuri-Hocquengham) ECC (Error Correction Code) was invented and constructed to cover the higher innate bit error rate of the advanced high-density NAND flash memory. The higher bit error rate requires stronger error correction capability of the BCH ECC circuit, while it increases the complexity of the BCH ECC circuit design. The inherent parallel page-wise accessing

of NAND Flash memory requires the parallel data I/O of the data accessing. The general w-bit parallel provides the most flexibility as designing the ECC circuit for NAND flash memory. The systematic construction procedure of the t-EC w-bit parallel BCH ECC by using the systolic array architecture was presented, which help reduce the design cycle time and the efficiency of the ECC circuit.

To support the hybrid multi-channel flash memory storage systems, a multi-mode BCH ECC circuit architecture was constructed. The hybrid multi-channel Flash memory array was presented to provide the optimal cost-performance for a high-speed and high-capacity solid-state drive by using multiple types of NAND flash memory. The separated ECC encoder / decoder module and the error corrector module are suitable for the flexible data flow control as supporting the multi-channel flash memory storage systems. The presented multi-mode BCH ECC circuit architecture shows the lower cost and lower power consumption for the solid-state drive controller chips design.

The high efficient hardware architecture for data buffering and transmitting was presented to provide the guaranteed maximum bandwidth utilization for the data transportation between the host system and the flash memory array regardless the very restricted data accessing speed in reading, programming, and erasing of a single flash memory device. The hardware architecture for high efficient data transportation contains: the buffer RAM and the buffer manager, the TD–based (Transfer Descriptor based) flash memory sequencer, and the hybrid multi-channel flash memory array. The buffer RAM and the buffer manager was established with the enough bandwidth to satisfy the bandwidth of host interface defined in the specification. The enough bandwidth of the buffer RAM and buffer manager was constructed by the efficient DMA (Direct Memory Access) mechanism and multi-buffering by sharing the buffer RAM in spatial or timing windowing. The TD-based flash sequencer is composed of TD buffer, TD processor, and the flash memory access controller. The TD-based flash sequencer was designed to do the high efficient data accessing of the NAND flash

memory array. The hybrid multi-channel flash memory array architecture was presented and composed by multiple flash memory devices. The hybrid composition of flash memory array can provide the optimal cost-performance combination. For example, SLC (Single-Level Cell) with higher performance and good endurance, MLC (Multi-Level Cell) with lower cost and higher density, an efficient management on them can have the optimal overall system level cost-performance. The multi-channel architecture of flash memory array provides the parallelism to increase the data accessing speed as at the flash memory side.

The hardware accelerator based architecture of the CPRM implementation provides an efficient data security of the content data stored in the solid-state drive. The CPRM was developed by the 4C entity LLC (http://www.4centity.com/) for an efficient digital content protection of digital data exchange among the digital information appliances [26-27]. The hardware accelerator based architecture can be used with a MCU (Micro-Controller Unit). The hardware accelerators are working to help the data processing as the micro-controller is doing the AKE (Authentication Keys Exchange) process and the secure read / write process defined in the CPRM specification. The architecture provides the high efficiency, high flexibility, low cost, and low power consumption for the supporting of the CPRM functions.

Besides the high-density NAND flash memory, there are other kinds of non-volatile solid-state memory, which have more excellent accessing speed, higher endurances, and longer data retention time than the advanced high-density NAND flash memory, such as: FeRAM (Ferroelectric RAM) [100], MRAM (Magneto-resistive RAM) [101], PRAM (Phase-changed RAM) [102]. Their excellence performance can be used to compensate the poor endurance, and long erase / program time of the high-density NAND flash memory by composing the hybrid non-volatile solid-state storage systems. The presented hybrid non-volatile solid-state memory array structure and its controller architecture attain the optimal cost-performance consequence by

leveraging the different characteristics among different kinds of non-volatile solid-state memory.

Finally, we have the chips implementation and experiments on the flash memory controllers design. We illustrated implementations and experiments of 3 designed flash memory controllers to show the effectiveness and performance results of controller chip design architecture we presented. The three implemented flash memory controllers are:

a NAND flash memory controller for SD/MMC card, a NAND flash memory controller of dual-mode USB flash card for low-power mobile devices, and a NAND flash memory controller for SATA II solid-state drive. The calculated performance of a 120GB SATA II solid-state drive is summarized as: 230MB/sec in reading, and 205MB/sec in writing. In the ending of this dissertation, conclusions and future works discussions give us the directions for doing the next steps.