ECC (Error Correction Code)

The Error Correction Code is used to increase the data integrity by adding some redundant information [2-3]. A FEC (Forward Error Correction) mechanism can do the error correction independently at the receiver side. The data stored in the storage media is like the data transferred through a communication channel. The defect and the disturbances in the NAND flash memory operation is analogues to the noisy in a communication channel. In Figure 2-6, there is the NAND flash memory is used to store the data. The data written to the NAND flash memory and read back is similar to the data is sent from a transmitter to a receiver in the communication channel. The source data is the data to be written to the NAND flash memory, and the drain data is the data

read back from the NAND flash memory. The ECC encoder generates the ECC parities as the redundancy of the user data which can be decoded by the ECC decoder. The ECC decoder can do the ECC decoding and check if the received is error-free or corrupted by noise. If the corrupted data is received, the ECC decoder will do the error correction by finding the error locations and the corresponding error patterns.

In practical, the ECC circuit was used to lower down the BER (Bit Error Rate) to be the lower bound of acceptability, thus let the whole system data integrity can meet the required specification. For example, the BER should be less than 10^-15 as a data storage device for computer systems.

Figure 2-6. Illustration of ECC in the NAND flash memory storage.

There are some famous algebraic codes for doing the error correction in a memory-less communication channel. The RS (Reed-Solomon) Code is designed for the data error correction of burst errors. RS code is widely adopted in Hard Disk Drive

and Optical Disk Drive industry. The BCH codes are used to correct the randomly happened errors in many systems. “BCH” is a name for the 3 historic mathematicians:

Bose, Chaudhuri, and Hocquengham. The BCH code is very suitable for the error correction for the randomly bit errors in the NAND flash memory, since the noise model of the NAND flash memory is the randomly bit error. In addition, the smaller redundant area requirement for the same EC (Error-Correction Capability) level compare to RS code make BCH is more suitable for the ECC strategy in NAND flash memory storage systems. In Table 2-IV shows the comparison between the BCH code and the RS code.

Table 2-IV. Comparisons between the BCH code and the RS code Items

BCH Code RS Code

Errors Correction Random Bit Error Burst Errors

Operation Unit Binary Non-binary (Symbol)

Encode Architecture

Long Cascade Shift Registers Parallel Symbol-base Registers

Decode Architecture

․ Syndrome Generators

․ Syndrome to Error Locator Polynomial

․ Chien’s Search

․ Error Correction

․ Syndrome Generators

․ Syndrome to Error Locator Polynomial

․ Chien’s Search

․ Error Patterns Evaluation

․ Error Correction

Application

The parity-check matrix is defined for the linear systematic block for t-error correction capability as below [3]:

⎥⎥

From the further induction of parity-check matrix, the generator polynomial of the general t-EC (t-error correction) BCH ECC code can be expressed as:

∏

While the generator polynomial of a general t-SC (t-symbol Correction) Reed-Solomon ECC code can be expressed as:

∏

Where α in equation (2-4) is the primitive element of GF(2^m).

ndromes will be gotten by the decoding of BCH and Reed-Solomon ECC codes.

3(x), …, S2t-1(x)) by the following minimal polynomials m1(x), m3(x), m5(x), …, m2t-1(x).

Both the BCH and Reed-Solomon ECC use the generator polynomial to generate the ECC parity for errors checking and correction redundancy. If the data is error-free, the all zero values of Sy

The decoding process of BCH ECC is done by doing the polynomial divisions and finding the remainder polynomial as the corresponding syndrome (S1(x), S

));

Where, the c(x) in equation (2-5) is the polynomial of the received code word.

The decoding process of Reed-Solomon ECC is done by doing the polynomial divisions and finding the remainder polynomial as the corresponding syndrome (S1(x), S2(x), …, S2t(x)) by the following polynomials: (x-α¹), (x-α²), …, (x-α^2t).

Where, the c(x) in equation (2-6) is the polynomial of the received code word.

If the received code word is corrupted by noise, the non-zero of syndromes will be decoded. The next step of both BCH and Reed-Solomon ECC is to find the error locator polynomial by solving the key equation. The key equation can be solved by the Berlekamp-Massey Algorithm [2]. The general format of an error locator polynomial for finding u errors is shown in equation (2-7).

∑

Where, the σi in the equation (2-7) is called the coefficients of the error location polynomial.

To find the error locations, the iteration for x = αⁱ evaluating is processed. This process is called the Chien’s Search. After finding the all of the error locations of the corrupted received code word, the bit error correction process of the BCH ECC code can be finished by doing the bit-inversion operation at the found error locations. While

the Reed-Solomon ECC due to its symbol-base ECC code, it needs to find the error patterns at the corresponding error locations. The process is called as the error pattern evaluation.

There are 3 possible results after the decoding of the received data code word. Case (i), if all of the syndromes are all zero, the error-free of the received data code word result is judged. Case (ii), if the error locations and error patterns can be found and consistent with the mathematical formula, the correctable errors of the received data code word result is judged. The third condition is happened while none of the case (i) or case (ii). It is called as the un-correctable data error.

The ECC circuit architecture for BCH and RS code is quite similar. The RS code can be regarded as an extension of BCH code to a symbol base error correction code.

Both of the BCH and RS code are in the class of cyclic linear block code. Figure 2-7 shows the general architecture for the BCH and RS ECC circuit. The ECC Registers are used to store the temporary data during the ECC encoding, ECC decoding, and finding the error locations and calculating error patterns. The key equation solver is designed to do the syndrome to error locator polynomial; the Berlekamp-Massey algorithm was constructed to do the operation. The error searcher is designed for finding the error locations by evaluating the error locator polynomial. Such evaluation of error locator polynomial is also called the Chien’s search algorithm. For the BCH ECC case, the corrector FSM (Finite State Machine) just doing the bit-inversion of the found error locations. For the RS ECC, there needs an operation to find the error pattern of each found error location, because RS is the symbol-base ECC code.

Figure 2-7. General architecture of ECC circuit.