Related Works

The controller chip design for solid-state drive has been developed for over 30 years. The related works of solid-state drive are the ECC circuit design for storage systems, the VLSI circuit architecture, the data security mechanism for content protection, the parallelism of multiple storage devices array, and hybrid multi-channel non-volatile solid-state memory devices.

The FEC (Forward Error Correction) is usually demanded for ensuring reliable data transmission in noisy communication channels, while maintaining a good system performance. There have been already a lot of algebraic ECC codes proposed for FEC purpose, in which the cyclic attribute of the BCH (Bose-Chaudhuri-Hocquenghem) code makes an easy adoption for hardware circuit implementation and has become a common choice in most applications [2-3]. Different from the BCH code is suitable for correcting random bit errors, the derivative RS (Reed-Solomon) code was developed for burst errors correction. Both codes are of similar mathematical fundamentals, while the RS code can be regarded as an extension of the BCH code to be a non-binary, symbol-base operation. Nowadays, many applications adopt BCH or RS code as a standard ECC (Error Correction Code), for example, CD (Compact Disc), DVD (Digital Versatile Disc), HDD (Hard Disk Drive), ether-net, wireless communications,

etc. The parallel data I/O bus (×8 or ×16) of a NAND flash chip thus requires a parallel I/O BCH ECC codec, applied the parallel CRC (Cyclic Redundancy Check) concept was proposed by Zukowski [62]. A longer encoder polynomial for BCH code is spontaneous to have a stronger bit error correction capability. Some high speed architectures were presented by K. K. Parhi, et al [63-64, 66]. Also, Jun Zhang et al presented an optimized architecture for the long parallel BCH encoder [65]. In addition to the long encoder issue, there were time and power consumption issues solved by Chien’s Search for error location [66-67]. These prior researches provide a formulated basis for a parallel BCH ECC code and circuit implementation.

The VLSI circuit design for micro-electronic technology has also been developed since 1980s [5-8, 37]. The smaller feature size of the semiconductor technology, the more transistors can be put on in a single chip. Thus, it also pushes the progressing of VLSI design techniques. In the highly regular and iterative VLSI architecture, the systolic array processors were introduced for the architecture and timing design by projection. The systolic array architecture has been applied to RS encoders and decoders, and showed good performance [68-70]. The systematic design approach of a systolic array processor can make the circuit design easy for implementation and easy for pipelining to fit the system level design specifications.

The rapid progressing in technology shrinking and the development of MLC (Multi-Level Cell) technology of NAND flash memory have increased the bit density and lowered the cost per MB of flash memory. The bit density of NAND flash memory was doubled per 12 months in the past decade. Nevertheless, the higher density of the NAND flash memory causes the poor performances and less endurance. The cost per MB versus to the performance and reliability of NAND flash memory has become a trade-off. In order to recover the performances and endurances loss of the higher density of the NAND flash memory, there are different strategies introduced to cover the degradation of advanced high-density NAND Flash memory [1, 47-51].

In the data cryptography, there are publications presented for discussing the data encryption and decryption, and public key cryptography algorithm design [4, 25, 36, 91-93, 108]. For example, the popular cryptography mechanism as: DES (Data Encryption Standard) algorithm, RSA (stands for the names of the 3 inventors: Rivest, Shamir, and Adleman) algorithm, and ECC (Elliptic Curve Cryptography) algorithm are developed to increase the difficulties to crack the encrypted data and decrease the probability of the secure data been destroyed. In the history of developing of cryptography, the public-key cryptography might be the most important discovery.

Moreover, we can say it might be the only one revolution from the long years “classic”

cryptography into the “modern” cryptography. From the classic cryptography development point of view, almost all of the cryptosystems are using the fundamental data scrambling, symbol replacement, and data harsh function. There was a famous data encryption code developed in IBM laboratory, called Lucifer algorithm, it became a USA national standard of data encryption codes, called as DES. Besides the algorithm development of cryptosystems, there are some hardware circuit implementation have been presented [94-96]. The high-speed VLSI circuit architecture has been discussed to satisfy the increasing of computation due to more secure functions required for the demands of data portability. To increase the generality and flexibility of the hardware based VLSI processor for cryptography, there are scalable design architecture presented [97-99]. The scalability of the VLSI cryptography process provides the programmability of the circuit as using by a micro-processor, or a micro-controller.

To increase the data accessing or processing speed, the parallelism of computer architecture was developed [38]. The efficient computer architecture of parallelism, for example the pipelining, parallel structure, or super-scalar, can be implemented by VLSI techniques for the controller chips design of solid-state drive. The high efficient hardware architecture design can provide the enough data transportation bandwidth during the data transfer between the host system and storage device. To increase the accessing speed and to provide data redundancy of the data storage devices, the RAID

(Redundant Array of Inexpensive Disks) technology was introduced [35]. The RAID level-0 can boost the higher data transfer by data block stripping. The RAID level-1 protects the data stored in the storage system by mirroring the data. The RAID level-5 provides the more utilization rate of the data storage capacity to provide the data parity redundant protection by n storage devices with the ratio of (n-1)/n.

There are several kinds of solid-state memory used in the computer, communication, industrial devices, car electronics, and consumer electronics, besides the NAND flash memory. Memory devices can be divided as the volatile memory type and the non-volatile memory type. The volatile memory is using for data storage as the device is powered, while the non-volatile memory can keep the data even if the power is off. The major volatile memory types are the DRAM and SRAM. Besides the NAND flash memory as the storage media for the mass data storage devices, there are other kinds of non-volatile solid-state memory device which has different characteristics of the memory cell. Such as FeRAM (Ferroelectric RAM, or called FRAM), which can offers a number of advantages, notably lower power usage, faster write speed and a much greater maximum number (exceeding 10¹⁶ for 3.3 V devices) of write-erase cycles [100], MRAM (Magneto-resistive Random Access Memory) which are using the magnetic element for storing bits, thus can have the almost un-limited endurance cycles and write the data without do the erase in advance [101], and PC-RAM (Phase-Change RAM, or called PRAM) with its fast performance and high endurance for write cycles and data retention life span [102]. The different characteristics among these non-volatile solid-state memory devices can be combined together and formed a hybrid solid-state storage system, which can provide an optimization of cost, performance, and reliability in the system level point of view.

The Sandisk Corp. (http://www.sadisk.com/) and M-systems are the pioneers in the flash storage devices. Now they are the same company since the December 2006, Sandisk acquired the company of M-Systems. In 2007, the solid-state drive related

products are very fruitful, and the related technology discussions and conferences, papers, patents are growing significantly. There are more than 50 companies (e.g., Sandisk, Simple Tech, Silicon Systems, A-Data, PQI, etc.) have solid-state drive products. The “Solid State Disks (SSDs) - all technologies” web-site shows the open-site articles, products information, and test reports for the solid-state drives (http://www.storagesearch.com/ssd.html). According to the survey on world-wide web, the current solid-state drives shown are: all using the SLC types NAND flash memory with 1-EC or 4-EC ECC circuit; the current available capacity of the solid-state drive is in range from 32GB to 160 GB; the host interfaces adopted are: SATA (Serial ATA), PATA (Parallel ATA, or IDE), SCSI, S-SCSI (Serial SCSI), iSCSI (Internet SCSI), FC (Fibre-Channel); the data transfer rate is from 40MB/sec to 180MB/sec depends on the application fields.