The gate-level simulation of the UWB baseband processor including the proposed high-speed channel equalizer has been completed. The developed UWB baseband processor comprises an OFDM modem and a LDPC FEC design, which provides three data rate including 120Mbits/s, 240Mbits/s and 480Mbits/s in 528MHz baseband bandwidth. The required 528Msymbol/s throughput of UWB specification can be achieved by using two parallel channel equalizers with operating clock rate equals to 264MHz. The gate count is 46.2K, which is 18.48% of the total gate count of the OFDM modem (250K).
Chapter 7 .
Conclusion and Future Work
After the algorithm illustration and performance analysis, the proposed channel equalizer is robust to solve multipath fading, CFO, and SCO due to the algorithm improvement and the combination of DDCE and PET. In the proposed CE, equalization error can be reduced efficiently by the novel data-aided tracking algorithm. In the proposed PET, a full tracking range can be achieved by the pilot pre-compensation scheme, and the tracking accuracy can be enhanced by the applied fixed-coefficient loop filters. With the proposed design, multipath fading, CFO and SCO can be eliminated simultaneously with channel equalization, which reduces the compensation complexity compared with former approaches. In performance measurement, the proposed CE achieves (i) 9~13dB gain in MSE compared with zero forcing CE, (ii) 2.0~13.9 dB gain in MSE compared with fixed-coefficient LMMSE CE. The proposed PET achieves a better 1.9~2.3dB gain in SNR for 10% PET compared with conventional approaches. Applying the proposed channel equalizer, the IEEE 802.11a baseband processor achieves 1.35~7.16dB average gain in SNR compared with current approaches and the standard requirement.
A high-speed and low-complexity phase-domain channel equalizer is proposed based on the previous algorithm with coordinate conversion. The proposed modified algorithm can achieve the same performance of conventional zero forcing with lower than 50% of the computation complexity. In hardware implementation, the gate count is 46.2K with maximum throughput of 554Msymbol/s, which is 50% of the hardware cost, ten times of the operation clock rate compared with conventional zero forcing approach.
In this thesis, we focus on indoor OFDM-based wireless access systems. The applied wireless channel model is relatively simple compared with outdoor, mobile systems. In the future, OFDM may be widely applied in mobile communications, which has a much more complicated transmission environment. Therefore, a more robust synchronization scheme including channel estimation, CFO and SCO compensation will certainly be needed to further explore in the future.
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Vita
姓 名： 俞 壹 馨 出 生 地： 台灣省花蓮縣 出生日期： 1980. 2. 9
學 歷： 2002. 9～2004. 6 國立交通大學 電子研究所系統組 碩士 (Si2 Lab) 1998. 9～2002. 6 國立交通大學 電子工程學系 學士
1995. 9～1998. 6 國立花蓮女子高級中學 1992. 9～1995. 6 花蓮縣立美崙國民中學
1986. 9～1992. 6 國立花蓮師範學院附設實驗國民小學
得獎事蹟： 91 學年度 第二學期電子研究所書卷獎
91 學年度 教育部 IC 設計競賽研究所／大學部 Cell base 組設計完整 90 學年度 殷之同專題計劃／成果獎學金
90 學年度 教育部 IC 設計競賽大學部 Full Custom 組優等 89 學年度 第二學期電子工程學系書卷獎
發表論文： [1] Yi-Hsin Yu, Hsuan-Yu Liu, Terng-Yin Hsu, and Chen-Yi Lee, “A Joint Scheme of Decision-Directed Channel Estimation and Weighted-average Phase Error Tracking for OFDM WLAN Systems,” APCCAS 2004 [2] Hsuan-Yu Liu, Yi-Hsin Yu, Chien-Ching Lin, Ching-Che Chung, Terng-Yin
Hsu, and Chen-Yi Lee, “A COFDM Baseband Processor with Robust Synchronization for High-Speed WLAN Applications,” Symposium on VLSI Circuits 2004.
[3] Hsuan-Yu Liu, Yi-Hsin Yu, Chien-Jen Hung, Terng-Yin Hsu, Chen-Yi Lee
“Combining Adaptive Smoothing and Decision-Directed Channel Estimation Schemes for OFDM WLAN Systems,” ISCAS 2003.