5.2 P ERFORMANCE A NALYSIS OF THE P ROPOSED C HANNEL E QUALIZER FOR UWB
5.2.3 Deep Fading Analysis
The deep fading subcarriers are seriously distorted by additive noise. A geometric average method with a deep fading detection scheme is applied to enhance system performance. The CFR power ratio (CFRsmall CFRbig ) of the duplicated subcarriers is measured. In figure 5.2.2, we can discover that the power ratios are close to “1” in correct packets. In error packets, the amount of small power ratios increase, deep fading may occur.
Figure 5.2.2 The power ratio distribution
We can decide the threshold value of deep fading subcarriers by the power ratio distribution.
From figure 5.2.3, the proposed geometric average method with deep fading detection achieves a better 1.3dB gain in SNR than the general average method without deep fading detection.
Figure 5.2.3 PER of the proposed deep fading detection (th=0.7)
5.2.4 System Performance
Figure 5.2.4 PER performance of the proposed UWB PHY
To verify the complete system performance of the proposed channel equalizer, a complete TFI-OFDM UWB PHY with a Low-Density Parity Check code (LDPC) in FEC is
established. LDPC achieves a better 2.0dB gain in SNR compared with the Viterbi encoder.
There is no puncturing in the LDPC scheme, only a fixed coding rate (3/4) can be supported.
Therefore, the supported data rates of the proposed UWB PHY are 120, 240, and 480Mbits/s.
PER curves are simulated under Intel channel model with 5ns RMS delay spread, 40ppm CFO, and 40ppm SCO. The simulation result can be shown in Figure 5.2.4
5.3 Summary
In the performance analysis of the proposed channel equalizer for general wireless access systems, the proposed DDCE achieves (i) 9~13dB gain in MSE compared with ZF CE, (ii) 2.0~13.9 dB gain in MSE compared with fixed-coefficient LMMSE CE [10]. The proposed PET achieves a better 1.9~2.3dB gain in SNR for 10% PER compared with conventional approaches [5]. Applying the proposed channel equalizer, the IEEE 802.11a baseband processor achieves 1.35~7.16dB average gain in SNR compared with current approaches and the standard requirement [12][13].
In the proposed high-speed and low-complexity channel equalizer, the PER performance is slightly better than conventional complex ZF approach with less than 50% of the computation complexity. The proposed deep fading detect scheme achieves a better 1.0~1.3dB gain in SNR than the conventional blind average method. Applying the proposed channel equalizer with coordinate conversion, the requirement of performance, high-speed, and low-complexity can be achieved in the UWB baseband processor.
Chapter 6 .
Hardware Implementation
In this chapter, we will introduce the platform based design flow. The architecture of the proposed design, hardware synthesis information and chip summary will be shown in the following sections.
6.1 Design Methodology
The trend of IC technology is towards to System-on-Chip (SoC). System-level simulation becomes very important in today’s design flow. Our design methodology from system simulation to hardware implementation can be shown in Figure 6.1.1.
Matlab platform
Algorithm verification Fixed-point design
Verilog HDL Coding Gate-level Synthesis Circuit-level Implementation
Channel model
Wordlength Analysis
Verilog Test Bench
Circuit Test Bench System built-up
Figure 6.1.1 Platform-based design methodology
First, the system platform with channel modals should be established according to the system specification, which ensures the design in the practical condition. Algorithm and architecture developments of each function block should be verified in the system platform to ensure the whole system performance. Fixed-point simulation is applied before hardware implementation to make a trade-off between system performance and hardware cost. An example of the wordlength distribution analysis can be shown in Figure 6.1.2. Based on the signal distribution analysis and the PER simulation, a reasonable wordlength of each signal can be decided.
(a) (b)
Figure 6.1.2 (a) Signal distribution analysis (b) PER analysis of different wordlength
In hardware implementation, the HDL modules are verified with the test benches dumped from the equivalent Matlab blocks to ensure the correctness.
6.2 The Channel Equalizer for OFDM-based Wireless Systems
6.2.1 Architecture of the Proposed Channel Equalizer
Figure 6.2.1 shows the hardware architecture of the proposed channel equalizer for general OFDM-based wireless systems.
Figure 6.2.1 The architecture of the proposed channel equalizer
In the initial training sequence, CE_en is set to logic “1”. CFR is calculated by the complex multiplication with the inverse of the defined training sequence “Def_XL[N]” and the received data. The estimated CFR HA[N] is saved in the CFR Memory. In normal OFDM symbols, CE_en is set to logic “0”. Input data is equalized with the estimated CFR. After the equalization, data subcarriers are used for DDCE and pilot subcarriers are used for PET. In DDCE, the new estimated CFR is calculated by the difference between the received data and the predicted mapping result. A loop filter is applied to reduce the influence of AWGN. In PET, “tan-1” is used for coordinated conversion. The mean phase error and the linear phase error are calculated with fixed-coefficient loop filters, which enhance the tracking accuracy.
The estimated phase error θis then converted to ejθ and combined with the inverse of the new CFR to update the CFR memory for next symbol equalization.
6.2.2 Hardware Synthesis
In this section, we discuss the implementation of the DDCE with feedforward compensation scheme, which has been accepted in 2003 ISCAS [19]. The proposed high performance channel equalizer with feedback compensation loop presented in the previous chapters is the algorithm improvement based on this design.
Table 6-1 shows the synthesis result of the six-stage pipelined DDCE with feedforward compensation scheme in a 0.18um cell library with clock rate equals to 20MHz (Tapeout 2003.
Aug). The combinational logic includes 4 complex multipliers, 4 real multipliers, and 6 real add/sub. The non–combinational (sequential) logic includes look-up tables, pipeline registers, and storage register files. The compensation complex divider is shared with the ZF CE, which is the critical delay. The synthesis result of the 22 bit complex divider can be shown in Table 6-2.
Table 6-1 The gate count of DDCE Gate count
Combinational 54296
Complex multiplier (14 bit) 8470
Non-Combinational 17756
Total 72052
Table 6-2 Gate count of the complex divider
Gate count Gate delay
Complex divider 38700 40ns
6.3 The High-Speed and Low-Complexity Channel Equalizer for UWB System
6.3.1 Architecture of the Proposed Channel Estimation
Figure 6.3.1 shows the hardware architecture of the proposed high-speed and low-complexity channel estimation. A 6-stage pipeline is applied for clock rate and data flow consideration.
Applying the proposed design, the required throughput can be achieved by using only 2 parallel CE.
First, output from 4 parallel FFT are sampled with the double rate for CE design. Based on the CEP definition of UWB specification, the complex divider used for ZF CE can be implemented as a simple sign inversion. Because of the total CFR size is less than 0.4K Byte, register files are used to save the estimated CFR instead of using memory. Arc-tangent is then
Figure 6.3.1 The architecture of the proposed CE
applied to make coordinate conversion form complex number to phase information only.
Therefore, channel equalization becomes a simple subtraction in phase domain. No complex
arithmetic blocks are used in the proposed design. Tables (multiplexers) and datapath registers will dominate the CE size. The critical path will be the arc-tangent design, which is 3-stage pipelined, and will be discussed in the next section.
6.3.2 Architecture of the Proposed Arc-tangent Design
Figure 6.3.2 shows the hardware architecture of the proposed logarithm TLU-based arc-tangent, which is used for coordinate conversion. In order to meet the clock rate requirement, a 3-stage pipeline is applied. Only real adder/subtraction are used in the proposed design. The gate count and critical time will be listed in the next section.
Figure 6.3.2 The architecture of the proposed logarithm TLU-based arc-tangent
6.3.3 Hardware Synthesis
Table 6-3 shows the hardware synthesis result of the proposed high-speed channel equalizer in a 0.18um cell library with successful gate-level simulation. With a parallel-two architecture, the throughput can reach 554Msymbol/s, which is higher than the requirement of UWB specification (528Msymbol/s).
Table 6-3 The gate count of the high-speed channel equalizer (parallel x2) Gate count
Combinational 27884
Non-Combinational 18305
Combinational 1118
Non-Combinational 315
Arc-tangent
Total 1433
Total 46189
The combinational logic includes look-up tables, multiplexers and simple real arithmetic blocks (add/sub). The sequential logic includes datapath and CFR registers. The critical delay is 3.41ns and has been successfully simulated with 277MHz (3.6ns) clock rate. Compared with the conventional complex ZF CE, it achieves more than ten times of the operation clock rate with only 50% of the hardware cost.
6.4 IEEE 802.11a Baseband Processor
Based on the proposed channel equalizer, OFDM modem and a low-power FEC design [20], a COFDM baseband processor compliant to IEEE 802.11a was designed using 0.18um standard CMOS process and tested completely. The microphoto is shown in Figure 6.4.1 with features listed in Table 6-4. The proposed low-cost baseband processor only contains 370K logic gates and 3.3Kbytes memory, which is less than the solution proposed in [21].
TX and Shares
FEC (II) Frame Detection
and AGC RAMs
(I)
RAMs (II)
CE
FEC (I) CFO Est. &
Com.
FFT
Tx & Others PET
Figure 6.4.1 Microphoto of the test chip for 802.11a baseband processor.
Table 6-4 Chip Feature
Technique 0.18um CMOS, 1P6M
Transistor Count
2.1M (Include I/O)
Package 144-pin CQFP
Core Size 3.8 x 3.8 mm2
Clock Speed 80MHz
Supply Voltage 1.8V Core, 3.3V I/O Core power at 54Mbits/s (Tx/Rx) 52.4mW/123.5mW
I/O Power 61mW
6.5 UWB Basedband Processor
The gate-level simulation of the UWB baseband processor including the proposed high-speed channel equalizer has been completed. The developed UWB baseband processor comprises an OFDM modem and a LDPC FEC design, which provides three data rate including 120Mbits/s, 240Mbits/s and 480Mbits/s in 528MHz baseband bandwidth. The required 528Msymbol/s throughput of UWB specification can be achieved by using two parallel channel equalizers with operating clock rate equals to 264MHz. The gate count is 46.2K, which is 18.48% of the total gate count of the OFDM modem (250K).
Chapter 7 .
Conclusion and Future Work
After the algorithm illustration and performance analysis, the proposed channel equalizer is robust to solve multipath fading, CFO, and SCO due to the algorithm improvement and the combination of DDCE and PET. In the proposed CE, equalization error can be reduced efficiently by the novel data-aided tracking algorithm. In the proposed PET, a full tracking range can be achieved by the pilot pre-compensation scheme, and the tracking accuracy can be enhanced by the applied fixed-coefficient loop filters. With the proposed design, multipath fading, CFO and SCO can be eliminated simultaneously with channel equalization, which reduces the compensation complexity compared with former approaches. In performance measurement, the proposed CE achieves (i) 9~13dB gain in MSE compared with zero forcing CE, (ii) 2.0~13.9 dB gain in MSE compared with fixed-coefficient LMMSE CE. The proposed PET achieves a better 1.9~2.3dB gain in SNR for 10% PET compared with conventional approaches. Applying the proposed channel equalizer, the IEEE 802.11a baseband processor achieves 1.35~7.16dB average gain in SNR compared with current approaches and the standard requirement.
A high-speed and low-complexity phase-domain channel equalizer is proposed based on the previous algorithm with coordinate conversion. The proposed modified algorithm can achieve the same performance of conventional zero forcing with lower than 50% of the computation complexity. In hardware implementation, the gate count is 46.2K with maximum throughput of 554Msymbol/s, which is 50% of the hardware cost, ten times of the operation clock rate compared with conventional zero forcing approach.
In this thesis, we focus on indoor OFDM-based wireless access systems. The applied wireless channel model is relatively simple compared with outdoor, mobile systems. In the future, OFDM may be widely applied in mobile communications, which has a much more complicated transmission environment. Therefore, a more robust synchronization scheme including channel estimation, CFO and SCO compensation will certainly be needed to further explore in the future.
Bibliography
[1] Rechard Van Nee, and Ramjee Prasad, “OFDM for Wireless Multimedia Communications,” pp.20-51, 2000.
[2] Salzberg, B.R, “Performance of an efficient parallel data transmission system,” IEEE Trans. Comm., Vol. COM-15, pp.805-813, Dec. 1967.
[3] IEEE 802.11a IEEE Standards for Wireless LAN Medium Access Control and Physical Layer Specifications, Nov. 1999.
[4] IEEE P802.15 Working Group, “Multi-band OFDM Physical Layer Proposal for IEEE 802.15 Task Group 3a,” July 2003.
[5] ESTI EN 300 401 “Radio broadcasting systems; digital audio broadcasting (DAB) to mobile; portable and fixed receivers,” May 2001.
[6] ESTI EN 300 744 “Digital vedio broadcasting (DVB); framing structure, channel coding and modulation for signal digital terrestrial television,” Jan. 2001.
[7] ESTI TS 101 475 “Broadband radio access network (BRAN); Hiperlan type 2; Physical layer,” April 2001.
[8] Weinstein, S.B. and P.M. Ebert, “Data Transmission by Frequency Division Multiplexing Using the Discrete Fourier Transform,” IEEE Trans. Comm., Vol. COM-19, pp.628-634, Oct. 1971.
[9] T. Pionteck, N. Toender, L.D. Kabulepa, and M. Glesner, “On the Rapid Prototyping of Equalizers for OFDM systems,”
[10] Furrer S. and Dahlhaus D. “Mean bit-error rates for OFDM transmission with robust channel estimation and space diversity reception,” Broadband Communications, Access, Transmission, Networking. International Zurich Seminar on, pp.: 47-1~47-6, 2002.
[11] Wolfgang Eberle, et al., “80-Mb/s QPSK and 72-Mb/s 64-QAM Flexible and Scalable Digital OFDM Transceiver ASICs for Wireless Local Area Networks in the 5-GHz Band,”
IEEE Journal of Solid-State Circuits, Vol. 36, No. 11, Nov. 2001.
[12] Fujisawa , et al., “A single-chip 802.11A MAC/PHY with a 32b RISC processor,” IEEE Journal of Solid-State Circuit, Vol. 38, No. 11, Nov. 2003.
[13] J. Thomson et al., “An integrated 802.11a baseband and MAC processor,” in IEEE Int.
Solid-State Circuits Conf. Dig. Tech. Papers, pp.126–127, Feb. 2002.
[14] Bob O’Hara and Al Petrick, “The IEEE 802.11 Handbook – A Designer’s Companion,”
IEEE Press, January 2000.
[15] John G. Proakis, “Digital Communications,” McGraw Hill, pp.808-810, 2001.
[16] Moose, P.H, “A Technique for Orthogonal Frequency Division Multiplexing Frequency Offset Correction,” IEEE Transactions on Communication, Vol. 42, No. 10, pp.1590-1598, Oct. 1994.
[17] M. Speth, D. Daecke, H. Meyr, “Minimum Overhead Burst Synchronization for OFDM based Broadband Transmission,” IEEE Global Telecommunications Conference, Vol.5, pp.2777-2782, 1998.
[18] Hsuan-Yu Liu, Yi-Hsin Yu, Chien-Ching Lin, Ching-Che Chung, Terng-Yi Hsu, and Chen-Yi Lee, “A COFDM Baseband Processor with Robust Synchronization for High-Speed WLAN Applications”, Symposium on VLSI Circuits, 2004.
[19] Hsuan-Yu Liu, Yi-Hsin Yu, Chien-Jen Hung, Terng-Yin Hsu, Chen-Yi Lee “Combining Adaptive Smoothing and Decision-Directed Channel Estimation Schemes for OFDM WLAN Systems,” ISCAS, 2003.
[20] C.C. Lin, C.C. Wu, and C.Y. Lee, "A low power and high speed Viterbi decoder chip for WLAN applications," in Proc. 29th Eur. Solid State Circuits Conf, pp.723-726, 2003.
[21] P. Ryan et al., “A single chip PHY COFDM modem for IEEE 802.11a with integrated ADC’s and DAC’s,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers,
pp.338–339, Feb. 2001.
Vita
姓 名： 俞 壹 馨 出 生 地： 台灣省花蓮縣 出生日期： 1980. 2. 9
學 歷： 2002. 9～2004. 6 國立交通大學 電子研究所系統組 碩士 (Si2 Lab) 1998. 9～2002. 6 國立交通大學 電子工程學系 學士
1995. 9～1998. 6 國立花蓮女子高級中學 1992. 9～1995. 6 花蓮縣立美崙國民中學
1986. 9～1992. 6 國立花蓮師範學院附設實驗國民小學
得獎事蹟： 91 學年度 第二學期電子研究所書卷獎
91 學年度 教育部 IC 設計競賽研究所／大學部 Cell base 組設計完整 90 學年度 殷之同專題計劃／成果獎學金
90 學年度 教育部 IC 設計競賽大學部 Full Custom 組優等 89 學年度 第二學期電子工程學系書卷獎
發表論文： [1] Yi-Hsin Yu, Hsuan-Yu Liu, Terng-Yin Hsu, and Chen-Yi Lee, “A Joint Scheme of Decision-Directed Channel Estimation and Weighted-average Phase Error Tracking for OFDM WLAN Systems,” APCCAS 2004 [2] Hsuan-Yu Liu, Yi-Hsin Yu, Chien-Ching Lin, Ching-Che Chung, Terng-Yin
Hsu, and Chen-Yi Lee, “A COFDM Baseband Processor with Robust Synchronization for High-Speed WLAN Applications,” Symposium on VLSI Circuits 2004.
[3] Hsuan-Yu Liu, Yi-Hsin Yu, Chien-Jen Hung, Terng-Yin Hsu, Chen-Yi Lee
“Combining Adaptive Smoothing and Decision-Directed Channel Estimation Schemes for OFDM WLAN Systems,” ISCAS 2003.