2.3 Chip Layout and Simulation Results
Fig. 2 - 10 shows the chip layout photograph of the proposed QVCO which is implemented in TSMC 0.18 μm mixed-signal/RF CMOS 1P6M process. The chip size is 1 × 0.78 mm2 including all pads and bypass capacitances. Each buffer of the QVCO output is designed as a common-source amplifier with bias-tee model. The core power consumption is 6.462 mW at 1.8 V supply.
Fig. 2 - 10 Chip layout of the proposed QVCO
Compared with P-QVCO, as shown Fig. 2 - 2, the proposed QVCO has three advantages:
(1) Low phase noise
(2) It doesn’t consider the trade-off of phase noise and phase error.
(3) Reducing power consumption.
The first combines current-reused VCO with Colpitts structure. And also it makes better phase noise by passive device coupling than active devise. Second, the active coupling transistors Mc1 to Mc4 make P-QVCO difficult to optimize phase noise and phase error. Using capacitor to generate quadrature signals doesn’t consider the coupling factor that defines as traditional P-QVCO. Finally, proposed QVCO only uses two branch currents to get desired trans-conductance. However, P-QVCO needs four branch currents to get same trans-conductance.
Fig. 2 - 11 The comparison of pre-simulated phase noise at 5GHz
Fig. 2 - 11 shows the pre-simulated phase noise performances of proposed QVCO, a stand-alone VCO of Fig. 2 - 6 and the P-QVCO of Fig. 2 - 2. Under supplied voltage of 1.8 V for all simulations at 5 GHz, the power consumption of the proposed QVCO is equal to the P-QVCO and is twice of the stand-alone VCO. In Fig. 2 - 11, the phase noise at 1MHz offset frequency of proposed QVCO is quite close to that of the stand-alone VCO. Compared with the phase noise of P-QVCO, the phase noise of proposed QVCO is better about 5 dB.
Consequently, using Colpitts capacitor to couple quadrature signals doesn’t make extra phase noise.
To consider EM effect, the simulated tuning range 、voltage swing at 5GHz and phase noise is shown in Fig. 2 - 12 to Fig. 2 - 14, respectively. The po-simulated tuning range covers from 4.7826 to 5.316 GHz with control voltage supplying from 0 V to 1.8 V shown in Fig. 2 - 12. When oscillatory frequency is 5.316 GHz, the po-simulated phase noise of proposed QVCO at 1 MHz offset frequency is -119.45 dBc/Hz shown in Fig. 2 – 13. Fig. 2 - 14 shows output voltage swing of proposed QVCO that exist a little amplitude error due to MOS mismatch. In addition, the po-simulated quadrature phase errors and differential phase error are below 4° shown in Fig. 2 - 14.
Fig. 2 - 12 Simulated tuning range of the proposed QVCO
Fig. 2 - 13 Simulated phase noise of the proposed QVCO
Fig. 2 - 14 Simulated swings of the proposed QVCO
2.4 Measurement Results and Comparison
2.4.1 Measurement Consideration
The proposed QVCO are designed for on-wafer testing, and the DC voltage are supplied by two sets of three-pin probe, so that the distance between each DC pad is 100um to satisfy the probe testing rules. The output buffer of each quadrature output is designed using common-source amplifier, and the drain end of each buffer is connected to the RF pad. For measurement, we connect four bias-tee terminals to the corresponding RF pads.
The phase noise, tuning range and output spectrum are measured by signal source analyzer (Agilent E5052B) shown in Fig. 2 - 15. The output voltage swing is measured by digital signal analyzer (Agilent DSA91204A) shown in Fig. 2 - 16.
Fig. 2 - 15 Signal Source Analyzer (Agilent E5052B)
Fig. 2 - 16 Digital Signal Analyzer (Agilent DSA91204A)
Fig. 2 - 17 Chip photo of the proposed QVCO
The Chip photo of the proposed QVCO is shown in Fig. 2 - 17. Fig. 2 - 18 shows the arrangement of DC and RF probes. The core DC consumption is 8.46 mW with 1.8 V. The measured phase noise at 1 MHz、output spectrum、output swings and tuning range, was shown in Fig. 2 - 19 to Fig. 2 - 22, respectively. When oscillatory frequency is 5 GHz, the measured phase noise of proposed QVCO at 1 MHz offset frequency is -119 dBc/Hz shown in Fig. 2 - 19. As shown in Fig. 2 - 20, the output power at 5 GHz is -8 dBm without compensating buffer effect and the loss of coaxial cables line. Measured output swings are shown in Fig. 2 - 21. According to measured swings data, the average phase error of quadrature signals and different signals is 8° and 9° respectively. The measured tuning range covers from 4.57 GHz to 5.02 GHz with control voltage supplying from 0 V to 1.8 V shown in Fig. 2- 22.
Fig. 2 - 18 Photograph of the probe station
Fig. 2 - 19 Measured phase noise of the proposed QVCO
Fig. 2 - 20 Measured output spectrum of the proposed QVCO
Fig. 2 -21 Measured voltage swings of the proposed QVCO
Fig. 2 -22 Measured tuning range of the proposed QVCO
The figure of merits (FOM) for oscillators summarizes the important performance parameters, i.e., phase noise and power consumption , to make a fair comparison is defined in [40] as : oscillation frequency, P is the power consumption of core circuit. Table 2 - 1 summarizes DC the simulated and measured results of the proposed QVCO. Every measured performance is close to simulated results except frequency range. Table 2 - 2 shows the comparison of the measured results of proposed QVCO with the published papers of QVCOs. From Table 2 - 2, it can get proposed QVCO making better performance than other QVCO at same frequency and process
Table 2 - 1 Simulated results of the proposed QVCO
Table 2 - 2 Comparison of QVCO performance Process Tuning
Chapter 3
A High Gain Down Conversion Mixer in Ku Band
3.1 Introduction
Mixer is an essential component of an RF system and translates the IF signal to a carrier frequency for transmission. Mixer operates either the trans-conductance of an amplifier or the resistance of a switch to produce the mixing action through time-varying mechanism. There are many structures of active mixers (single-balanced 、 double-balanced, etc.), the double-balanced circuit have been popularly appearing in microwave and millimeter wave applications for its good isolations because it solves the problem of LO-IF feed-through from single-balanced circuit.
Fig. 3 - 1 Conventional double-balanced mixer
For example, as indicated in Fig. 3 - 1, the schematic is a typical double balanced mixer.
In order to enhance the conversion gain, it is perhaps to use large RL. However, as RL increasing, the voltage headroom will decrease and minimize the output swing to drive next stage hardly. Increasing the power supply VDD is a solution but it will consume more power.
Another solution is additionally current bleeding by using the two current sources as indicated in Fig. 3 - 2. Bleeding can achieve a higher conversion gain through the higher load because part of the trans-conductance stage current steers from the switching pairs. Furthermore, the transistors of switch pairs could be operated at a lower overdrive voltage and smaller size transistors could be used. In either case, for setting power of local signal, bleeding improves the conversion efficiency when lower charges are necessary to turn them on and off. However, bleeding degrades at high frequency performance of the trans-conductance stage due to the higher impedance at the output as the smaller DC currents through the switching pairs reduce their trans-conductance [14].
Fig. 3 - 2 Conventional double-balanced mixer with current bleeding
3.2 Circuit Design Consideration
The proposed high gain mixer is shown in Fig. 3 - 3. It can be divided mixer into three blocks, active load, switch pairs and radio frequency (RF) trans-conductance stage like Fig. 3 - 4 and discuss each block respectively.
Fig. 3 - 3 The proposed high gain mixer
Fig. 3 - 4 The block diagram of conventional mixer
The active load is shown Fig. 3 - 5. The transistors M9 and M10 are the active load of the mixer replacing passive load resistors of conventional mixer. Furthermore, using M9 、M10
and RL to construct common mode feedback circuit (CMFB) can stabilize the IF ports (IF+、
IF- ) and restrain the common mode signal from the IF ports. RL also can prevent the IF ports dropping as it is increased to provide more conversion gain. This will provide a better linearity than passive load structure even if the conversion gain is increased [27].
Fig. 3 - 5 The active load by CMFB circuit
The switching pairs are formed by four transistors M5-M8 and the current-bleeding circuit is composed of transistors M11-M12, shown Fig. 3 - 6. The current-bleeding circuit [14]
plays an important component in the operation of the down-conversion mixer. First, it improves the conversion gain. Second, the switching pairs can be biased with a low overdrive voltage that reduces the local signal power needed for switching and makes the switching more ideal [14].
Fig. 3 - 6 The switch pairs and current bleeding circuit
Fig. 3 - 7 The LNA trans-conductors for mixer
The LNA trans-conductors with inductor Lsis used to design RF trans-conductance stage [16] shown in Fig. 3 - 7. It is used the LC match input T-model network to simulate optimal noise and impedance matching. This match method yields good input matching and achieves minimum noise figure at the same time easily. Optimum the fingers of transistors and gate bias voltage are needed to get a minimum noise figure for the LNA. But, in mixer, the flicker noise of the switching pairs translates to output due to the direct and indirect mechanism that is explained in [15]. To minimize the noise effect of the direct mechanism, the current-bleeding circuit is used to decrease the dc current through the switch pairs. However, the current-bleeding circuit also adds noise to mixer. To minimize the noise of the current-bleeding circuit, PMOS transistor is chosen and biased at the optimum overdrive voltage for minimum noise. The size of switch transistors increases for getting high conversion gain as soon as tail capacitances of the switching pairs increase. It results extra flicker noise translating to the output indirectly [25]. This phenomenon is called noise in indirect mechanism. If parallel inductor L1 be used to resonate out the tail-capacitance, the flicker noise in indirect mechanism will decrease.
3.3 Simulated and Measured Results
The proposed high gain mixer is simulated and optimized using Agilent ADS. Fig. 3 - 8 shows the chip layout of the proposed high gain mixer which is implemented in TSMC 0.18 μm mixed-signal/RF CMOS 1P6M process. The mixer size is 0.7 × 1.4 mm2 including all pads and bypass capacitances. Each buffer of the IF ports were designed as a common-source amplifier.
Fig. 3 - 8 The chip layout photograph of the proposed high gain mixer
Fig. 3 - 9 The full chip photograph of integrated circuit
Fig. 3 - 9 shows the chip photograph of integrated circuit that includes antenna (0.7 × 1.4 mm2) and high gain mixer (0.7 × 1.4 mm2). Fig. 3 - 10 shows the simulated and measured s-parameter of RF ports. The simulated result without antenna is an exact performance of proposed mixer. However, it cannot cut the antenna to get the true results of mixer when the probe contacts the pad of mixer to measure performance. So, the matching s-parameter of mixer shifts to high frequency because the load of antenna affects matching impendence that smaller than standard impendence during measurement. As shown Fig. 3 - 10, the simulated s-parameter without antenna is below -10 dB in 12.5~15 GHz and with antenna is below -10 dB in 13~20 GHz. The measured s-parameter is averagely below -10 dB in 6~20 GHz.
Fig. 3 - 11 shows the simulated and measured the bandwidth of conversion gain while radio frequency down converts to 100 MHz. The simulated result with antenna or not exhibits the 3 dB gain bandwidth from 11.5 to 14.8 GHz and the maximum conversion gain is 22.285 dB at 13 GHz. However, the measured result decreases 4 dB approximately. The maximum conversion gain is 18.3 dB at 14 GHz and bandwidth covers from 12 to 16 GHz. As shown Fig. 3 - 12, the simulated noise figure without antenna is below 9 dB in 12~15.5 GHz and with antenna is below 12.3 dB in 12~16 GHz. The measured noise figure is below 16 dB in 12~16 GHz and the minimum is 13.214 dB at 13.5 GHz.
Fig. 3 - 10 The input return loss of the proposed high gain mixer
Fig. 3 - 11 The conversion gain of the proposed high gain mixer
Fig. 3 - 12 The noise figure of the proposed high gain mixer
Fig. 3 -13 and Fig. 3 - 14 show the simulated and measured linearity at 14 GHz that is the radio frequency of the maximum conversion gain. The simulated linearity shows that P1dB is -26 dB and IIP3 is -15 dB. The measured linearity shows that P1dB is -16 dB and IIP3 is -7.5 dB. Fig. 3 -15 shows the measured isolation from 9.9 to 18 GHz. The LO-IF isolation is below -35 dB, the LO-RF isolation is below -55 dB and the RF-IF isolation is below -35 dB. The figure of merits (FOM) for mixer summarizes the important performance parameters and formula is defined as:
FOM
Mixer＝ 20log( f
RF)+ CG NF DSB ( ) IIP 3 10log( P
Consumption)
(3.1)
where fRF is the center frequency. CG is the conversion gain. NF DSB( ) is noise figure at
double-side band. IIP3 is input third-order intercept point.
P
Consumptionis power consumption.Table 3 - 1 summarizes the simulated and measured results of the proposed high gain mixer.
The simulated FOM is 193.7 by equation (3.1). However, the measured FOM drops to 191.42.
Including the antenna load effect, the simulated power consumption is not equal to the measured power consumption. This condition must be process variation. Also, the proposed mixer is used by idea balun to generate different signals and drive proposed mixer. The performance of idea balun is obviously different from the real balun that used in measurement because real balun exists phase error but idea balun doesn’t. So, from Fig. 3 – 11 to Fig. 3 – 15, the simulated results are not fit measured results perfectly due to process variation and using real balun.
Fig. 3 - 13 The P1dB of the proposed high gain mixer
(a) Simulation
(b) Measurement
Fig. 3 - 14 The IIP3 of the proposed high gain mixer
Fig. 3 - 15 The isolation of the proposed high gain mixer
Table 3 -1 Simulated results of the proposed high gain mixer
Simulation Measurement
Technology TSMC 0.18um CMOS
RF Freq. 11.5~14.8 GHz 12~16 GHz
IF Freq. 100 MHz 100 MHz
LO Power 0 dB 0 dB
Conversion Gain,max 22.285 dB 18.327
NF 8~9 13.2~15.9
P1dB -26 dB -16 dB
IIP3 -15 dB -7.5 dB
LO-to-RF isolation < -40 dB < -55 dB
LO-to-IF isolation < -35 dB < -35 dB
RF-to-IF isolation < -35 dB < -35 dB
Power Consumption 6.12 mW 7.56 mW
FOM 193.7 191.42
Table 3 -2 Comparison of mixer performance
Chapter 4
4-17 GHz Wideband High Gain Down
Conversion Mixer with Cascade Structure
4.1 Introduction
Direct conversion front-end circuit is a very important component in wireless communication system. Generally, front-end circuit must be constituted by low-noise amplifier (LNA) and mixer. The mixer is a key block to translate signals in the system. In the development of modern wireless applications, wideband frequency range, low power consumption and small chip area are the aims of work. For these topics, the idea of high gain mixer is proposed and replaced conventional front-end circuit further. The double-balance mixer is commonly used because the advantage of this active mixer is good isolation [14].
However, the main challenge in double-balanced mixer is to decrease noise figure and extend frequency range for more applications at steady high conversion gain.
In this chapter, a broadband high gain mixer is presented for many bands applications such as C band (4~8 GHz)、X band (8~12 GHz) and most part of ultra-wide band (3.1~10.6 GHz) and Ku band (12~18 GHz). The RF trans-conductance stage of proposed mixer uses cascade structure that the capacitor cross-coupled wideband amplifier at first stage replaces passive LC input match network to design high gain mixer at wide frequency range.
4.2 Circuit Design Consideration
Radio frequency designs are increasingly used in advance CMOS process that makes the integration of complete communications systems possibly [17]. The proposed mixer at this chapter is shown in Fig. 4 – 1. In high gain mixer, the blocks of active load and switch pair are discussed at chapter 3. This section focuses on RF trans-conductance stage how to achieve high gain and low noise figure in wideband. The RF part can be divided into CS-LNA [17] at second stage and CCC CG-LNA [20] at first stage.
Fig. 4 - 1 The proposed high gain mixer with wideband amplifier
A. Common Source Low Noise Amplifier (CS-LNA)
As shown Fig. 4 – 2, it is a popular structure of low noise amplifier that is inductive generation common-source LNA (CS-LNA). In a CS-LNA, degenerated inductor LS2 is used to generate the real part impedance needed to match the LNA easily. Using LG2 is called series RLC network circuit can possibly match the input impedance to 50Ω in narrow band. A simple analysis of input impedance is defined as [17]:
and proportional to LS2. The gate inductor LG2 is used to set the resonance frequency as it is chosen to satisfy the criterion of 50 Ω input impedance [17].Ctot is the capacitance of CGS,2 and CG2 in series. The large gate capacitance CG2 is used to be a DC block so the capacitance of Ctot almost equals to CGS,2.
Fig. 4 - 2 The CS-LNA with series RLC input match network
However, the degenerated inductor common source LNA with a series RLC input match network only can enhance effective trans-conductance to increase gain and reduce the noise figure in narrowband [19].
B. Capacitor Cross-Coupled CG-LNA (CCC CG-LNA)
In order to extend bandwidth, common gate amplifier (CGA), shown Fig. 4 - 3, is used to match wideband input impedance generally. The simple input admittance and noise factor analysis of CGA is defined as [20]:
1 1 α,γ are bias-dependent parameters [26]. According Equation (4.2), the CGA at first stage can achieve to 50 Ω because the input impedance looking into the source of transistor M1 is approximate 1/Gm1. However, the CGA suffers from poor noise figure comparison to CS-LNA [20]. To solve this problem, a capacitive cross-coupling method can boost the trans-conductance of transistors M1 and M3 with the passive component of capacitors [20]-[22]. As shown in Fig. 4 – 4, it is called capacitor cross-coupled common-gate low noise amplifier (CCC CG-LNA).
M
1Ls
RF+
V
GFig. 4 - 3 The structure of common gate amplifier
Fig. 4 - 4 The structure of CCC CG-LNA
According to Fig.4 – 4, the small signals analysis of CCC CG-LNA can prove the effective trans-conductance and noise factor better than CGA by following formula:
, 1 1 Due to capacitors cross-coupling, the noise factor decreases and the effective trans-conductance is double if CC is much larger than CGS. So, the CCC CG-LNA is fit for wideband differential topology.
The RF trans-conductance stage of proposed mixer combines CCC CG-LNA with CS-LNA to design a cascade structure. The CCC CG-LNA at first part achieves wideband input matching to improve applications and supplies the RF gain of low frequency band. The CS-LNA at second part includes both the RF gain of high frequency band and translating voltage signals into current signals that provides switch pair down-conversion. LD2 and LD4 resonate out the tail capacitance of switch pairs to reduce flicker noise in indirectmechanism more [15] [23] [25].
4.3 Simulated and Measured Results
The proposed high gain mixer is simulated and optimized using Agilent ADS. Fig. 4 - 5 shows the chip layout of the proposed high gain mixer which is implemented in TSMC 0.18 μm mixed-signal/RF CMOS 1P6M process. The chip size is 1.19 × 1.17 mm2 including all pads and bypass capacitances. Each buffer of the IF ports were designed as a common-source amplifier.
Fig. 4 - 5 The chip layout of the proposed mixer
Fig. 4 - 6 The chip photograph f the proposed mixer
Fig. 4 - 6 shows the chip photograph of proposed mixer. As shown in Fig. 4 -7, the simulated and measured return losses of RF ports are below -8 dB in 4~20 GHz. Fig. 4 - 8 shows the simulated and measured the bandwidth of conversion gain when radio frequency down converts to 100 MHz. The simulated result exhibits the 3dB gain bandwidth from 2.7 to 17.8 GHz and the maximum conversion gain is 27 dB at 4 GHz and 15 GHz. But, the measured result decreases 4 dB approximately and the maximum conversion gain is 22.7 dB
Fig. 4 - 6 shows the chip photograph of proposed mixer. As shown in Fig. 4 -7, the simulated and measured return losses of RF ports are below -8 dB in 4~20 GHz. Fig. 4 - 8 shows the simulated and measured the bandwidth of conversion gain when radio frequency down converts to 100 MHz. The simulated result exhibits the 3dB gain bandwidth from 2.7 to 17.8 GHz and the maximum conversion gain is 27 dB at 4 GHz and 15 GHz. But, the measured result decreases 4 dB approximately and the maximum conversion gain is 22.7 dB