Characteristic Fluctuations in Analog Circuits

This subsection presents the implication of device variability in analog circuits. At first, we compared current mismatch between control and inLAC device in current mirror cir-cuit. Based upon the Vthis significantly suppressed form 43.3 mV and 28.5 mV for NMOS devices, the normalized IOUT fluctuation of the studied circuits caused by random dopants is reduced to 4.66%, as shown in Fig. 4.16. To disclose the suppression more clearly, the IREF corresponding to IOUT for each discrete-dopant-induced fluctuated device of control and inLAC devices are explored in Fig 4.17, respectively. The solid symbols indicated the control device and open symbols are inLAC devices. The IOUT of inLAC devices is 1.74 times smaller than the current mirror with control devices. Comparing dynamic charac-teristic fluctuations between the inLAC and LAC devices are then examined in Fig. 4.18.

The inLAC device exhibits better immunity against RDF. The fluctuations of calculated quantities are summarized in inset of Fig. 4.18, where the horizontal ratio is calculated by Ratio = fluctuation of LAC devices / fluctuations of inLAC devices. The inset shows the fluctuation ratio of circuit gain, 3dB bandwidth, and unity-gain bandwidth for LAC device which dopants located near the source-end are 1.59, 1.21, and 2.16 times larger than those of inLAC device with dopants near the drain-end. Therefore, the intrinsic output resistance (ro), transconductance (gm), gate capacitance, and dynamic characteristic fluctuations of the inLAC device and control device are further explored. Figure 4.19 shows the smaller

4.2 : Characteristic Fluctuations of Lateral Asymmetric Channel Device 93

gm and ro fluctuation of inLAC device as compared with control device which meant less impact on magnitude of output signal and thus exhibits less the influence on circuit gain.

Figure 4.20 explores the CG− V^G characteristics of the discrete-dopant fluctuated inLAC (dashed lines) and the original (solid lines) devices, respectively. The spreading range of the lateral asymmetry doping profile is reduced, which implies the suppression of Cg and dynamic characteristic fluctuations, as marked in Fig. 4.20. The high-frequency response of the nano-MOSFET circuit is then studied in Fig. 4.21(a), where the solid lines are control devices and the dashed lines show the inLAC devices. The spreading range of the inLAC devices is reduced significantly due to the suppression of ro, gm, and Cg. As shown in Figs. 4.21(b)-4.21(d), the high frequency characteristic fluctuations of the circuit gain, the 3dB bandwidth, and the unity-gain bandwidth are reduced by 31.2%, 37.6% and 47% for inLAC device, respectively. Notably, since the gm and Cg are factors of circuit gain, 3dB bandwidth and unity-gain bandwidth, the dynamic characteristics have similar fluctuation suppression.

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fluctuations for the studied current mirror circuit with control device and inLAC device, respectively, where the normalized IOUT fluctuations are defined by standard deviation of absolute difference of IOUT and IREF divide by IREF.

4.2 : Characteristic Fluctuations of Lateral Asymmetric Channel Device 95

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Figure 4.18: High frequency response of the studied circuits. The solid

lines are the results of inLAC devices and the dash lines are for the results of LAC devices. The inset is comparison of different fluctuation components between the studied two group devices.

4.2 : Characteristic Fluctuations of Lateral Asymmetric Channel Device 97

Figure 4.19: DC characteristic fluctuation of (a) gmand (b) robetween control and inLAC devices. As the dopant number is increased, the devices Vthis increased and thus increased ro and decreases transconductance. The triangle symbols show the control devices and the cross symbols are inLAC devices, respectively.

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discrete-dopant-fluctuated 16-nm-gate devices generated from the proposed inLAC devices (dashed line) and control device (solid line).

4.2 : Characteristic Fluctuations of Lateral Asymmetric Channel Device 99

Figure 4.21: Comparison of (a) frequency response fluctuations, (b) circuit gain, (c) 3dB bandwidth, (d) and unity-gain bandwidth fluctuations of the 216 discrete-dopant

fluctuated 16-nm-gate planar MOSFET circuit with inLAC and control devices. The circle symbols show the control devices and the cross symbols are inLAC devices,

respectively.

4.3 Summary of this Chapter

In this chapter, we have presented two techniques to suppress RDF-induced character-istics fluctuation. For the DMG device, the dopant will induce relatively small potential deviation in DMG due to a large initial potential barrier existed (φdopant/φH, compared with φdopant/φLand φdopant/φM) in the cross-sectional view of potential energies for dopant near the source side. However, the same suppression of AC characteristic fluctuations can not enjoy the advantage of DMG device because the capacitance of depletion region is af-fected by doping distribution of channel region and effective oxide thickness. Therefore, the inLAC device was proposed to suppress AC characteristics sequentially. The inLAC device has exhibited less characteristic fluctuations due to the well controlled of major fluc-tuation source of Cgd. Moreover, in contrast to the control device, the fluctuations of Vth, Ion, gm, ro, Cg, circuit gain, 3dB bandwidth, and unity-gain were simultaneously reduced by 33.4%, 32.8%, 11.9%, 80.6%, 68.8%, 31.2%, 37.6% and 47%, respectively.

101

PART B

Design Optimization of TFT-LCD

ASG Driver Circuit

102

Chapter 5

Optimization Technique

I

n this chapter, the evolutionary algorithm, genetic algorithm and implemented simulation-based optimization method is introduced. At first, we give a brief introduction of the evolutionary algorithm, genetic algorithm (GA), in this work. Then we show the algorithm scheme of the solver to optimize the tested amorphous silicon gate (ASG) driver circuits in Chap. 6.

5.1 Genetic Algorithm

GA is a kind of evolutionary algorithms which are based on simple concepts inspired by the evolutionary biology theory such as selection, crossover, mutation, and so on [62-65,86,87]. GA works with a population of individuals which evolve from one generation

103

to next one. This evolution is able to search all the possible solutions by totally exploring the searching space and lead us to find the global solution of the optimization problem.

Generally, GA includes the following parts as shown in Fig. 5.1; each of the components must be specified in order to define a particular GA.

1. Representation;

2. Evaluation;

3. Population;

4. Parent Selection mechanism;

5. Variation Operator;

6. Survivor selection mechanism; and

7. Initialization Procedure and Terminal. Condition

As for the representation, it is the method to link the “real world” to “GA world”.

The possible solution of real world will be “encoded” to the specified form which is called chromosome and usually represents a candidate solution. Evaluation forms the basis for selection. Usually, specific fitness function depending on the problems of the candidates will be calculated and provide the information to the selection mechanism. Parent selec-tion mechanism is to choose better candidates which will be sent in the mating pool and

5.1 : Genetic Algorithm 105

thus variation operators are applied on them. There are two critical variation operators in GA: recombination and mutation. The basic idea of recombination is inheriting informa-tion from two parents, and mutainforma-tion is supposed to cause a random, unbiased change. The offspring will be created after applied variation operators on the candidates in the mating pool. After that, the survivor selection mechanism which is similar to parent selection but used in the different stage of GA is enabled. Age factor is also usually considered in this selection. If no survivor achieves the desired targets, the process repeats until a specified number of generations.

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population, parent selection mechanism, variation operator, survivor selection mechanism, initialization procedure and terminal condition .

5.2 : Variation of Operator in the Genetic Algorithm 107

5.2 Variation of Operator in the Genetic Algorithm

After selection step, the crossover operator is used to generate the next generation so-lution. According to crossover probability and crossover strategy, the crossover operator generates the offspring from two parent individuals chosen from the population by selec-tion. The offspring will substitute their parents in the next populations and may result better fitness score based upon an appropriate crossover strategy. Generally, the crossover methods include one-point crossover [88,89], two-point crossover [88,89], and uniform crossover [64,88-90]. In this thesis, one-point crossover is used to optimize the proposed ASG driver circuit. The one-point crossover is randomly determine one crossover point, and the gene of the offspring from beginning to crossover point will be inherited by one parent individual, and the rest will be inherited by the other parent, as disclosed in Fig.

5.2(a).

After crossover operator, the mutation operator enables to randomly choose two gene in one individual and exchange them with mutation rate, as shown in Fig. 5.2(b). In addition, mutation operator is necessary to maintain genetic diversity to evaluate all the searching space and therefore avoid local optimal solution. The mutation rate is the probability of applying certain randomized change to an individual. Notably, the mutation rate is must be carefully determined. If the mutation rate is too high, it may interrupt the process and imply the loss of optimal solution. If the mutation rate is too low, the genetic diversity may

not be increased and then sticks in the local optimal. More detail setting is discussed in the next subsection.

5.2 : Variation of Operator in the Genetic Algorithm 109

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Figure 5.2: The variation operators, (a) crossover and (b) mutation, used in this work. For the crossover, we randomly choose one point and split two parents at the point, then we exchange the tails of them to create two offspring. After that, the mutation enable to randomly choose two gene in one individual and exchange them with mutation rate.

5.3 The Simulation-Based Optimization Methodology

5.3.1 The Optimization Flow

The unified optimization framework (UOF) [66] enables us to implement the optimiza-tion method to design ASG driver circuit with the most suitable parameters. The UOF can evolve the parameter configuration of circuit by genetic algorithm [64,86,87,91-93] and achieve particular performance of the circuit with the parameter configuration as fitness value by executing external circuit simulator [94-97]. The flow is shown in Fig. 5.3; for a script file of netlist depending on the ASG driver circuit topology, we define the parameters of ASG driver circuit to be optimized. Then, the initial population of these parameters is generated by engineering design or random selection. The evaluation mechanism is putting the parameters into script file to obtain the complete circuit netlist file, and then send the file into circuit simulator to acquire the circuit characteristics automatically. If the characteris-tics meet the requirement prescribed by the circuit designer, we output the final optimized solution. If the error between the specifications and characteristics does not meet the con-vergence criterion, the UOF performs GA to assess the designed parameters. The process will be iterated until the specifications are matched.

5.3 : The Simulation-Based Optimization Methodology 111

5.3.2 The Performance of Developed Optimization Methodology

The parameters setting of GA in circuit design optimization is summarized in Table 5.1.

By considering the experiment, Figs. 5.4(a) and 5.4(b) show a comparison of the score convergence behavior among population sizes, where the crossover and mutation rate is fixed at 0.6. The fitness score versus the number of generation suggests that the score convergence behavior does not have a satisfied result if the population size is too small.

According to our experience, the population size = 100 is good for the optimal design of ASG driver circuit. In addition, Figs. 5.5(a) and 5.5(b) show the fitness score convergence behavior for the circuit optimization with different mutation rate, where the population size

= 100. The results suggest that the mutation = 0.6 keeps the population diversity and finally has better evolutionary results.

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Figure 5.3: The algorithm scheme of the solver to optimize the

proposed ASG driver circuits in this thesis.The replacement is age-based but with 10% elitist and 30% regenerate random individual. After replacement complete, we check whether the solution meets requirements or the max generation is reached.

5.3 : The Simulation-Based Optimization Methodology 113

Table 5.1: The parameters setting of genetic algorithm in our circuit design optimization experiments. The designed parameters of population size, crossover rate, and mutation rate are suitable for ASG driver circuits.

Parameters Setting of Genetic Algorithm value

Population Size 100

Max Generation 100

Crossover Rate 0.6

Mutation Rate 0.6

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Figure 5.4: (a) and (b) The comparison of the score convergence

behavior of the algorithm in two ASG driver circuits among population sizes are 50, 100, and 150, where the crossover and mutation rate is fixed at 0.6, respectively.

5.3 : The Simulation-Based Optimization Methodology 115 Figure 5.5: (a) and (b) The comparison of the score convergence

behavior of the algorithm in two ASG driver circuits among mutation rates are 0.4, 0.6, and 0.8, where the crossover a is fixed at 0.6 and population size is fixed at 100, respectively.

5.4 Summary of this Chapter

The genetic algorithm was introduced briefly in this chapter. Then, detail implemen-tation of optimization flow by UOF was also shown in this chapter. By considering the experiment, the parameters setting of GA, such as population sizes and mutation rate in circuit design optimization were then investigated.

Chapter 6

The ASG Driver Circuit and Simulation Results

I

n this chapter, the original and optimization simulation results of proposed amorphous silicon gate (ASG) driver circuits are discussed. At first, we brief the operation of explored ASG driver circuits. Then the numerical experiments for the proposed explored ASG driver circuits are realized and discussed. Finally, the sensitivity analysis verifies the characteristic variations of optimized circuits.

117

6.1 Operation of ASG Driver Circuit

The proposed ASG driver circuits are used for different products as compared with conventional one [94]. A schematic of active matrix liquid crystal display (LCD) panel controlled by ASG driver circuit in product is shown in Fig. 6.1(a); each stage ASG driver circuit consists of pull-up and pull-down control circuits, pull-up and pull-down output cir-cuits, as show in Fig. 6.1(b). The output state, VGH, and rise time of output waveform are influenced by designed pull-up output circuit. The steady state, VGL, and fall time of output waveform are affected by designed pull-down output circuit, respectively. Figures.

6.2(a) and 6.3(a) show one stage circuit of the proposed ASG driver circuits used in differ-ent products and its timing diagram. The differdiffer-ent between Fig. 6.2(a) and Fig. 6.3(a) is the Pull-up control circuit, Pull-down control circuit and Pull-down output circuit. The reason is that the ASG driver circuit with 14-TFTs used in large loading products such as monitor and screen of TV, whereas the ASG driver circuit with 8-TFTs used in display panel of cell phone, as disclosed in Figs. 6.2(b) and 6.3(b). Thus, the circuit of Fig. 6.2(a) needs more transistors than that of Fig. 6.3(a) to accelerate charge and discharge time. However, the function of two ASG driver circuits is almost the same. Then in these circuits’ topologies, the CLK and CLKB denote the clock signal and clock bar signal; VGL is the steady state voltage, and STV/V_n−1is inputted pulse signal. The Vnand VN are the output signal which supply for the panel and next stage, respectively. Fig. 6.4 shows timing diagram of ASG

6.1 : Operation of ASG Driver Circuit 119

driver circuit with 14-TFTs and the operation of 14-TFTs-ASG driver circuit is as follows.

When the input signal is high, the Q₁ node is charged by the input signal (STV/V_n−1);

then, as CLK is changed from low to high, the Q₁ node voltage is boosted up due to the gate-drain capacitive coupling of M10. Therefore, the output driving ability (Vn and VN) is achieved through M7 and M10. At this time, the high voltage of the Q₁ node is applied to the gates of M4 simultaneously. Therefore, M11 is turned off, and the high voltage is kept at the Q₁ node. After generating an output voltage, the Q₁ node voltage is discharged when the output signal of next stage (Vn) is applied to the gate of M12. After that, the Q₁ node is alternately discharged through M13 by using the CLKB signal.

9*/ Figure 6.1: (a) The common schematic of active matrix liquid-crystal

display panel controlled by ASG driver circuit in real product. (b) The components of one stage ASG driver circuit and the output waveform affected by corresponding component of ASG driver circuit.

6.1 : Operation of ASG Driver Circuit 121

Figure 6.2: The first ASG driver circuit (a) has fourteen a-Si:H TFTs which consisted of 3 pull-up control devices, 3 pull-down control devices, 3 pull-up output devices and 5 pull-down output devices and (b) used in large loading products such as monitor and screen of TV (17 inch).

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Figure 6.3: The second one has (a) eight a-Si:H TFTs and two

capacitors which consisted of 2 pull-up control devices, 2 pull-down control devices, 4 pull-up output devices and 2 pull-down output devices and (b) used in small loading products such as display panel of cell phone (3.3 inch).

6.1 : Operation of ASG Driver Circuit 123

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6.2 Simulation Results of 14-TFTs-ASG Driver Circuit

The designed parameters of 14-TFTs-ASG driver circuit are widths of a-Si:H TFT de-vices, as shown in Fig. 6.2(a). The original (dashed line) and optimized (solid line) results of the output signal which contains the fall time, the rise time and the ripple voltage in the ASG driver circuit are shown in Fig. 6.5, respectively. The rise time is defined by the interval of time required for leading edge of a pulse raised from 10% to 90% in the peak pulse amplitude and the definition of fall time is contrary to rise time. The ripple voltage is defined by maximum peak to peak voltage after the pulse. These three electrical character-istics are the required specifications in the ASG driver circuit design generally. The inset table of Fig. 6.5 indicates the specifications, original and optimized results. The original result shows that the fall time and the rise time are lower than the given specifications;

however, the ripple voltage compared with our setting criteria is extremely high. There-fore, the established optimization kernel in the unified optimization framework is activated to find the feasible configuration of device widths based on the netlist file of the initial circuit. Finally, the ripple voltage after optimization decreases significantly from 5.419 V to 1.904 V while we keep the rise time and fall time satisfied the required specifications.

Fig. 6.6 shows the initial device widths of this circuit by expert experience and our opti-mized results. There is 35% reduction of the optimized total devices width of a-Si:H TFTs compared with the initial one in this explored ASG driver circuit.

6.2 : Simulation Results of 14-TFTs-ASG Driver Circuit 125

 Figure 6.5: The original/optimized simulation results of 14-TFTs-ASG driver circuit. The inset table indicates specifications, original and optimized results of electrical characteristics.

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Figure 6.6: The comparison of TFT widths in original/optimized results

of 14-TFTs-ASG driver circuit. From our optimized results, there is 35% reduction of the total devices width as

compared to the original one.

6.3 : Simulation Results of 8-TFTs-ASG Driver Circuit 127

6.3 Simulation Results of 8-TFTs-ASG Driver Circuit

Similarly, eight widths of the a-Si:H TFT devices and two charged capacitors are needed to be optimized, as shown in Fig. 6.3(a). Figure 6.7 shows the information of simulation result of the output signal and power dissipation in the second tested circuit before/after optimization. The definition of rise time, fall time and ripple are the same as

Similarly, eight widths of the a-Si:H TFT devices and two charged capacitors are needed to be optimized, as shown in Fig. 6.3(a). Figure 6.7 shows the information of simulation result of the output signal and power dissipation in the second tested circuit before/after optimization. The definition of rise time, fall time and ripple are the same as

在文檔中 16奈米場效應電晶體特性擾動抑制暨TFT-LCD驅動電路設計優化之研究 (頁 132-0)