國 立 交 通 大 學
電信工程研究所
碩 士 論 文
16奈米場效應電晶體特性擾動抑制暨
TFT-LCD驅動電路設計優化之研究
Suppression of 16-nm MOSFET Characteristic Fluctuation and
Design Optimization of TFT-LCD ASG Driver Circuit
研 究 生：李國輔
指導教授：李義明 教授
16 奈米場效應電晶體特性擾動抑制暨
TFT-LCD 驅動電路設計優化之研究
Suppression of 16-nm MOSFET Characteristic Fluctuation and
Design Optimization of TFT-LCD ASG Driver Circuit
研 究 生：李國輔 Student：Kuo-Fu Lee
指導教授：李義明 博士 Advisor：Dr. Yiming Li
國 立 交 通 大 學
電 信 工 程 研 究 所
碩 士 論 文
A ThesisSubmitted to Institute of Communications Engineering College of Electrical Engineering and Computer Engineering
National Chiao Tung University in partial Fulfillment of the Requirements
for the Degree of Master in
Electrical Engineering Augest 2010 Hsinchu, Taiwan
c
Copyright by Kuo-Fu Lee 2010
All Rights Reserved
i
16 奈米場效應電晶體特性擾動抑制暨
TFT-LCD 驅動電路設計優化之研究
學生：李國輔 指導教授：李義明 博士
國立交通大學電信工程研究所碩士班
摘
要
本論文主要分為兩部份，這兩部份皆與類比暨前瞻通訊應用上有相關性，
其中甲部分為半導體
16 奈米場效應電晶體特性擾動抑制分析，乙部分為
TFT-LCD 驅動電路設計優化之研究。分述如下:
甲部分:
隨著手機應用越來越廣泛，使得頻率區段使用變的極為競爭且激烈，然而
高頻段區域尚未有使用執照的限定與規範，因此為了提升動態特性，就加速
了半導體元件微縮在類比電路上的應用。
但是伴隨著金屬氧化半導體場效應電晶體(MOSFET)元件通道尺寸依循
摩爾定律被迅速缩小，元件特性變異成為主要挑戰且對電路設計上極為重
要。而隨機離散摻雜所導致的擾動(RDF)是這些特性變異的主要來源。透過檢
驗元件變異所造成類比電路上的特性變異便成極迫切的議題，在16奈米技術
上去壓抑隨機離散摻雜所造成的特性擾動是個熱門的研究方向。
在本研究中，我們首次探討了兩種不同的雙邊非對稱金屬閘極元件來壓抑
由16奈米金屬氧化半導體場效應電晶體 (MOSFET)元件隨機摻雜效應(RDF)
所導致在元件直流(DC)特性擾動，例如:臨界電壓(V
th)、導通電流(I
on)、夾止
電流(I
off)等等。然而同樣的壓抑現象卻不能實現在非對稱雙金屬閘極(DMG)
元件的交流
(AC)特性上，例如電容(C
g)。這是因為空乏區电容是被通道區域的
摻雜分佈和有效的氧化層厚度所影響。為了有效壓抑離散隨機摻雜所導致的
交流特性擾動，我們進一步探討16奈米隨機摻雜分佈的元件的非對稱現象，
主要分為靠近源極端摻雜和汲極端的摻雜。在通道區域中靠近源極端離散摻
ii
件和電路由隨機摻雜所導致的擾動。本研究結果發現，在靠近汲極端離散摻
雜的元件和一般所使用的元件比較中，臨界電壓擾動(V
th)、導通電流擾動
(I
on)、電導擾動 (g
m)、元件阻抗擾動(r
o)、閘極電容擾動 (C
g)、電路增益
擾動、3dB 頻寬擾動以及单位增益擾動，同時分別降低33.4%, 32.8%, 11.9%,
80.6%, 68.8%, 31.2%, 37.6% 和 47%。所以這樣的横向不對稱通道摻雜可以有
效使用來設計壓抑電晶體的特性擾動。
乙部分:
近年來，隨著面板產業的蓬勃發展，非晶矽薄膜電晶體液晶顯示器(a-Si:H
TFT-LCD)已被廣泛應用於手機之顯示系統。而以非晶矽薄膜電晶體為元件的
閘極驅動電路（TFT-ASG circuit），在薄膜電晶體液體顯示器（TFT-LCD）
面板的製造上已扮演重要的角色。但是，設計薄膜液晶顯示器面板驅動電路
的工作是相當複雜以及費時，工程師必須不斷地調整電晶體參數以滿足節能
產品之需求，像是:降低充放電的時間、降低漣漪電壓以及降低消耗等顯示規
格。
在這篇論文中，我們使用兩個不同的電路架構來改善動態特性並且對這些
動態特性進行電晶體尺寸的最佳化。所使用的最佳化技巧主要是在統合性的
最佳化架構下，以模擬為基礎並結合基因演算法與電路模擬器的演化式方
法。其中第一個含有
14 顆 TFT 的電路除了設計上要求上升時間及下降時間
小於
1.5 微秒，漣漪電壓小於 3 伏特之外，也同時考慮電路面積的最小化；
此電路主要用於大型面顯示器。第二個含有
8 顆 TFT 及 2 顆電容的電路不僅
設計上要求上升時間、下降時間以及漣漪電壓小於
2 微秒和 2 伏特外，還多
增加了功率小於
2 毫瓦特的要求；此電路主要用於手機面板。經過最佳化的
結果，所有動態特性和功率消耗全部符合預期所設定的限制。並且在含有
14
顆
TFT 電路的總元件尺寸上有 35%的降低，而經過敏感度分析測試之後，更
發現這些最佳參數具有優異的穩定性。
接著使用標準的
TFT 4 微米的製程技術，將這些最佳化過後的電路一一實
做出來進行動態特性量測與分析，
14 顆 TFT 電路在量測分析中上升和下降時
間均維持在要求的規格中，並且在漣漪電壓上有
71%的改善，模擬與實際量
測誤差值更是相符合，而在
8 顆 TFT 電路上，上升和下降時間也均符合規格
iii
要求，漣漪電壓更是有
49%上之改善，另外值得注意的是與原始對照組的電
路面積比較，最佳過後的電路面積更是微縮了
36%之多。
透過統合性的最佳化架構，以模擬為基礎並結合基因演算法與電路模擬器
的演化式方法，自動調整電晶體參數來最佳化面板閘極驅動電路的設計，這
將對面板市場和閘極電路設計獲益良多。
總而言之，不管是甲部分還是乙部分，本論文的研究對目前台灣兩兆雙星
產業:半導體和面板帶來技術諸多優勢以及經濟利潤許多遠景。
Abstract (English)
T
his thesis consists of two research topics: the suppression of 16-nm MOSFET Char-acteristic fluctuation and design optimization of TFT-LCD amorphous silicon gate (ASG) driver circuit. The abstract of each study is organized as follows.PART A :
As the minimum feature size of metal-oxide-semiconductor field effect transistor (MOS-FET) has been rapidly scaled down, characteristic variability becomes a major challenge to device technologies and crucial for circuit design. The random dopant fluctuation (RDF) has shown as the major source of variation. It is stringent to examine the device-variability induced characteristic fluctuations of analog circuit and suppression of RD-induced thresh-old voltage (Vth) fluctuation is urgent for 16-nm device technologies. In this part, we for
the first time explore the dual materials gate (DMG) and inverse DMG (inDMG) devices for suppressing RDF-induced DC characteristics fluctuation in 16-nm MOSFET devices. However, the same phenomenon can not enjoy the advantage in AC characteristics of DMG
sketch of random dopants distribution near the source end and the drain end in 16 nm MOSFETs. Discrete dopants near the source and drain ends of channel region induce rather different fluctuations in gate capacitance and dynamic characteristics. Based upon the observed asymmetry properties, a lateral asymmetry channel doping profile engineer-ing is then proposed to suppress the random-dopant-induced characteristic fluctuations in the examined devices and circuits. The results of this study indicate the fluctuations of threshold voltage (Vth), on-current (Ion), transconductance (gm), intrinsic output resistance
(ro), gate capacitance (Cg), circuit gain, 3dB bandwidth, and unity-gain bandwidth for the
cases with dopants near the drain side could be simultaneously reduced by 33.4%, 32.8%, 11.9%, 80.6%, 68.8%, 31.2%, 37.6% and 47%, respectively. Consequently, such lateral asymmetry channel doping profile could be considered to design intrinsic parameter fluc-tuation resistant transistors.
PART B :
Recently, a-Si:H thin film transistor liquid-crystal display (a-Si:H TFT-LCD) has been widely used in display system of mobile phone. For TFT-LCD panel manufacturing, gate driver circuit with hydrogenated amorphous silicon thin-film transistor (TFT-ASG circuit)
plays an important role. Unfortunately, to meet specified display performances of prod-uct, such as low power display system, high dynamic characteristics, and so on, system designers have to manually and iteratively adjust the designing parameters of the a-Si:H TFT-ASG driver circuit, which make the design of a-Si:H TFT-ASG driver circuit system complicated and time-consuming. In this part, we propose two different ASG driver circuit topologies to improve circuits’ dynamic characteristics. The optimization work is con-ducted by the adopted simulation-based evolutionary method integrating genetic algorithm and circuit simulator on the unified optimization framework. The first circuit consisting of fourteen hydrogenated amorphous silicon TFTs (a-Si:H TFTs) used in a large panel is optimized for the specifications of the rise time < 1.5 μs, the fall time < 1.5 μs and the ripple voltage < 3 V with the minimization of total layout area. The second one with eight a-Si:H TFTs and two capacitors used in a display panel of mobile phone is optimized with the further condition that power dissipation < 2 mW. By optimizing the devices’ width and passive components, the optimized results of this study successfully meet the desired spec-ifications, where the sensitivity analysis is conducted to verify the characteristic variation with respect to the optimized parameters. To validate the results, the optimized circuits are fabricated in standard 4-μm a-Si:H TFT technology and the experimental results confirm the practicability of achieved design. The ripple voltage of 1.9 V is successfully obtained
also achieved. For the second circuit, the 49% improvement of ripple voltage and 36% reduction of circuit area are obtained from fabricated sample.
In summary, we have studied two important issues for advance semiconductor and current photonics industries. The results of these studies may benefit 16-nm MOSFET technologies and TFT-LCD circuit design.
ix
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Abstract (Chinese) . . . i
Abstract (English) . . . v
Acknowledgment . . . ix
List of Tables . . . xv
List of Figures . . . xvi
1 Introduction 1 1.1 Suppression of 16-nm MOSFET Characteristic Fluctuation . . . 1
1.1.1 Motivation . . . 1
1.1.2 Literature Review . . . 4
1.1.3 The Study of This Part . . . 5
1.2 Design Optimization of TFT-LCD ASG Driver Circuit . . . 8
1.2.1 Motivation . . . 8
1.2.2 Literature Review . . . 11 xi
1.2.3 The Study of This Part . . . 12
1.3 Outline . . . 14
1.4 PART A : Suppression of 16-nm MOSFET Characteristic Fluctuation . . . 15
2 Simulation and Fabrication 17 2.1 Manufacturing Process . . . 18
2.2 Physical Modeling and Numerical Methods . . . 21
2.3 Simulation Technique . . . 26
2.4 Summary of this Chapter . . . 44
3 RDF Effects in Planar MOSFET and Analog Circuits 45 3.1 DC Characteristic Fluctuations . . . 46
3.2 AC Characteristic Fluctuations . . . 54
3.3 Characteristic Fluctuations of Analog Circuits . . . 60
3.3.1 Current Mirror . . . 60
3.3.2 Common Source Amplifier . . . 61
3.4 Summary of this Chapter . . . 68
4 RDF Suppression Approaches 69 4.1 Characteristic Fluctuations of Dual Material Gate Device . . . 70
4.2 Characteristic Fluctuations of Lateral Asymmetric Channel Device . . . 81
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CONTENTS xiii
4.2.1 Characteristic Fluctuations in Asymmetric Device . . . 81
4.2.2 Characteristic Fluctuations in Analog Circuits . . . 92
4.3 Summary of this Chapter . . . 100
4.4 PART B : Design Optimization of TFT-LCD ASG Driver Circuit . . . 101
5 Optimization Technique 103 5.1 Genetic Algorithm . . . 103
5.2 Variation of Operator in the Genetic Algorithm . . . 107
5.3 The Simulation-Based Optimization Methodology . . . 110
5.3.1 The Optimization Flow . . . 110
5.3.2 The Performance of Developed Optimization Methodology . . . 111
5.4 Summary of this Chapter . . . 116
6 The ASG Driver Circuit and Simulation Results 117 6.1 Operation of ASG Driver Circuit . . . 118
6.2 Simulation Results of 14-TFTs-ASG Driver Circuit . . . 124
6.3 Simulation Results of 8-TFTs-ASG Driver Circuit . . . 127
6.4 Sensitivity Analysis . . . 130
6.5 Summary of this Chapter . . . 134
7 Design, Fabrication and Measurement 135
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7.1 Process Flow of a-Si:H Thin Film Transistors . . . 135
7.2 Experimental Results of 14-TFTs-ASG Driver Circuit . . . 139
7.3 Experimental Results of 8-TFTs-ASG Driver Circuit . . . 146
7.4 Summary of this Chapter . . . 152
8 Conclusions 153 8.1 Suppression of 16-nm MOSFET Characteristic Fluctuation . . . 154
8.1.1 Summary . . . 154
8.1.2 Future Work . . . 159
8.2 Design Optimization of TFT-LCD ASG Driver Circuit . . . 160
8.2.1 Summary . . . 160
8.2.2 Future Work . . . 163
References . . . 164
Appendix A VITA . . . 184
List of Tables
3.1 Summarized dynamic characteristic fluctuations of the nano-MOSFETs circuit. . . 67 5.1 The parameters setting of genetic algorithm in our circuit design
optimiza-tion experiments. The designed parameters of populaoptimiza-tion size, crossover rate, and mutation rate are suitable for ASG driver circuits. . . 113 8.1 The comparison of suppression techniques. . . 157
1.1 The continuously scaling of physical gate length with years from ITRS Roadmap 2007 [2]. The physical gate length is decreased from 32 nm to 16 nm during year 2007 to 2013. . . 3
1.2 (a) Combining display panel and gate IC’s by bonding process of the con-vention design (b) Display panel and integrated gate driver circuit are fab-ricated simultaneously of the on going design. . . 10
2.1 Illustrations of planar MOSFET flow in National Nano Device Laboratories (NDL). The process flow consists of 150 steps for planar devices. . . 20
2.2 The RDF-, LER-, WKF-, OTF-induced Vthfluctuation for NMOS devices,
where the total σVthis calculated with Eq. 2.9. . . 32
LIST OF FIGURES xvii
2.3 (a) Discrete dopants randomly distributed in the (96 nm)3cube with the av-erage concentration of 1.5×1018cm−3. There will be 1327 dopants within the cube, but dopants may vary from 0 to 14 ( the average number is 6 ) within its 216 sub cubes of 16 nm× 16 nm × 16 nm ((b) and (c)). . . 33
2.4 The histogram of the dopants in 216 sub cubes for 16 nm devices. The dopants number can be describe by Gaussian Distribution with a mean of six. 34
2.5 The sub-cubes are equivalently mapped into channel region for discrete dopant simulation as shown in MOSFET (a) control, (b) DMG, and (c) inverse DMG devices, respectively. (d) The properties of metal material used in this study. . . 35
2.6 The sub-cubes are equivalently mapped into channel region for discrete dopant simulation as shown in MOSFET (a) conventional lateral asymmet-ric channel (LAC) and (b) inverse LAC devices, respectively. . . 36
2.7 The histogram of the dopants in 216 sub cubes (16 nm× 16 nm × 8 nm) for near-source-end channel doping profile of conventional LAC device. The dopants number can be describe by Gaussian Distribution with a mean of six. . . 37
2.8 The histogram of the dopants in 216 sub cubes (16 nm× 16 nm × 8 nm) for near-drain-end channel doping profile of inverse LAC device. The dopants number can be describe by Gaussian Distribution with a mean of six. . . 38
2.9 (The current mirror of analog circuit consisted of NMOS for exploring the variation sources induced current (IREF/IOU T) mismatch. . . 39
2.10 (a) The common-source circuit is used as a tested circuit to explore the fluc-tuation of high-frequency characteristics. (b) The input signal is a sinusoid input wave with 0.5 V offset. The frequency is swept from 1×108 Hz to 1×1013Hz [33]. . . 40
2.11 The flowchart for the mixed-mode device circuit coupling simulation. The devices simulation is performed first and get the initial solution of the de-vices potential. The mixed-mode simulation is then executed until the final step [83]. . . 41
2.12 TA flowchart of the decoupling algorithm. First we solve the nonlinear Poisson equation until it is convergence, and then the current continuity equation of electron and hole is following solved. If the error is less than the tolerance, the program stops. . . 42
LIST OF FIGURES xix
2.13 A flowchart for solving decoupled PDE. First the simulation domain have to be discretized. Applying the finite element method approximation to the decoupled PDE, we obtained the nonlinear algebraic equations correspond-ing to the discretized grid. The Newton linearization method is then used to linearized the nonlinear equations. Finally, the linear algebraic equation-scan be solved using either direct or iterative method [84]. . . 43
3.1 Example of a 16-nm planar MOSFET with atomistic doping profiles both in the channel and S/D regions. (a) The actual locations of random dis-crete dopants and (b) The fluctuation in electrostatic potential are illus-trated. There are 7 and 358 dopants located in channel region and S/D region, respectively. . . 49
3.2 Comparison of RDF effect in channel versus S/D region of a planar MOS-FET. The Vthfluctuations are 42.8 mV and 20 mV for channel and S/D RDF
only cases, respectively. The Vth fluctuation is 47.1 mV for both channel
and S/D RDF cases. Note that the channel RDF introduced around 90% of Vthfluctuation. . . 50
3.3 DC characteristic fluctuations of ID − VG characteristics, where the solid
line shows the nominal device, whose channel doping profile is continu-ously doped with 1.5×1018cm−3, and the dashed lines are random-dopant-fluctuated devices. The threshold voltage is determined from a current cri-terion that the drain current larger than 10−7A. Ion is determined at VG =
0.8 V and Iof f is determined at VG= 0 V. . . 51
3.4 DC characteristic fluctuations of (a) Vth, (b) Iof f, (c) Ion, and (d) gm
charac-teristics. As the number of dopants in channel is increased, the devices Vth
is increased and thus decreases the on- and off-state current and transcon-ductance. The magnitude of the spread characteristics increases as the number of dopants increase. Furthermore, the position of random dopants induced different fluctuation of characteristics in spite of the same number of dopants. . . 52
3.5 Extracted band profile for (c) discrete dopant-located below surface and (c) discrete-dopant-located in the surface devices. Several potential barriers in the discrete-dopant-located in the surface device are induced by the cor-responding dopants in devices channel and therefore change the threshold voltage. (b) Discrete dopants randomly distributed in the (96 nm)3 cube with the average concentration of 1.5×1018cm−3. . . 53
LIST OF FIGURES xxi
3.6 The total gate capacitance (Cg,total) results from the shunt of the gate-drain
capacitance (Cgd), the gate-source capacitance (Cgs), and the gate-bulk
ca-pacitance (Cgb). . . 55
3.7 (a) The CG− VGcharacteristics of the 216 discrete-dopant-fluctuated
con-trol devices. The red solid lines indicate the devices with 0.8 drain bias voltage and gray dash lines are the devices with zero drain bias voltage. (b) Fluctuation of total gate capacitance (Cg,total) of the 216 discrete dopant
fluctuated 16-nm-gate control devices with zero and 0.8 drain bias voltage. The total gate capacitance (Cg,total) results from the shunt of the gate-drain
capacitance (Cgd), the gate-source capacitance (Cgs), and the gate-bulk
ca-pacitance (Cgb). . . 56
3.8 Fluctuation of gate-drain capacitance (Cgd) for the 216 discrete dopant
fluc-tuated 16-nm-gate planar MOSFETs. The symbol and error bar denote the characteristics of nominal device and fluctuation, respectively. As the VD
changes from 0 V (circles) to 0.8 V (squares), the wider of depletion layer at the drain junction decreases the Cgdand thus exhibits less fluctuation. . . 57
3.9 Fluctuation of gate-source capacitance (Cgs) for the 216 discrete dopant
fluctuated 16-nm-gate control device. The symbol and error bar denote the characteristics of nominal device and fluctuation, respectively. The Cgs is
increased because of the channel length modulation at drain voltage of 0.8 V. 58
3.10 Fluctuation of gate-body capacitance (Cgb) of the 216 discrete dopant
fluc-tuated 16-nm-gate control device. The symbol and error bar denote the characteristics of nominal device and fluctuation, respectively. Cgb is
in-significant due to the relatively larger distance between gate and substrate. . 59
3.11 The scatter plot of current mirror current for discrete-dopant-induced fluc-tuated devices. The filled-in blue symbols indicates the flucfluc-tuated devices and open symbol is nominal devices, respectively. . . 64
3.12 DC characteristic fluctuations of ro of the 216 discrete dopant fluctuated
16-nm-gate control device. As the dopant number is increased, the devices Vthis increased and thus decreased ro. . . 65
3.13 The (a) frequency response, (b) high-frequency circuit gain, (c) 3dB band-width, (d) and unity-gain bandwidth fluctuations of the studied discrete-dopant-fluctuated 16-nm-gate common source amplifier. . . 66
LIST OF FIGURES xxiii
4.1 The energy band diagram of (a) off-state and (b) on-state for control, DMG and inverse DMG nominal device, respectively. For the higher WK near the source side or the drain side, it may induce higher intrinsic electrostatic potential barrier for both off- and on-state. . . 73
4.2 The 14 random dopants induce rather different potential profiles due to WK difference in spite of the same number and position of dopants which are extracted from (b) between on-state and off-state for (a) DMG and (c) inverse DMG device. . . 74
4.3 The ID−VGcurves of (a) inverse DMG and (b) DMG devices. The nominal
values and normalized characteristic variations for inverse DMG and DMG devices are summarized in the insets, respectively. . . 75
4.4 (a) The surface potential energy induced by 14 random dopants for control, DMG and inverse DMG devices, respectively. (b)-(d) the slices of potential energy for dopant near source side of control, DMG and inverse DMG devices, respectively. The dopants will induce potential deviation φdopant,
and the high, low, and control WK-induced potential barriers are φH, φL
4.5 (a) The surface potential energy induced by 14 random dopants for control, DMG and inverse DMG devices, respectively. (b)-(d) the slices of poten-tial energy for dopant near drain side of control, DMG and inverse DMG devices, respectively. The phenomenon for dopant near the drain side can not enjoy the advantage in the inverse DMG structure because the carrier controllability is totally decided at the source edge. . . 77
4.6 Comparison of nominal (a) surface potential, (b) lateral electric field, (c) electron velocity, and (d) ID−VGcurve for DMG device and control devices. 78
4.7 (a) Comparison of discrete-dopant-fluctuated ID− VGcurves of DMG
de-vice (red line) and control dede-vice (gray line). (b) Iof f, (c) Ion, and (d) Vth
fluctuations which extracted from (a). . . 79
4.8 The CG− VG characteristics of the 216 discrete-dopant-fluctuated control
and DMG devices with (a) zero volt drain bias and (b) 0.8 volt drain bias voltage. The gray solid lines indicate the control devices and red dash lines are the DMG devices. . . 80
LIST OF FIGURES xxv
4.9 The discrete dopant fluctuated devices are then classified into two groups: (a) LAC devices with dopants near source end and (b) inLAC devices with dopants near drain end. For the LAC device, the selection criterion is that device has more than three dopants in the near-source-end channel but with zero or one dopant locating near the other end. The inLAC devices are then selected accordingly. . . 85
4.10 The Averaged of total gate capacitance (Cg,total) for LAC and inLAC
de-vices at (a) VD = 0 V and (b) VD = 0.8 V. Both LAC and inLAC devices
exhibit a quite similar C-V characteristics under VD = 0 V and VD = 0.8 V. . 86
4.11 Fluctuations of total gate capacitance for LAC and inLAC devices at (a) VD
= 0 V (b) VD = 0.8 V. The σCg,totalof the LAC devices show a significantly
large fluctuation as compared to the inLAC devices at VD = 0.8 V. . . 87
4.12 Fluctuations of (a) Cgd and (b) Cgs at VD = 0 V. The σCgs is more
pro-nounced and becomes major source of fluctuation for the LAC devices. Similarly, the σCgd dominates the fluctuation of gate capacitance for the
4.13 Fluctuations of (a) Cgdand (b) Cgsat VD = 0.8 V. For inLAC devices, since
the major source of fluctuation is contributed by Cgd, the σCg,tatol is well
controlled. For the LAC devices, the major source of fluctuation, that is the σCgs, could not be reduced. . . 89
4.14 The discrete-dopant-induced ID−VGcharacteristic fluctuations of (a) LAC
and (b) inLAC devices, respectively. The σVth of inLAC device is 1.78
times smaller than LAC device because of the smaller fluctuation of injec-tion velocity and thus a smaller current variainjec-tion for dopants located near the drain-end of the channel. . . 90
4.15 (a) The comparison of ID − VGcharacteristics, where the solid lines show
the control devices and the dashed lines are inLAC devices, respectively. The DC characteristic fluctuations of, (b) Iof f, (c) Ion, and (d) Vth, where
the triangle symbols show the control devices and the cross symbols are inLAC devices, respectively. . . 91
4.16 The IOU T fluctuation (σIOU T) and normalized IOU T fluctuations for the
studied current mirror circuit with control device and inLAC device, re-spectively, where the normalized IOU T fluctuations are defined by standard
LIST OF FIGURES xxvii
4.17 The scatter plots for comparing the current mirror current with control de-vices (filled-in blue symbols) and inLAC (open symbols) dede-vices, respec-tively. . . 95
4.18 High frequency response of the studied circuits. The solid lines are the results of inLAC devices and the dash lines are for the results of LAC de-vices. The inset is comparison of different fluctuation components between the studied two group devices. . . 96
4.19 DC characteristic fluctuation of (a) gm and (b) ro between control and
in-LAC devices. As the dopant number is increased, the devices Vth is
in-creased and thus inin-creased ro and decreases transconductance. The trian-gle symbols show the control devices and the cross symbols are inLAC devices, respectively. . . 97
4.20 Comparison of gate capacitance fluctuations of the discrete-dopant-fluctuated 16-nm-gate devices generated from the proposed inLAC devices (dashed line) and control device (solid line). . . 98
4.21 Comparison of (a) frequency response fluctuations, (b) circuit gain, (c) 3dB bandwidth, (d) and unity-gain bandwidth fluctuations of the 216 discrete-dopant fluctuated 16-nm-gate planar MOSFET circuit with inLAC and con-trol devices. The circle symbols show the concon-trol devices and the cross symbols are inLAC devices, respectively. . . 99
5.1 The general scheme of an evolutionary algorithm consist of population, parent selection mechanism, variation operator, survivor selection mecha-nism, initialization procedure and terminal condition . . . 106
5.2 The variation operators, (a) crossover and (b) mutation, used in this work. For the crossover, we randomly choose one point and split two parents at the point, then we exchange the tails of them to create two offspring. After that, the mutation enable to randomly choose two gene in one individual and exchange them with mutation rate. . . 109
5.3 The algorithm scheme of the solver to optimize the proposed ASG driver circuits in this thesis.The replacement is age-based but with 10% elitist and 30% regenerate random individual. After replacement complete, we check whether the solution meets requirements or the max generation is reached. . 112
LIST OF FIGURES xxix
5.4 (a) and (b) The comparison of the score convergence behavior of the algo-rithm in two ASG driver circuits among population sizes are 50, 100, and 150, where the crossover and mutation rate is fixed at 0.6, respectively. . . . 114 5.5 (a) and (b) The comparison of the score convergence behavior of the
al-gorithm in two ASG driver circuits among mutation rates are 0.4, 0.6, and 0.8, where the crossover a is fixed at 0.6 and population size is fixed at 100, respectively. . . 115 6.1 (a) The common schematic of active matrix liquid-crystal display panel
controlled by ASG driver circuit in real product. (b) The components of one stage ASG driver circuit and the output waveform affected by corre-sponding component of ASG driver circuit. . . 120 6.2 The first ASG driver circuit (a) has fourteen a-Si:H TFTs which consisted
of 3 pull-up control devices, 3 pull-down control devices, 3 pull-up out-put devices and 5 pull-down outout-put devices and (b) used in large loading products such as monitor and screen of TV (17 inch). . . 121 6.3 The second one has (a) eight a-Si:H TFTs and two capacitors which
con-sisted of 2 pull-up control devices, 2 pull-down control devices, 4 pull-up output devices and 2 pull-down output devices and (b) used in small load-ing products such as display panel of cell phone (3.3 inch). . . 122
6.4 The timing diagram of 14-TFTs-ASG driver circuit. The CLK and CLKB denote the clock signal and clock bar signal and STV/Vn−1is inputted pulse
signal. The Vnand VN are the output signal which supply for the panel and
next stage, respectively. . . 123 6.5 The original/optimized simulation results of 14-TFTs-ASG driver circuit.
The inset table indicates specifications, original and optimized results of electrical characteristics. . . 125 6.6 The comparison of TFT widths in original/optimized results of
14-TFTs-ASG driver circuit. From our optimized results, there is 35% reduction of the total devices width as compared to the original one. . . 126 6.7 The original/optimized simulation results of 8-TFTs-ASG driver circuit.
The inset table indicates specifications, original and optimized results of electrical characteristics. . . 128 6.8 The comparison of TFT widths in original/optimized results of
8-TFTs-ASG driver circuit. Comparing with initial total device width, the opti-mized result is almost same. . . 129 6.9 The sensitivity analysis of the14-TFTs-ASG driver circuit. (a) ± 0.5 μm
of each width with L=4 μm (b) ± 0.2 μm of each length with optimized widths sequentially. . . 132
LIST OF FIGURES xxxi
6.10 The sensitivity analysis of the 8-TFTs-ASG driver circuit. (a) ± 0.5 μm of each width with L=4 μm (b)± 0.2 μm of each length with optimized widths sequentially. . . 133
7.1 The process flow of inverted-staggered back-channel etched (BCE) type of a-Si:H TFT. . . 137
7.2 (a) The cross-section view of SEM picture of fabricated TFT sample. The process variation of (b) L5 and (c) L11 of 14-TFTs-ASG driver circuit and (d) L3 and (e) L6 of 8-TFTs-ASG driver circuit, respectively. . . 138
7.3 The tested chip layout of six stages gate driver circuit which is 1320 μm wide and 1050 μm high and occupied the area of 1.386 mm2. . . 140
7.4 The equipments of (a) a Chroma 58162-E signal generator and (b) a Tek-tronix DP04054 oscilloscope which we used to carry out the measurement results. . . 141
7.5 The detail setting of input signal of 14-TFTs-ASG driver circuit by using a Chroma 58162-E signal generator. . . 142
7.6 The experimental results of rise time, fall time and ripple voltage for 14-TFTs-ASG driver circuit are measured by using a Tektronix DP04054 os-cilloscope. . . 143
7.7 ((a) Comprehensive comparison among the fabrication data of the origi-nal/optimized setting and the specifications. (b) The comparison of simu-lation and characterization results of 14-TFTs-ASG driver circuit. . . 144 7.8 (a) The optical image of the fabricated 14-TFTs-ASG driver circuit which
occupied the area of 0.231 mm2(1050 μm× 220 μm) . (b) The comparison of a single-stage circuits area for 14-TFTs-ASG driver circuit. . . 145 7.9 The tested chip layout of eleven stages gate driver circuit which is 500 μm
wide and 3218 μm high and occupied the area of 1.795 mm2. . . 147 7.10 The detail setting of input signal of 8-TFTs-ASG driver circuit by using a
Chroma 58162-E signal generator. . . 148 7.11 The experimental results of rise time, fall time and ripple voltage for
8-TFTs-ASG driver circuit are measured by using a Tektronix DP04054 os-cilloscope. . . 149 7.12 (a) Comprehensive comparison among the fabrication data of the
origi-nal/optimized setting and the specifications. (b) The comparison of simu-lation and characterization results of 8-TFTs-ASG driver circuit. . . 150 7.13 (a) The optical image of the fabricated 8-TFTs-ASG driver circuit which
occupied the area of 0.152 mm2. (b) The comparison of a single-stage circuits area for 8-TFTs-ASG driver circuit. . . 151
LIST OF FIGURES xxxiii
8.1 The effectiveness of the fluctuation suppression in both the inLAC-device and common source amplifier, compared with the results of control-device and circuit. . . 158 8.2 The dynamic characteristics and circuit area of ASG driver circuits are
compared among specification, original simulation, optimized simulation, original fabrication, and optimized fabrication. . . 162
Chapter 1
Introduction
1.1
Suppression of 16-nm MOSFET Characteristic
Fluc-tuation
In this section, we brief the motivation, literature review and the study of the suppression of 16-nm MOSFET characteristic fluctuation.
1.1.1
Motivation
The mobile-handset market continues to be a dynamic and growing one, enabled by technology advances that include increased bandwidth, greater processing performance, increased power efficiency, and improved display technologies to deliver compelling user
experiences. As for multi-Gb/s wireless communications which allocated in the unlicensed spectrum around 60 GHz have been the topic of intense research in the recent past and de-vices are expected to hit the market shortly. Key aspects behind the increasing interest for technology deployment are the feasibility of the radio in scaled CMOS and the successful demonstration of Gb/s transmissions.
Although the scaling of Complementary metal-oxide-semiconductor (CMOS) devices feature size offer the possibility of operation beyond 100 GHz where new applications are envisioned in the near future, including imaging and spectroscopy systems for scientific, medical, space, and industrial applications at low cost, light weight and easy assembly [1]. The physical gate length of metal-oxide-semiconductor field effect transistors (MOS-FETs) roll-off follows the International Technology Roadmap for Semiconductors (ITRS), as shown in Fig. 1.1. However, as the dimension of CMOS devices shrunk into sub-65 nm, double-digit channel dopants make transistor behaviors more complicated to be character-ized with conventional ”continuum modeling”. Random nature of discrete dopant distribu-tion results in significantly random fluctuadistribu-tions, such as the deviadistribu-tion of threshold voltage (Vth), drive current mismatch, dynamic characteristic fluctuations, and so on. The
mod-ern scaled-down devices and characteristics mismatches make maintaining an acceptable dynamic characteristic in analog circuit becomes more challenging.
1.1 : Suppression of 16-nm MOSFET Characteristic Fluctuation 3
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Figure 1.1: The continuously scaling of physical gate length with years from ITRS Roadmap 2007 [2]. The physical gate length is decreased from 32 nm to 16 nm during year 2007 to 2013.
1.1.2
Literature Review
Silicon-based devices are scaled down continually in order to increase density and speed. The gate lengths of scaled metal-oxide-semiconductor field effect transistors (MOSFETs) have been the sub-30 nm for 45 nm node high-performance circuit design [3]. Moreover, the devices with sub-10-nm-gate lengths have been currently investigated [4-7]. For the radio-frequency/mixed-signal applications in mobile phone, a cutoff frequency higher than 200 GHz have been also reported [8,9]. In device point of view, dual material gate (DMG) and lateral asymmetric channel (LAC) were recently proposed to improve device and dy-namic performance sequentially [10]. Yield analysis and optimization, which take into account the manufacturing tolerances, model uncertainties, variations in the process pa-rameters, etc., are known as indispensable components of the circuit design methodology [11-15]. However, attention is seldom drawn to the existence of dynamic characteristic fluctuations of active device due to random dopant placement. With geometries of MOS-FET shrink, the intrinsic device parameter variations such as line edge roughness [16], the granularity of the polysilicon gate [17,18], random discrete dopants [19-38] effects have brought significant impacts on device characteristic fluctuations; and it is imperative to model and mitigate them in silicon technology. Furthermore, various randomness ef-fects resulting from the random nature of manufacturing process, such as ion implantation,
1.1 : Suppression of 16-nm MOSFET Characteristic Fluctuation 5
diffusion, and thermal annealing, have induced significant fluctuations of electrical charac-teristics in nanometer scale (nanoscale) MOSFETs. The number of dopants is of the order of tens in the depletion region of a nanoscale MOSFET, whose influence on device charac-teristic is large enough to be distinct [19].
Various random dopant effects have been recently studied in both experimental and the-oretical approaches [19-38]. Fluctuations of characteristics are caused not only by a varia-tion in an average doping density, which is associated with a fluctuavaria-tion in the number of impurities, but also with a particular random distribution of impurities in the channel re-gion. Diverse approaches have recently been reported to study fluctuation-related issues in semiconductor devices [19-36] and digital integrated circuit [37-41]. Unfortunately, these studies are mostly focused on the fluctuations of threshold voltage and DC characteristics. However, the investigation of RDF on gate capacitance as well as dynamic characteristics due to random dopant placement is still not clear for nanoscale MOSFET circuit. Dynamic characteristic fluctuations of the nanoscale transistor circuit induced by random dopants and the effectiveness of fluctuation suppression technique are thus intensively explored.
1.1.3
The Study of This Part
In this thesis, an experimental validated three-dimensional (3D) ”atomistic” coupled device-circuit simulation approach will be employed to analyze the discrete-dopant-induced
gate capacitance dynamic characteristic fluctuations for the tested 16 nm MOSFET and analog circuits, concurrently capturing ”dopant concentration variation” and ”dopant po-sition fluctuation”. Not only current mirror circuit but also common source amplifier had been investigated in this work. The statistically generated large-scale doping profiles are similar to the physical process of ion implantation and thermal annealing [39]. Based on the statistically (totally randomly) generated large-scale doping profiles, device simulation is performed by solving a set of 3D drift-diffusion equations with quantum corrections by the density gradient method, which is conducted using a parallel computing system [39-45]. In estimation of the characteristics variations in circuit, for obtaining more physical insight device and pursuing higher accuracy, a coupled device-circuit simulation with dis-crete dopant distribution is conducted to examine the associated behavior of circuit, which concurrently considers the discrete-dopant-number- and discrete- dopant-position-induced fluctuations. Notably, the statistically sound analyzing methodology was quantitatively ver-ified with the experimentally measured data of 20 nm CMOS for the best accuracy [27].
We are then proposed the DMG and inverse DMG devices for suppressing RDF-induced DC characteristics fluctuation in 16-nm MOSFET devices. The physical mechanism of DMG devices to suppress RDF-induced DC characteristics fluctuation are investigated and discussed. Then based upon the asymmetric sketch of the random dopants distribution near the source end and the drain end, it is found that discrete dopants near the source and drain
1.1 : Suppression of 16-nm MOSFET Characteristic Fluctuation 7
ends of channel region induce rather different fluctuations in gate capacitance and dynamic characteristics. This asymmetry property is utilized to design a lateral asymmetry chan-nel doping profile for the reduction of random-dopant-induced characteristic fluctuations. Consequently, fluctuations of DC characteristics, average gate capacitance, circuit gain, 3dB bandwidth, and unity-gain bandwidth for the devices with dopants near the drain side are significantly reduced. The lateral asymmetry channel doping profile could be consid-ered to design intrinsic parameter fluctuation resistant transistors. The function-dependent and circuit-topology- dependent characteristic fluctuations resulted from random nature of discrete dopants are thus for the first time discussed in this thesis.
1.2
Design Optimization of TFT-LCD ASG Driver Circuit
In this section, the introduction to this study of design optimization of TFT-LCD ASG driver circuit is stated briefly.
1.2.1
Motivation
Hydrogenated amorphous silicon thin film transistors (a-Si:H TFT) are famous for their uniform and low-cost process. Such characteristics have attracted more attention in various applications such as active-matrix organic light-emitting diode (AMOLED) pixels, sen-sor amplifier, oscillator and gate driver. Furthermore, using the technology of integrated a-Si TFT gate driver on medium and large size TFT-LCD has become the main stream to reduce the cost of manufacturing. The reason is that the gate IC’s and display panel are fabricated individually and combined each other by bonding process of conventional design, as shown in Fig. 1.2. However, the bonding process may results in mechanical re-liability problem. Therefore, the integrated circuits using a-Si:H TFTs have been proposed to handle reliability and give several advantages such as mature manufacturing technol-ogy which can be fabricated with the standard 5 or 4 mask processes, low temperature, low-cost processing, and elimination of the driver ICs. Although the integrated a-Si gate driver circuit has advantage of lowering fabrication cost, it is important and requested to achieve superior and stable output waveform of a-Si integrated gate (ASG) driver circuit in
1.2 : Design Optimization of TFT-LCD ASG Driver Circuit 9
modern TFT-LCD panel industry. To meet specified display performances of product, trial-and-error method is generally adopted by circuit designers to tune circuit parameters of the a-Si:H TFT-LCD circuit, which make the design of a-Si:H TFT-LCD system complicated and time-consuming. As a result, reducing time-consuming while maintain the superior dynamic characteristics is crucial issue and challenging.
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Figure 1.2: (a) Combining display panel and gate IC’s by bonding process of the convention design (b) Display panel and integrated gate driver circuit are fabricated simultaneously of the on going design.
1.2 : Design Optimization of TFT-LCD ASG Driver Circuit 11
1.2.2
Literature Review
LCD displays for application of smart phone is being developed rapidly in points of reso-lution, pixels per inch (PPI), number of color and brightness. Thus, integrating driver circuit on the TFT backplane is one of the fascinated challenge in QVGA resolution LCD panel because of its many advantages such as overall cost reduction, compactness, and mechani-cal reliability [46-50]. Diverse approaches such as low temperature polycrystalline silicon (LTPS), hydrogenated amorphous silicon (a-Si:H) [50,51], and zinc-oxide (ZnO) [53,54] are proposed as an active channel material in n-channel thin-film-transistors (TFTs) as well as gate driver circuits sequentially. However, the additional processes which resulted in increasing cost are necessary in LTPS technology. Furthermore, there are several reliable problems of amorphous silicon gate (ASG) driver circuit should be concerned in ZnO film [55]. Therefore, a-Si process has been main stream in gate driver circuit of TFT-LCD for mobile application because of the cost merits due to simple process and high yield in nowadays [56-58]. In general, the ASG driver circuit is requested to achieve superior and stable output waveform. Therefore, dynamic characteristics are usually obtained empiri-cally to meet the required specifications [59-61] for given ASG circuits. Trial-and-error method is generally adopted by circuit designers to tune circuit parameters including de-vice geometry, biasing, etc. This design flow generally is a time-consuming task to meet all desired specifications in display circuit manufacturing. In addition, the methodology
of simulation-based evolutionary approach has recently been proposed for optimizing de-vice’s doping profile [62-64] and equivalent circuit model parameter extraction [65] in our previous works. Optimization results of these studies computationally have confirmed the robustness and efficiency of the proposed method. Systematical optimization approach, based upon simulation-based evolutionary methodology, will be an interesting study for optimal design of TFT-LCD panel circuits, and thus benefit their manufacturing.
1.2.3
The Study of This Part
In this thesis, we will demonstrate two optimized gate driver circuits on glass substrate to improve dynamic characteristics. Then simulation-based evolutionary algorithm on the unified optimization framework [66] is successfully advanced on performing optimal de-sign of these two circuits on the a-Si:H TFT-LCD panel. The first proposed circuit consists of three pull-up control devices, three pull-down control devices, three pull-up output de-vices and five pull-down output dede-vices, where all dede-vices’ widths are parameters to be designed for the specifications of the rise time < 1.5 μs, the fall time < 1.5 μs and the rip-ple voltage < 3 V while we simultaneously consider the minimization of total layout area. The second proposed circuit consists of two pull-up control devices, one pull-down control device, three pull-up output devices and two pull-down devices, where the eight devices’ widths and two charged capacitances are tuning parameters to be optimized, and the rise
1.2 : Design Optimization of TFT-LCD ASG Driver Circuit 13
time < 2 μs, the fall time < 2 μs, the ripple voltage < 2 V and the power dissipation < 2 mW are adopted as targets to be achieved. As for the optimized solutions achieved by the method, the sensitivity analysis is simultaneously considered to verify how the varia-tion in dynamic characteristics of optimized circuits. We analyze a selected and modified solution for two ASG driver circuits by ± 0.5 μm of each width and ± 0.2 μm of each length with optimized widths sequentially. The final optimized ASG driver circuits are further fabricated with 4-μm process a-Si:H TFT technology. The comparison of dynamic characteristics of measurement and simulation are discussed in detail.
1.3
Outline
The first part of thesis is organized as follows. The fabrication process, physical mod-eling and numerical methods, analyzing technique for studying the random dopants ef-fect in nanoscale device and circuit are given in Chap. 2. In Chap. 3, we examine the discrete-dopant-induced characteristic fluctuations in the 16-nm MOSFET devices and cir-cuits. Then, the suppression techniques for discrete-dopant-induced fluctuations are pro-posed and discussed in Chap. 4.
As for the second part, the genetic algorithm and the implemented simulation-based op-timization method are introduced in Chap. 5. In Chap. 6, the explored ASG driver circuits are optimized and discussed. In Chap. 7, the fabricated and measured results are shown to validate our theoretical results. Finally, conclusions and suggested future work of the thesis are drawn in Chap. 8.
15
PART A
Suppression of 16-nm MOSFET
Characteristic Fluctuation
Chapter 2
Simulation and Fabrication
I
n this chapter, a large-scale statistically sound “atomistic” device-circuit coupled sim-ulation approach is proposed to characterize the random-dopant-induced characteris-tic fluctuations when the gate length of MOSFET integrated circuits is down to 16 nm concurrently capturing the discrete-dopant-number- and discrete-dopant-position-induced fluctuations. We experimentally quantified the random dopant fluctuation (RDF) induced threshold voltage (Vth) standard deviation up to 40 mV for sub-20-nm-gate planarmetal-oxide-semiconductor field effect transistors. The accuracy of the simulation technique is confirmed by the use of experimentally calibrated transistor physical model.
2.1
Manufacturing Process
The standard MOSFET process flow at National Nano Device Laboratories (NDL) could be summarized as follows:
1. Active area patterning;
2. Shallow trench isolation (STI) formation (chemical-mechanical polishing (CMP)); 3. Narrow width device trimmed down upon STI etching;
4. P/N-well implant;
5. Gate oxide and poly gate patterning (I-line ready, deep-UV under planning); 6. Re-oxidation;
7. N/P halo and lightly doped drain shallow junction; 8. SiN MSW;
9. N+/P+ source/drain;
10. Spike rapid thermal anneal (RTA); 11. Low-temperature annealing NiSi;
12. Strained SiN contact etch stop layer (CESL) and interlayer dielectric (ILD); 13. Contact patterning (I-line ready, deep-UV under planning);
14. Ti/TiN/AlCuSi/TiN deposition; 15. M1 patterning;
2.1 : Manufacturing Process 19
17. Via patterning;
18. Ti/TiN/AlCuSi/TiN deposition; and 19. Sintering.
The entire process flow for planar MOSFET contains about 150 steps, which may take 3 to 4 months. Fig. 2.1 illustrates several key process steps for planar MOSFET. The process is started from active area patterning. After shallow-trench isolation (STI) formation, the device width is trimmed down upon STI etching. Channel doping is performed to adjust threshold voltage (Vth) of transistor, using masked ion implantation. To relieve the etch
damage; a sacrificial oxide is removed before gate oxidation. Thermal oxide is grown and in-situ heavily doped N+ poly-silicon is deposited. After the deposition and trimmed down of gate hard mask, the pocket implantation technique is used for the suppression of the short channel effect. Composite spacer of silicon oxide and nitride are deposited and etched anisotropically. After the gate and spacer formation, heavily doped N+ junction is made with Arsenic implantation. Low-thermalbudget activation process is used for dopant activation and control of doping profile. After inter-layer-dielectric deposition, tungsten is used for metal contact plugging and copper is used for interconnection. Finally, alloying anneal is performed. We notice that the narrow width device trimmed down upon STI etching and low-thermal-budget activation process are the critical steps in fabrication of sub-20 nm transistor [67].
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Figure 2.1: Illustrations of planar MOSFET flow in National Nano Device Laboratories (NDL). The process flow consists of 150 steps for planar devices.
2.2 : Physical Modeling and Numerical Methods 21
2.2
Physical Modeling and Numerical Methods
The technology computer-aided design (TCAD) simulations, such as process and device simulations, are widely used for the analysis of semiconductor devices. The process sim-ulation can generate the device geometry and doping profile according to the parameters of the fabrication processes. The output of process simulation is then used in the device simulation to estimate device characteristics. The drift-diffusion (DD) and hydrodynamic (HD) models play a crucial role in the development of semiconductor device simulator in the macroscopic point of view. The DD model was derived from Maxwell’s equation as well as charges’ conservation law and has been successfully applied to study device trans-port behavior, in the past decades. It assumes local isothermal conditions and is still widely employed in semiconductor device design.
Classical drift-diffusion model consists of at least three coupled partial differential equa-tions (PDEs), such as electrostatic potential and electron-hole densities. When device chan-nel is specified, a set of the DD equations in semiconductor device simulation is solved:
φ = q εs(n − p + D), (2.1) 1 q ·Jn = R(n, p), (2.2) and 1 q ·Jp = −R(n, p), (2.3)
where φ is the electrostatic potential and its unit is volt. n and p are classical electron and hole concentrations (cm−3). q is the elementary charge and its unit is coulomb. The net doping concentration is D(x, y, z) = ND+(x, y, z)−NA−(x, y, z). R is the net recombination rate (cm−3s−1). The carrier’s currents densities are given by
Jn= −qμnn φ + qDn n, (2.4)
and
Jp = −qμpp φ − qDp p, (2.5)
where μnand μp are the carrier mobility (cm2/V − s). The diffusion coefficients, Dnand
Dp(cm2/s), satisfy the Einstein relation.
According to Mathiessen’s rule [29-31], the mobility models used in the device sim-ulation can be expressed as:
1 μ = D μsurf aps + D μsurf rs + 1 μbulk, (2.6)
where D= exp (x/lcrit), x is the distance from the interface and lcritis a fitting parameter.
The mobility consists of three parts: (1) the surface contribution due to acoustic phonon scattering, μsurf aps = BE +EC(N1/3(T/Ti/N0)τ
0)K, where Ni = NA+ ND, T0= 300 K,E is the
trans-verse electric field normal to the interface of semiconductor and insulator, B and C are parameters which based on physically derived quantities, N0 and τ are fitting parameters,
2.2 : Physical Modeling and Numerical Methods 23
T is lattice temperature, and K is the temperature dependence of the probability of sur-face phonon scattering; (2) the contribution attributed to sursur-face roughness scattering is
μsurf rs = ((E/Eδref)Ξ + Eη3)−1, whereΞ = A + α·(n+p)N
v ref
(Ni+N1)v , Eref = 1 V/cm is a reference
electric field to ensure a unitless numerator in μsurf rs, Nref = 1 cm−3 is a reference
dop-ing concentration to cancel the unit of the term raised to the power v in the denominator of Ξ, δ is a constant that depends on the details of the technology, such as oxide growth conditions, N1 = 1 cm−3, A, α, and η are fitting parameters; (3) and the bulk mobility is μbulk = μL(TT
0)
−ξ, where μLis the mobility due to bulk phonon scattering and ξ is a fitting
parameter.
The quantum mechanical effects should be considered in the device simulation when the dimensions of the devices shrunk into nanometer scale. Various theoretical approaches have been presented to study the quantum confinement effects, such as full quantum me-chanical model (e.g. nonequilibrium Green’s function) and quantum corrections to the clas-sical drift-diffusion (DD) or hydrodynamic (HD) transport models. A set of Schrodinger-Poisson (SP) equations have been applied to study the quantum confinement effect in the inversion layers as well as the quantum transport between source and drain, but it is a time consuming task in the TCAD application to realize device characterization. Therefore, various quantum correction models, density gradient (DG) [42-45], Hansch [68], modified local density approximation (MLDA) [69], effective potential (EP) [70-72], and unified
quantum correction Model [73], have been proposed for classical DD or HD transport mod-els. In this investigation, the density-gradient is coupled with the DD model and solved for the quantum mechanical effects. The density-gradient equation can be expressed as,
Jn= −qμnn φ + qDn n − qnμn γn, (2.7)
Jp = −qμpp φ − qDp p + qpμp γp, (2.8)
where γn and γp are the quantum potentials for electrons and holes: γn = 2bn2 √n √n
and γp = 2bp
2√p
√p bn; and bp are density-gradient coefficients for electrons and holes.
bn = 2/(12qm∗n) and bp = 2/(12qm∗p). m∗n and m∗p are effective masses for the
elec-trons and holes. is the Planck constant. bnand bp in Eqs. (2.7) and (2.8) are the density
gradient coefficient which determines the strength of the gradient effect in the electron and hole gas. The last term in the right hand side of Eqs. (2.7) and (2.8) are referred to as “quantum diffusion”, which makes the electron continuity equation having a fourth-order partial differential equation. Therefore, such an approach is highly sensitive to noise in the local carrier density, and the methodology is highly important in cases of strong quantiza-tion. To calculate the numerical solution of the multidimensional density-gradient model, firstly we decouple the coupled partial differential equations (PDEs); and approximate each decoupled PDE with the finite volume method over nonuniform mesh. The corresponding system of the nonlinear algebraic equations is then solved with the monotone iteration
2.2 : Physical Modeling and Numerical Methods 25
method. Iteration will be terminated and post-processes will be performed when the speci-fied stopping criteria for inner and outer iteration loops are satisspeci-fied, respectively.
2.3
Simulation Technique
Threshold voltage is one of the key device parameters in the characteristics of nanoscale metal-oxide-semiconductor field effect transistors. This section presents the characteriza-tion technique for intrinsic parameter fluctuacharacteriza-tions consisting of line edge roughness (LER), oxide thickness fluctuation (OTF), random-dopant-fluctuation (RDF), and an emerging fluctuation source: work-function fluctuation (WKF). The characterization approaches are examined with experiment data. Base upon the independent of random variables, the total threshold voltage fluctuation, σVth,totalis expressed as follows [74]:
σ2Vth,total ≈ σ2Vth,RDF + σ2Vth,LER+ σ2Vth,OT F + σ2Vth,W KF, (2.9)
where σVth,RDF, σVth,LER, σVth,OT F, and σVth,W KF are the threshold voltage fluctuations
caused by the random-dopant-fluctuation, line edge roughness, oxide thickness fluctuation, and the workfunction fluctuation, respectively. The statistical addition of individual fluc-tuation sources herein, as shown in Equation (2.9), simplifies the variability analysis of nano-devices and circuits, significantly [74]. In addition, the methodology of LER, OTF and WKF has been proposed and LER- ,OTF- and WKF-induced Vth fluctuations are
ex-amined in our previous work [74]. However, the result shows that the RDF dominates the Vthfluctuation in NMOSFETs, as disclosed in Fig. 2.2.
