Platform-based Design

Our behavior model is implemented according to the platform-based design methodology.

Platform-based design is a powerful concept for releasing the increased pressure on

time-to-market, design and manufacturing costs. The modern SoC design flow increases the

productivity of each engineer. Usually the engineers just change few functions in the former

design to create a new one. Most design effort is reused and shared in the following projects.

The engineers will reuse the components like the ARM processor, the memory, and some

peripheral modules. As shown in Figure 15, the AMBA interface and protocol enable the

designer to develop the SoC system by assembling essential IPs. The platform-based design

concept is adopted by our design methodology. In the following subsections, we will

introduce the features of AMBA, the interaction of hardware and software, and the memory

mapping concept for accessing declared registers.

Figure 15 The Platform-based Design.

2.4.1 AMBA

The AMBA protocol is an open standard, on-chip bus specification that details a strategy

for the interconnection and management of functional blocks that makes up a System-on-Chip

(SoC). The AMBA protocol enhances a reusable design methodology by defining a common

backbone for SoC modules.

There are three different buses in the AMBA specification: AHB, ASB and APB. AHB

stands for Advanced High-performance Bus. AHB is a new generation of AMBA bus which

is intended to address the requirements of high-performance synthesizable designs. It is a

high-performance system bus that supports multiple bus masters and provides high-bandwidth

operation. ASB stands for Advanced System Bus. This is an older version has been replaced

by AHB. APB stands for Advanced Peripheral Bus. It is a simple lower performance and low

power bus used for low speed peripherals. The APB is optimized for minimal power

consumption and reduced interface complexity. The macrocells designed to interface with

AMBA can be seen as building blocks which can be reused in future designs and mixed and

matched in different combinations to realize complex systems in a shorter period of time. The

AMBA architecture is shown as Figure 16.[22]

Figure 16 The AMBA Architecture.

2.4.2 The HW/SW Interaction

Hardware/software interaction plays an important role in co-design of the embedded system.

It connects the software part and the hardware part in a system. There are two main

approaches for hardware/software interaction: Polling and Interrupt.

Polling the device usually means reading its status register so often until the device's status

changes to indicate that it has completed the request. Interrupt is a signal from a device

attached to a processor or from a program within the processor that causes the main program

that operates the system to stop and figure out what to do next. An interrupt can be generated

by one of two sources: software interrupt and hardware interrupt. The interrupt signals

initiated by programs are called software interrupt. An interrupt also can be generated by an

external device. These are called hardware interrupts. When a program receives an interrupt

signal, it takes a specified action. Interrupt signals can cause a program to suspend itself

temporarily to service the interrupt.

Figure 17 Interaction between Hardware and Software.

The behavior of the interrupt and the actual layout is shown in the Figure 17. The

interaction between our hardware module and ARM processor is hardware interrupt. This is a

more effective approach than polling. After the unprocessed data is moved into the input

buffer, the CRC module is enabled by software with the CRC_enable signal. Then the CRC

hardware module will start to process the data and return the CRC result. After the CRC

hardware finishing it job, the hardware module will inform the ARM core to fetch the CRC

result from the output buffer by using the interrupt signal. In the embedded system design, the

interrupt signal is connected to an interrupt control IC. Then the IC will inform the CUP that a

hardware module and jumps to the address of the service routine and deal with the process.

2.4.3 Hardware Registers

In embedded system design, hardware registers compose a storage area for control signals

and data.Hardware registers are contained within a certain peripheral unit. Usually we divide

the hardware registers into three types -- control registers, status registers, and data buffers. A

status register is a collection of bits for a processor that indicates the status of various specific

operations. When a status register is read, it will report the state of the peripheral device.

When a control register is written, it will change the state of the peripheral device. The data

buffers usually storage the raw data for processing and the output data for accessing. Registers

is costly, so the registers will not be used unlimited.

2.4.4 Memory Mapping

Memory mapping is a process that a digital hardware is connected to a processor’s address

bus and data bus. In this way, the component can be accessed exactly as if it were a memory

cell. To a processor, everything is memory. The memory mapping is to define the address of

the I/O registers in the memory table so the embedded processor can exactly access the

specific registers. Memory-mapped I/O (MMIO) and port-mapped I/O (PMIO) are two

complementary methods of performing input/output between the CPU and I/O devices in an

embedded system. In our implementation, we use the memory-mapped I/O methodology.

Memory-mapped I/O uses the same bus to address both memory and I/O devices, and the

same CPU instructions are used to access both memory and I/O devices. The I/O devices

monitor the CPU's address bus and map the address to their hardware registers. The Figure 18

shows the memory map in our implementation.

Figure 18 Memory Map.