Chapter 3 Case Study:A Behavior Model Design 32
3.3 Simulation Result and Application
3.3.2 Simulation Model and Simulation Result
In this subsection, we use three simulation models to compare the simulation performance.
We want to calculate the clock cycle of the software function and hardware module based on
different packet sizes. There are three simulation models - the model with no CRC function,
the model with software CRC function, and the model with hardware CRC module. The
Figure 30 shows the clock cycles of three simulation models in three different packet sizes.
Figure 30 The Clock Cycles of Three Simulation Models in Different Packet Sizes
The Figure 31 shows the comparison of simulation result. We obtain the clock cycle for
software function and hardware module in different transmitted packet sizes. The simulation
result explains the improvement of the overall system performance in heavy traffic data. The
simulation shows that there are 1.6% and 11.7% improvements by setting the packet size in
100bits and 1000bits respectively.
The processed data is transferred between software and hardware through the AMBA bus.
The bus transaction is an overhead for system simulation. For the small packet size, the
simulation result of hardware version is worst because the extra overhead in bus transaction is
larger than the processing gain of hardware component. For the large packet size, the
transaction is smaller than the processing gain of hardware component. The packet size in
100bits is an approximate threshold in our behavior model for using the CRC accelerator.
3.4 Summary
In this chapter, we illustrate our implementation process and demonstrate our simulation
results. In the section 3.1, we explore our design flow for our behavior model and finish the
system level simulation. In the section 3.2, we explore our design flow for hardware modeling
and finish the heterogeneous simulation. In the section 3.3, we have a comparison between the
pure software version and the other version with hardware accelerator model. The design
methodology and platform can be used to verify different communication scenarios. By using
this platform, a behavior model with the error detection and error correction function is
demonstrated in this chapter. The simulation result shows our hardware accelerator can
improve the simulation performance for this platform.
Chapter 4
Conclusions and Future Work
This thesis presents an implementation of our behavior model on an electronic system level
simulation platform to enable the data transmission. A virtual socket concept is proposed to
deal with the packet transmission. We implement our behavior model at the electronic system
level simulation platform, which provides three purposes: system level design, system level
verification, and hardware/software co-design. The design concepts and design methodology
are exploded. This behavior model demonstrates the packet transmission between the
transmitter and the receiver and guarantees the data integrity. The behavior model also can be
used to verify the different communication scenarios.
The heterogeneous simulation improves the efficiency of the system simulation. The
hardware module is become a library that can be reuse for the other designs. Finally, we
demonstrate the heterogeneous simulation at electronic system level and improve the efficient
for the system simulation.
For the further improvement of our behavior model, the hardware module can be realized in
the register transfer level and obtain the time, area, and power information.
Bibliography
[1] IEEE 802.16.IEEE Standard for Local and Metropolitan Area Networks-Part 16.Air Interface for Fixed Broadband Wireless Access Systems-2004.
[2] A. Ghosh et al., “Broadband Wireless Access with WiMAX/802.16:Current Performance Benchmarks and Future Potential”, IEEE Communications Magazine, vol.43, no.2, pp.
129-136, 2005.
[3] Thorsten Grotker, Stan Liao, Grant Martin and Stuart Swan, System Design with SystemC, Kluwer Academic Publisher, 2002.
[4] M. Keating and P. Bricaudr, Reuse Methodology Manual for System-On-A-Chip Designs, Kluwer Academic Publishers, 2002.
[5] Steve Furber, ARM System-on-Chip Architecture second edition, ADDISON WESLEY, 2000.
[6] Takayuki Tachikawa and Makoto Takizawa, “ARQ Protocols for Bi-directional Data Transmission”, International Conference on Information Networking (ICOIN-12), Tokyo, Japan, pp.468-473, 1998.
[7] Tim Hopes, “Hardware/Software Co-verification, an IP Vendors Viewpoint”, Proceedings of the International Conference on Computer Design (ICCD), Austin, TX, USA, pp.242-246, 1998.
[8] Jing-Yang Chou, “Special Topics in Computer Aided Design”.
[9] Theo A.C.M Claasen, “An Industry Perspective on Current and Future State of the Art in System-on-Chip (SoC) Technology ” Proceedings of the IEEE, Vol. 94, No. 6, pp.
1121-1137, 2006.
[10] ARM Limited, “The Software Development Toolkit”, version 2.50, pp. 370, 1998.
[11] Ray Turner, “System Level Verification – a Comparison of Approaches”, Proceedings of the 10th IEEE International Workshop on Rapid System Prototyping, Clearwater, FL, USA, pp154-159, 1999.
[12] Joanne DeGroat, Arun Raman, Bakr Younis, “A Design Project for System Design with SystemC”, Proceedings of the IEEE International Conference on Microelectronic Systems Education, Anaheim, CA, USA, pp108-109, 2003.
[13] Liao, S. Y., “Towards a New Standard for System-Level Design”, Proceedings of the Eighth International Workshop on Hardware/Software Co-design, San Diego, 2000.
[14] Open SystemC Initiative. See http://www.systemc.org
[15] J. Bhasker, A SystemC Primer, Star Galaxy Publishing, 2002.
[16] H. Holisaz, S. Shamshiri et al, “Hardware Accelerator IP-Core for Wireless 802.16 MAC”, IFIP International Conference on Wireless and Optical Communication Networks, Bangalore, India, 2006.
[17] Liangshan Ma and Dongyan Jia, “The Competition and Cooperation of WiMAX, WLAN and 3G”, 2nd Asia Pacific Conference on Mobile technology application and systems, Guangzhou, China, 2005.
[18] Nak Woon Sung, “HW/SW Codesigned Implementation of IEEE 802.16 TDMA MAC for the Subscriber Station”, Proceedings of the Fourth Annual ACIS International Conference on Computer and International Science, Jeju Island, South Korea, pp436-440, 2005.
[19] Jorg Henkel, “Closing the SoC Design Gap”, Computer, Volume 36, Issue 9, pp119-121, 2003.
[20] ARM Limited, “RealView SoC Designer SystemC-TML Import”, version 3.06, pp. 22, 2006.
[21] Collett International Research:2000, 2002 Functional Verification Studies.
[22] ARM Limited, “AMBA Specification (Rev 2.0)”, pp. 1-4, 1999.
[23] Gordon Moore, “Cramming more components onto integrated circuits”, Electron. Mag, vol.38, no.8, pp.114-117, 1965.
[24] Thorsten Grotler, Stan Liao, Grant Martin, Stuart Swan, System Design with SystemC, Kluwer Academic Publishers, 2002.
[25] International Technology Roadmap for Semiconductors, 2006 Update, Semiconductor Industry Association. Available from http://www.itrs.net/