Gox Channel
(c).
Fig 4-1. (a) Schematic diagram of M10 polysilicon TFT.
(b) Cross-section view of Fig. 1a AA’ direction.
x
z
A
B
B’
A’
x
z
(a). y
(b).
BOX 4000A
Poly Gate
Source N+ N+ Drain
Table 4-1 Summary all devices dimension. All devices are top single-gate structure.
Device name Gate length L
Channel number
Each channel width
Effective channel width W
L1M10 1um 10 67nm 0.67um
L1S1 1um 1 1um 1um
L2M10 2um 10 67nm 0.67um
L2S1 2um 1 1um 1um
L5M10 5um 10 67nm 0.67um
L5M5 5um 5 0.18um 0.9um
L5M2 5um 2 0.5um 1um
L5S1 5um 1 1um 1um
L10M10 10um 10 67nm 0.67um
L10S1 10um 1 1um 1um
Fig. 4-2 (a) Scanning electron microscopy photography of active pattern with the source, the drain and multiple nano-wire channels of M10 TFT. (b) Magnified area of multiple nano-wire channels. The each nano-wire width is 67 nm.
(
So Dr
(
67
Gate voltage (V)
Field effect mobility ( cm2 /Vs)
0
Fig. 4-3b Device Id-Vd characteristics of L5M10 (L/W = 5um/67nm×10) polysilicon TFT
Fig. 4-3a Device Id-Vg characteristics of L5M10 (L/W = 5um/67nm×10) polysilicon TFT.
.
Field effect mobility ( cm2 /Vs)
0
Fig. 4-4b Device Id-Vd.characteristics of L5M5 (L/W = 5um/0.18um×5) polysilicon TFT.
Fig. 4-4a Device Id-Vg characteristics of L5M5 (L/W = 5um/0.18um×5) polysilicon TFT.
Gate voltage (V)
Field effect mobility ( cm2 /Vs)
0
Gate voltage (V)
Field effect mobility ( cm2 /Vs) 0
Fig. 4-6a Device Id-Vg characteristics of L5S1 (L/W = 5um/1um) polysilicon TFT.
Fig. 4-6b Device Id-Vd characteristics of L5S1 (L/W = 5um/1um) polysilicon TFT.
Table 4-2 Device a parameters of M10, M5, M2 and S1. All parameters were extracted at Vd = 5V, except for the field-effect mobility which were extracted at Vd = 0.1V.
Device name Mobility (cm2/VS)
Vth
(V)
SS (V/dec.)
Ion / Ioff
L5M10 42.29 4.05 0.59 2.93 × 106
L5M5 30.62 4.56 0.66 1.87 × 106
L5M2 21.39 4.70 0.78 1.15 × 106
L5S1 18.11 4.79 0.80 2.93 × 106
Fig. 4-7 Field effect mobility (µFE) versus different channel number polysilicon TFTs, with the same gate length L = 5um.
Fig. 4-8 Drain current maximum ON/OFF ratio (R) versus different channel number polysilicon TFTs, with the same gate length L = 5um.
Channel number
M10 M5
M2 S1
Field effect mobility ( cm2 /Vs)
15
Fig. 4-9 Threshold voltage (Vth) versus different channel number polysilicon TFTs, with the same gate length L = 5um.
Fig. 4-10 Subthreshold slope (SS) versus different channel number polysilicon TFTs, with the same gate length L = 5um.
Fig. 4-11a Schematic plot of PDM M10 TFTs polysilicon grain lateral growth.
Drain Source
MILC window
Gate
MILC window
Drain Source
Gate
Fig. 4-11b Schematic plot of PDM S1 TFTs polysilicon grain growth.
Gate voltage (V)
Field effect mobility ( cm2 /Vs)
0
Fig. 4-12a Device Id-Vg characteristics of L10M10 (L/W = 10um/0.67um) polysilicon TFT.
Fig. 4-12b Device Id-Vd characteristics of L10M10 (L/W = 10um/0.67um) polysilicon TFT.
Gate voltage (V)
Field effect mobility ( cm2 /Vs)
0
Fig. 4-13a Device Id-Vg characteristics of L10S1 (L/W = 10um/1um) polysilicon TFT.
Fig. 4-13b Device Id-Vd characteristics of L10S1 (L/W = 10um/1um) polysilicon TFT.
L/W=2um/67nm*10
Gate voltage (V)
-4 -2 0 2 4 6 8 10
Drain current (A)
10-14
Field effect mobility (cm2 /Vs)
0
Fig. 4-14a Device Id-Vg characteristics of L2M10 (L/W = 2um/0.67um) polysilicon TFT.
Fig. 4-14b Device Id-Vd characteristics of L2S1 (L/W = 2um/0.67um) polysilicon TFT.
L/W=2um/1um
Field effect mobility (cm2 /Vs)
0
Fig. 4-15a Device Id-Vg characteristics of L1S1 (L/W = 2um/1um) polysilicon TFT.
Fig. 4-15b Device Id-Vd characteristics of L1S1 (L/W = 2um/1um) polysilicon TFT.
Gate voltage (V)
Field effect mobility ( cm2 /Vs)
0
Fig. 4-16a Device Id-Vg characteristics of L1M10 (L/W = 1um/0.67um) polysilicon TFT.
Fig. 4-16b Device Id-Vd characteristics of L1M10 (L/W = 1um/0.67um) polysilicon TFT.
Gate voltage (V)
Field effect mobility ( cm2 /Vs)
0
Fig. 4-17a Device Id-Vg characteristics of L1S1 (L/W = 1um/1um) polysilicon TFT.
Fig. 4-17b Device Id-Vd characteristics of L1S1 (L/W = 2um/1um) polysilicon TFT.
Table 4-3 Device a parameters of L1M10, L2M10, L5M10 and L10M10. All parameters were extracted at Vd = 5V, except for the field-effect mobilities which were extracted at Vd = 0.1V.
Device name Mobility (cm2/VS)
Vth
(V)
SS (V/dec.)
Ion / Ioff
L1M10 72.93 1.87 0.60 4.58 × 105
L2M10 64.71 3.16 0.53 4.77 × 106
L5M10 42.29 4.05 0.59 2.93 × 106
L10M10 48.71 3.44 0.55 1.30 × 106
M10
W=67nm*10
Channel length
0 1 2 3 4 5 6 7 8 9 10 11
Field effect mobility ( cm2 /Vs)
30
Fig. 4-18 Field effect mobility (µFE) versus different channel length polysilicon TFTs.
The dots value present average value and error bars present standard deviation.
M10
Fig. 4-19 Drain current maximum ON/OFF ratio (R) versus different channel number polysilicon TFTs.
M10
W=67nm*10
Channel length (um)
0 1 2 3 4 5 6 7 8 9 10 11
Threshold voltage (V)
0 1 2 3 4 5
Fig. 4-20 Threshold voltage (Vth) versus different channel number polysilicon TFTs.
M10
W=67nm*10
Channel length (um)
0 1 2 3 4 5 6 7 8 9 10 11
Subthreshold swing (V/dec)
0.50 0.55 0.60 0.65 0.70
Fig. 4-21 Subthreshold slope (SS) versus different channel number polysilicon TFTs.
Source
Gate
Drain
MILC window
Drain Source
MILC window
Gate
Fig. 4-22a Schematic plot of PDM M10 TFTs polysilicon grain lateral growth.
Fig. 4-22b Schematic plot of PDM M10 TFTs polysilicon grain lateral growth.
Chapter 5 Conclusion
A novel pattern-depended metal induced lateral crystallization thin film transistors (PDM TFT) has been proposed to fabricate and characterization. A serious of multi-channel structure with different number and width have been combined into MILC process to enhance the mobility and improve gate controllability. Experiment results show that the field effect mobility is highly depended on multi-channel width.
For the same gate length L=5um, the field effect mobility increasing with channel number from L5S1, L5M2, L5M5 to L5M10, resulting its polysilicon grain lateral size enhanced by channel width limitation effect. In addition, experiment results also show that at the same M10 multi-channel structure, the field effect mobility increasing with gate length decreasing from L = 10 um, L = 5 um, L = 2 um to L = 1 um, resulting its polysilicon grain boundary defects lowering. Moreover, in short channel effect study, comparing the L1S1 to L1M10 devices, the L1S1 shows punch-through phenomena. It ca be explain that the L1M10 TFT has the better gate controllability due to its nano-wires structure behavior than L1S1 TFT. The lateral electrical field of M10 TFT can be effectively reduced by additional two side-gates control. The PDM TFTs process is compatible with CMOS technology, and involves
no any extra mask process. Such PDM TFTs are thus highly promising for use in future high-performance polysilicon TFT applications, especially in AMLCD and 3D MOSFET stacked circuits.
References
Chapter 1
[1.1] H. Oshima and S. Morozumi, “Future trends for TFT integrated circuits on glass substrates,” IEDM Tech. Dig., 157, 1989.
[1.2] M. Stewart, R. S. Howell, L. Pires, and M. K. Hatalis, “Polysilicon TFT technology for active matrix OLED displays ,” IEEE Trans. Electron Devices, vol. 48, pp. 845-851, 2001.
[1.3] H. Kuriyama et al., “An asymmetric memory cell using a C-TFT for ULSI SRAM,” Symp. On VLSI Tech., p.38, 1992.
[1.4] T. Yamanaka, T. Hashimoto, N. Hasegawa, T. Tanala, N. Hashimoto, A.
Shimizu, N. Ohki, K. Ishibashi, K. Sasaki, T. Nishida, T. Mine, E. Takeda, and T.
Nagano, “Advanced TFT SRAM cell technology using a phase-shift lithography,” IEEE Trans. Electron Devices, Vol. 42, pp.1305-1313,1995.
[1.5] K. Yoshizaki, H. Takaashi, Y. Kamigaki, T.asui, K. Komori, and H. Katto, ISSCC Digest of Tech., p.166, 1985
[1.6] N. D.Young, G. Harkin, R. M. Bunn, D. J. McCulloch, and I. D. French , “The fabrication and characterization of EEPROM arrays on glass using a low-temperature polysilicon TFT process,” IEEE Trans. Electron Devices, Vol.
43, pp. 1930-1936, 1996.
[1.7] T. Kaneko, U. Hosokawa, N. Tadauchi, Y. Kita, and H. Andoh, “400 dpi integrated contact type linear image sensors with polysilicon TFT's analog readout circuits and dynamic shift registers,” IEEE Trans. Electron Devices, Vol.
38, pp. 1086-1093, 1991.
[1.8] U. Hayashi, H. Hayashi, M. Negishi, T. Matsushita, Proc. of IEEE Solid-State Circuits Conference (ISSCC), p. 266 , 1998.
[1.9] N.Yamauchi, U. Inava, and M. Okamura, “An integrated photodetector- amplifier using a-Si p-i-n photodiodes and polysilicon thin-film transistors,”
IEEE Photonic Tech. Lett, Vol. 5, pp. 319-321, 1993.
[1.10] M. G. Clark, IEE Proc. Circuits Devices Syst, Vol. 141, 133 , 1994.
[1.11] Noriyoshi Yamauchi, Jean-Jacques J. Hajjar and Rafael Reif, “Polysilicon Thin-Film Transistors with Channel Length and Width Comparable to or Smaller than the Grain Size of the Thin Film,” IEEE Trans. Electron Devices, Vol. 38, pp 55-60, 1991.
[1.12] Singh Jagar, Mansun Chan, M. C. Poon, Hongmei Wang, Ming Qin, Ping K.
Ko, Yangyuan Wang, “Single Grain Thin-Film-Transistor (TFT) with SOI CMOS Performance Formed by Metal-Induced-Lateral-Crystallization,” IEDM Tech. Dig., pp. 293-296, 1999.
[1.13] K. Nakazawa, “Recrystallization of amorphous silicon films deposited by low-pressure chemical vapor deposition from Si2H6 gas,” J. Appl. Phys, Vol. 69, pp. 1703-1706, 1991.
[1.14] T. J. King and K. C. Saraswat, “Low-temperature fabrication of polysilicon thin-film transistors,” IEEE Electron Device Lett, Vol. 13, pp. 309-311, 1992.
[1.15] H. Kuriyama, S. Kiyama, S. Noguchi, T. Kuahara, S. Ishida, T. Nohda, K.
Sano, H. Iwata, S. Tsuda, and S. Nakano, “High mobility polysilicon TFT by a new excimer laser annealing method for large area electronics,” IEDM Tech. Dig, Vol. 91, pp. 563, 1991.
[1.16] S. W. Lee and S. K. Joo, “Low temperature polysilicon thin-film transistor fabricated by metal-induced lateral crystallization,” IEEE Electron Device
[1.17] H. J. Kim and J. S. Im, “New excimer-laser-crystallization method for
producing large-grained and grain boundary-location-controlled Si films for thin film transistors,” Appl. Phys. Lett., vol. 68, p. 1513, 1996.
[1.18] M. K. Hatalis and D. W. Greve, “Large grain polycrystalline silicon by low-temperature annealing of low-pressure chemical vapor deposited amorphous silicon films,” J. Appl. Phys., vol. 63, p. 2260, 1988.
Chapter 2
[2.1] J. Levinson, F. R. Shepherd, P. J. Scanlon, W. D. Westwood, G. Este, and M.
Rider, “Conductivity behavior in polycrystalline semiconductor thin film transistors,” J. Appl. Phys. Vol. 53, pp.1193-1202, 1982.
[2.2] P. Migliorato, C. Reita, G. Tallatida, M. Quinn and G. Fortunato, “Anomalous off-current mechanisms in n-channel polysilicon thin film transistors,”
Solid-State-Electronics, Vol.38, pp.2075-2079, 1995.
[2.3] M. Hack, I-W. Wu, T. H. King and A. G. Lewis, “Analysis of Leakage Currents in Polysiliconlicon Thin Film Transistors,” IEDM Tech. Dig., vol. 93, pp.
385-387, 1993.
[2.4] “Polycrystalline silicon for integrated circuits and displays,” second edition, written by Ted Kamins, pp.200-210.
[2.5] K. R. Olasupo and M. K. Hatalis, “Leakage Current Mechanism in Sub-Micron Polysilicon Thin-Film Transistors,” IEEE Trans. Electron Devices, ” Vol. 43, pp.1218, 1996.
[2.6] “Semiconductor devices physics and technology,” second edition, written by S.M Sze, pp. 199-213
crystallization of nickel-implanted amorphous silicon thin film,” J. Appl. Phys., vol.73, pp.8279-8289,1993.
[2.8] C. F. Cheng, Vincent M. C. Poon, C. W. Kok, and Mansun Chan, “Modeling of Grain Growth Mechanism by Nickel Silicide Reactive Grain Boundary Effect in Metal-Induced-Lateral-Crystallization,” IEEE Trans. Electron Devices, Vol.50, pp.1467-1474, 2003.
Chapter 4
[4.1] K. Suzuki, T. Tanaka, Y. Tosaka, H. Horie, and Y. Arimoto, “Scaling theory for double-gate SOI MOSFET’s,” IEEE Trans. Electron Devices, Vol. 40, pp.2326-2329, 1993.
[4.2] Shoichi Miyamoto, Shigeto Maegawa, Shigenobu Maeda, Takashi Ipposhi, Hirotada Kuriyama, Tadashi Nishimura, and Natsuro Tsubouchi, “Effect of LDD Structure and Channel Polysilicon Thinning on a Gate-All-Around TFT (GAT) for SRAM’s,” IEEE Trans. Electron Devices, Vol.46, pp.1693-1698, 1999.
[4.3] B. Doyle, B. Boyanov, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, R. Rios and R. Chau, “Tri-Gate Fully-Depleted CMOS Transistors:
Fabrication, Design and Layout,” Symp. VLSI Technology Dig. Tech. Paper, 2003.