Chapter 2 Background
2.3 Power Switch
Power switch has first adopted by MTCMOS (Multi-threshold CMOS) technique [18], [19]. MTCMOS is very effective at reducing leakage current in the idle mode.
MTCMOS use two types of CMOS: high-VT and low-VT transistor. High-VT devices can be used to reduce leakage currents while low-VT devices can be used whenever high performance is required. MTCMOS technique involves using high-VT transistors to gate power supplies of a low-VT logic block as shown in Figure 2.4. When the high-VT transistors are turned on, the low-VT logic is connected to virtual ground and power, the switching is performed through fast devices. When the circuit enters the idle mode, the high-VT gating transistors are turned off, resulting in a very low leakage current from VCC to ground [20]. MTCMOS circuit can achieve several orders of magnitude reduction in leakage currents through two effects. First, the total effective transistor width of the original CMOS circuit is reduced to the width of the single “off” transistor (provided it is smaller than the original width), and second, the increased threshold voltage results in an exponential reduction in leakage currents [18].
Low-VT
Figure 2.4 MTCMOS circuit structure.
Power switch (or Sleep transistor) connecting power lines to virtual power lines can be accurately modeled as linear resistors. For a turned-on NMOS transistor sized large enough to ensure performance for requirement, the virtual ground voltage will be close to actual ground. Therefore, the power switch sizing is a key design parameter that affects the performance of circuit. If sized too large, the silicon area would be wasted and switching energy overhead between idle and active modes would be increased. On the other head, if sized too small, then the circuit would be too slow because of increased resistance to ground. Therefore, overdriving and under-driving are used to apply on the power switch [20], [21. Overdriving is used in active mode in order to reduce the frequency penalty of the power switch. Gate under-driving is used in idle mode to further increase the leakage savings by reducing the leakage of the power switch. Besides incurring a little performance penalty, power switch is still a very attractive technique for leakage suppression.
In order to insert power switch into Cell-Based design without modifying core design, the appropriate arrangement for power switch is important. Figure 2.5 show the power connection between power grid and standard cell. In our implementation, the power switch is inserted below the power delivery grid between metal-1 and metal-2 [Figure 2.6]. The power switches are distributed throughout the power ring in two columns in order to avoid any current crowding issues. The power switches are designed as large as possible to avoid the sizing impact on performance.
Metal 2 VSS
Figure 2.5 Power connection in general physical design flow.
Cell
Virtual
Metal 2 Vss
Metal 1
VSS
Virtual VSS
Power Switch
VSS Cell
Figure 2.6 Power connection for power switch.
Chapter 3
Implementation
In this chapter, each physical design flow is presented. First, general cell-based physical design flow is introduced in Section 3.1. It is divided into seven design phases and purpose of each phase is explained clearly. The physical design flow for Voltage Separation is presented in Section 3.2. In order to avoid substrate noise coupling, deep n-well (DNW) pattern is added for digital circuit core. The body bias for cell-based design flow is shown in Section 3.3. For dual-supply cell, layout of dual-supply cell and connection between port and power net are presented. For general standard cell, the modification of well and contact are introduced. Finally, the power switch implementation is shown in Section 3.4.
3.1 General Automatic Physical Design Flow
The physical design is translating gate-level netlist into a physical representation.
Because of the major goal of physical design is standard cells’ placement and routing.
The physical design is also called to Auto Place and Routing (APR). The physical design flow includes power/ground line design, partitioning, floorplanning, placement, routing and clock tree synthesis. A general automatic physical design flow is shown in the figure 3.1. From the gate-level netlist to final GDSII file, the entire physical design flow is divided into seven phases. The details of each phase will be described below.
First phase in physical design flow is design setup. In this design phase such as technology file, reference libraries, gate-level netlist and power connection are specified. The technology file contains layer definitions and process design rules. It must be specified before creating a design library. The reference libraries are including standard cell library, memory library and IO library. The gate-level netlist is an HDL code after logic synthesis. The EDA tool can load appropriate standard cells from gate-level netlist. Power and Ground port of each standard cell must be
associated with corresponding global Power and Ground nets, respectively.
Second phase is floorplanning. In this design phase the core area aspect and Power/Ground Grid will be determined. The core area aspect including standard cell placement direction will be defined by some control parameters. The routing channel and core utilization also be confirm in this design phase respectively. The size of routing channel and core utilization affect the total chip area and probability of routing success. The core power ring and power straps are created to form Power/Ground Grid. The well-defined Power/Ground Grid leads to power arrangement balance and current density. The third design phase is timing setup. In this design phase EDA tool optimize the logic gates, places and routes them to fit in the smallest possible area while meeting all timing constraints by relying on static timing analysis and parasitic extraction estimation and calculation.
The forth phase is placement. The placement of standard cells is determined in this design phase. Unsuitable placement of standard cells results in congestion problem which is a limit to the number of nets through the small area. During placement, the congestion problem is fixed by spreading cells apart and wire detour without hurting circuit performance. After placement, the port of each standards cell will connect to Power/Ground Grid. The fifth design phase is clock tree synthesis (CTS). The multi-level buffer trees according to clock specification are added into your target design. The clock skew will be decrease and fit the time specification of your design.
The side effort of clock tree synthesis is re-move of some cells and increase of congestion. The EDA tool will optimize the placement of standard cells and fix the congestion problem.
The sixth design phase is routing. The goal of routing is drawing Design-Rule- Check-correct (DRC) metal shapes for all interconnect wire while maintaining circuit timing, clock skew, signal net transition and capacitance limits. But this build-in DRC is used for simple verification only, it have to use other tools for sing-off. When routing phase, each metal layer has its own, possibly unique, grid and preferred routing direction. Therefore, every metal line is assign to respective track and is attempting to make long, straight routes. Like placement phase, the congestion problem is expected and resolving with detour routing.
The seventh, is also last, design phase is Design for Manufacture (DFM). DFM is used to improve several manufacturability issues and increase manufacturing yield.
Such as antenna fixing, metal slotting and metal filler are used to control metal density and prevent from metal liftoff and erosion. The final validation is detailed DRC and Layout Versus Schematic (LVS) verification. The DRC checks physical
formation matching fabrication design constrains. The LVS checks the connectivity of physical layout to its related schematic circuit netlist. Finally, the GDS II file which is free of error can be fabricated in foundry for manufacture.
Figure 3.1 General automatic physical design flow.
3.2 Physical Design Flow for Voltage Separation
This section presents a design flow for the Voltage Separation. The entire design flow for Voltage Separation is shown in the figure 3.2. Compare with general physical design flow, the difference parts of design phase are design setup, floorplanning and design for manufacturing. The detailed illustrations are shown in remaining of this section.
In the floorplanning design phase for Voltage Separation, the extra three steps are added to the design phase. There respectively are
z Partition into groups z Floorplanning of groups z Create Separated Power Rings
First step is Partition into Groups. According to the demand of system, designer can partition design circuit into several Groups which are supplied to difference voltage level, respectively. Therefore, the power consumption of system can be decrease by providing lowest voltage level for each Group. But at the same time, the core area will be increase result of individual voltage grid and dead space from floorplanning of Groups. In order to increase the design flexibility and decrease the area penalty caused by voltage separation, each Group can adjust island’s aspect and core utilization by some design parameters tuning.
After step of Partition into Groups, the Floorplanning of Groups has to implement.
According to the pre-plan of power grid, designer can place Group to any region in the core individually. In order to reduce power consumption of system, creating Separated Power Rings surrounding each island respectively is needed. To prevent from fault connection of power rings, the declaration of power rings connection has to specify clearly.
In this part, the deep N-well (DNW) can be respectively added to each Group for decreasing substrate noise coupling. The DNW attenuating noise to common substrate is shown in figure 3.3. The DNW isolates the P-well, which is the noise source and P-substrate with each other. The device of characteristic is not affected by DNW impact because DNW implant peak is deep enough, about 2 um. 70dB substrate noise isolation between integrated subsystems is achieved from a circuit level methods [22], substrate noise trapping, descript in figure 3.4. The DNW entirely covering the digital circuit section attenuates the substrate noise passing through the DNW’s walls towards the common substrate (substrate noise trapping). Once into the common substrate, the attenuated substrate noise will proceed towards the DNW protecting the
RF circuit section, making that whole DNW change its electric potential uniformly.
Therefore, DNW is needed if there is some sensitivity circuit block on the same die and remarkable noise immunity is achievable. Therefore, if there are two or more than two groups in the design and body bias techniques is applied on NMOS, the coupling noise from two p-well block can be diminished by Double Deep N-well architecture.
Figure 3.2 Physical design flow for voltage separation.
Deep N-well
P-well is isolated by Deep n-well
Deep N-well
Disturb
Receiver
Figure 3.3 Deep n-well isolation structure.
P-substrate
Figure 3.4 Double deep N-well isolation structure.
3.3 Body Bias for Cell-Based Design Flow
Two methods of realizing body bias with Cell-Based design flow are introduced in this section. Two methods are individually based on the dual-supply standard cell and modification of well and contact. In Section 3.3.1, the features and extra design phases associated with dual-supply standard cell are introduced. In Section 3.3.2, how to add extra well and strap and remove contact of standard cell are specified.
3.3.1 Body Bias with Dual-Supply Standard Cell
The schematic diagrams of conventional and dual-supply standard cell are shown in figure 3.5. The Body and Source terminals of MOSFET in conventional standard cell are tied together. So the voltage level of Body and Source terminal of MOSFET in conventional standard cell are the same. But for body bias design, the voltage level of Body terminal change dynamically according to system requirement. Therefore, separating Body terminal from Source terminal for body bias design is necessary. As shown in figure 3.5(b), dual-supply standard cell has additional power and ground ports, VDDB and VSSB. Therefore, voltage level of Body and Source terminal is assigned to differential value respectively.
Figure 3.5 Schematic diagrams (a) Conventional cell.
(b) Dual-supply cell.
The layout of conventional and dual-supply standard cell is shown in figure 3.6.
The remarkable variation of those two standard cells is metal lines isolation between Body and Source terminal. Besides isolated metal lines, the remaining part of dual-supply standard cell is almost the same with conventional ones. However,
because of the isolated metal lines have to obey the design rule of layout, the extra gap existed in the standard cell results the increase of cell area. Therefore, the design circuit with dual-supply standard cell has larger area compared with conventional standard cell. The detailed analysis of area penalty will be discussed in Section 4.3.
Figure 3.6 Layout diagrams. (a) General cell.
(b) Dual-supply cell.
After simply introduces the features of dual-supply standard cell, the entirely physical design flow, shown in figure 3.7, is specified below. In order to fit dual-supply standard cell for conventional physical design flow, there are three additional steps are added into the conventional physical design flow. There are:
z Global Net Setting z Create Power Rings z Connect Port to P/G
Compare with conventional standard cell, dual-supply ones has extra VDDB and VSSB ports. During expansion the netlist into the design library in Design Setup phase, power and ground ports in standard cells must be associated with corresponding global power and ground net. Using the Global Net Setting, It can specify the global net connections to nets and ports in the standard cells. Because of VDDB (VSSB) is fed another voltage source which differs from VDD (VSS), creating individual power and ground ring in Floorplanning phase is necessary. In the fourth design phase of Placement, standard cells are put into core and connect power and ground ports to corresponding power and ground nets. So power connection between the created power rings and corresponding ports in standard cell is achieving in this step. The remaining design phase is the same with conventional physical ones.
Design For Manufacturing Routing
Clock Tree Synthesis Placement Timing Setup Floorplanning
Design Setup
Gate-Level Netlist
GDSII Layout
Global Net Setting
Create Power Rings
Connect Ports to P/G
Figure 3.7 Physical design flow with dual-supply standard cell.
3.3.2 Body Bias with General Standard Cell
In the earlier section we introduce how to implement body bias with dual-supply standard cells. But in the general situation, the conventional standard cell is only available in Cell-Based design flow. Therefore, how to add body bias into your design circuit with conventional standard cell is becoming an important topic. In Section 3.3.2, realizing the body bias into design circuit with extra well pattern addition and modification of contact is introduced. With less design step and resource, the body bias can be achieved in cell-based design flow. The example of body bias applied on NMOSFET is illustrated below.
The principle of adding body bias for NMOSFET is shown on Figure 3.8. Key point in this design phase is removing body terminal from power grid, adding extra power straps for body terminal voltage controlling and sticking body terminal on power straps. Of course, there are several details must be considered in this design flow. The layout diagram of design process is shown in Figure 3.9. In order to create extra metal liens for VSSB, the standard cells are placed at appropriate intervals, which can be done by using the conventional P&R tool with appropriate parameters.
Next, PIMP and DIFF patterns are added to the interval between standard cells.
Finally, the removing contact located on VSS line and adding contact on the VSSB line is implemented.
The figure 3.10 shows the design flow of body bias with well pattern addition and contact modification. There are five extra steps added into design flow:
z Decide Interval z Create Power Ring z Add Straps z Add DIFF & PIMP z Contact Modification
During Decide Interval, standard cells are placed at the appropriate interval, which are used to add VSSB metal straps without violating design rule. The appropriate intervals can be determined by design parameters. If biasing both Body terminals of NMOSFET and PMOSFET are needed, it can be realizing, e.g. No Double Back shown in Figure 3.11, by appropriate parameter.
When Create Power Ring, just like body bias design flow with dual supply standard cell supported, extra power ring is creating for VSSB strap addition. After creating power rings for VSSB, connecting ports to power and ground nets in the placement design phase is specified. Next, the extra straps for VSSB power line are added from
power delivery grid and inserted into intervals between standard cells. The strap addition can be inserted by conventional P&R EDA tool command. It makes the strap addition more efficiently and avoids error created by hand.
Next, the DIFF and PIMP patterns are added by commercial P&R tool command.
The patterns overlap to the standard cell can be adjusted by command parameter.
According to characteristic of standard cells, this method can adjust the degree of overlap to fit the demand of design. Finally, the modification of contact is implemented. Removing substrate contacts within the standard cells and adding contact on VBBS metal lines make the complete isolation of Body and Source terminals. Therefore, the body bias implementation with modified Cell-Based flow is done.
VDD
VDD VSS
VDD
VDD VSS
VSS VSS
VSSB
Figure 3.8 Schematic diagram of body bias design principal.
VSS
BODY VSS BODY
SOURCE
DIFF PIMP
Add Metal Contact Remove
VSSB Add
Contact Interval
Figure 3.9 Layout view of body bias design principle.
Figure 3.10 Physical design flow of body bias implementation.
Std Cell
Figure 3.11 Design parameter of cell placement.
3.4 Power Switch Implementation
In Section 3.4, the implementation of power switch is introduced. Entire design phase of power switch is using Cadence Virtuoso-XL and verified by Mentor Calibre.
The NMOSFET power switch implementation diagram is shown in Figure 3.12. The power switches are added below VSS net and distributed throughout the layout in two main VSS columns in order to reduce any current crowding issues.. During implementation of power switch, some layout modification is need for VSS delivery grid.
The layout of NMOSFET power switch is indicated in Figure 3.13. The NMOSFET use multi-finger type architecture. The multi-finger architecture provides larger channel width in the limit area, which is suitable for cell-based design and is inserted below the power delivery grid. In order to change general delivery gird to fit power switch insertion, some modification of power delivery is needed. The principle of modification is shown in Figure 3.14 and Figure 3.15. Figure 3.14 and Figure 3.15 show the cross-sections of general VSS delivery grid and modified VSS delivery grid, respectively. Compare Figure 3.14 and Figure 3.15, the contact between metal 1 and metal 2 is removed and a NMOSFET power switch is inserted. The Gate terminal of NMOSFET is driven by sleep signal. Figure 3.16 shows the location of power switches in the entire core.
Metal 2
Metal 1
VSS
Virtual VSS Power Switch
Cell
Figure 3.12 Diagram of power switch implementation.
Drain
Source Gate
Figure 3.13 Layout of multi-finger type NMOSFET power switch.
Figure 3.14 Profiles of general VSS delivery grid.
P-well
P+
N+
N+
V1
CO CO
CO
Metal 1 Metal 1
Metal 2
PO CO Metal 1
P-substrate
VSS
Power Switch
Figure 3.15 Profile of VSS power delivery grid for power switch. Modified VSS delivery grid, indicating the insertion of power switch and remove of contact.