This subsection shows the related works covering two major targets of interconnect detection and diagnosis in Section 2.7.1 and oscillation ring scheme (also known as ring oscillator in some fields) in Section 2.7.2.
2.7.1 Interconnect Detection and Diagnosis Test Architectures & Algorithms Interconnect test and diagnosis for various applications, such as printed circuit board (PCB), multi-chip module (MCM), and systems in package (SiP), have been studied extensively in the literature [7, 14, 61, 62, 89, 122, 124].
Previous works on interconnect test, including fault detection and diagnosis, focus mainly on traditional fault models including stuck-at and bridging faults. Those diagnosis algorithms include counting sequence, walking-0 and walking-1 sequence, maximum anti-chain, maximal independent test set [20, 21], etc. An efficient way to apply these tests is to exploit the boundary-scan architecture [58, 111, 117]. Many diagnosis algorithms presented in previous works focus mainly on special interconnect structures, especially for bus-oriented systems [108], sparsely interconnected systems [26], or FPGA designs [1, 46, 114]. The diagnosis of wire delay and crosstalk faults, often considered the most important segments of interconnect diagnosis, has attracted increasing attention since the process technology enters the deep submicron era. Much work has been done in these areas, including the development of fault models, test generation algorithms, and test methodology for delay tests [63] and BIST schemes for crosstalk faults [109, 111, 117]. However, the counting sequence and the maximal independent test set detect faults without
diagnosing the faulty positions. On the other hand, the walking-one sequence can detect and diagnose all faults, but its test length is too long. Therefore, an interconnect test algorithm to diagnose all faults within a short testing period is not only desired but required. The new algorithm named the group, net, shifted net (GNS) sequence can detect and diagnose all faults within a much shorter testing period than previous diagnosis algorithms [62]. However, most previous work focus only on stuck-at, open or short faults, not crosstalk-induced glitches and delay faults due to nanotechnology effects.
There are many other pioneer researchers in interconnect test problem in additional to previous mentioned works. Shi et al. [106] studied the diagnosis problem on the interconnect diagnosis with randomized algorithm. They formulated the interconnect diagnosis problem as a two-dimensional graph problem and studied the complexity of that problem. Unlike the work in [21] which is based on graph mixing theory and adjacency analyses, they explored the behavior diagnosis on that architecture using the worst-case scenario—they proved that it is NP-complete to determine whether a given interconnects can have full diagnosis (detection and identification/location). Again, their target fault model is only short, and adjacency relations are known.
The conclusions in the above subsections lead to the architectural choice: general interconnect structure combined with a general graph topology analysis which gives the best area and routability trade-offs. A theoretical study of flexibility and routability was later presented based on a routing framework and model with congestion-guided weight which confirms the experimental results in [81, 82].
The worst cases occur when most nets are very long and are routed in some
specially designed topologies, a complete tree structure of an entire SoC chip (see Figure 2.19 for a worst-case instance shown in [77-80]). Especially, global interconnects are often very long and often takes cycles to communicate in SoC ICs which leads to the motivation of our systematic study on interconnect diagnosis problem with the optimal resolution. Later in Chapter 5, we will show the formal definition of the optimal resolution of interconnect diagnosis which is roughly referred as uniquely identifying any fault. This work provides a theoretical insight to the worst-case performance of interconnect diagnosis problem by using that oscillation ring test architecture.
Figure 2.19 A worst-case scenario of interconnect structure or topology in SoC.
We considered a variation of the interconnect detection architecture modeled in Chapters 4 and 5 [77-80]. See Figure 2.4 for an illustration of the architecture and an interconnect routing on that architecture.
2.7.2 Oscillation Test Schemes
Oscillation based test is an efficient and effective method to detect faults in a circuit or a device [6, 58]. Recently, oscillation ring test is applied for system-level interconnects for delay faults and crosstalk glitch faults [77-78]. The proposed oscillation test methodology attacks the testing problem from a different perspective.
It modifies the storage elements such that oscillation signals can be generated according to the functional specifications of a given circuit.
2.7.2.1 Analog and Mixed Signal Domain
Ring Oscillator related techniques are developed in many prospects [6], [52], [58], [103] such as Selective Process Bias (SPB) of interconnects, Phase Noise, and etc. There are many works on oscillation tests. For example, Kaneko and Sakaguchi proposed an oscillation fault diagnosis method for analog circuits based on boundary search with perturbation model [58].
2.7.2.2 Digital Domain
With contrast with [6], Lee and Wu develop an oscillation test scheme in logical level (gate-level) [119-120]. [120] proposes a new test scheme, oscillation ring test, and its associated test circuit organization for delay fault testing for high performance microprocessors. For this test scheme, the outputs of the circuit under test are connected to its inputs to form oscillation rings and test vectors which sensitize circuit paths are sought to make the rings oscillate. High speed transition counters or oscillation detectors can then be used to detect whether the circuit is working normally or not. The sensitizable paths of oscillation rings cover all circuit lines, detecting all gate delay faults, a large part of hazard free robust path delay faults and all the stuck-at faults. It has the advantage of testing the circuit at the working speed of the circuit. Also, with some modification, the scheme can also be used to measure the maximum speed of the circuit. The scheme needs minimal simple added hardware, thus ideal for testing, embedded circuits and microprocessors. Further in
[119], a test scheme for the crosstalk fault based on the oscillation signal is proposed.
It uses an oscillation signal applied on an affecting line and detects induced pulses on a victim line if a crosstalk fault exists between these two lines. It is simple and eliminates the complicated timing issue during test generation for the crosstalk fault in the conventional approaches. The test generation and fault simulation based on the scheme are described.
In our work, we have a total different approach and focus on system-level interconnects. However, later in Chapter 6, we adopt a different approach of finite machine synthesis to deal with gate-level oscillation ring test scheme.
Chapter 3