以交連線為中心加強系統晶片可測試性及良率之震盪環結構與演算法

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(1)國立交通大學電子工程學系電子研究所. 博士論文. 以交連線為中心加強系統晶片可測試性及良率之震盪環結構與演算法 Interconnect-Centric Oscillation Ring Architectures and Algorithms for SoC Testability and Yield Enhancement. 研究生：李淑敏指導教授：李崇仁. 中華民國九十五年. i. 博士. 一月.

(2) Copyright by KatherineShu-Min Li 2006. ii.

(3) INTERCONNECT-CENTRIC OSCILLATION RING ARCHITECTURES AND ALGORITHMS FOR SOC TESTABILITY AND YIELD ENHANCEMENT by Katherine Shu-Min Li, B.S., M.S.. DISSERTATION Presented to the Faculty of the Graduate School of National Chiao Tung University in Partial Fulfillment of the Requirements for the Degree of. DOCTOR OF PHILOSOPHY. NATIONAL CHIAO TUNG UNIVERSITY AT HSINCHU January 2006. iii.

(4) To my parents, Yoan-Jian Lee and Ru-Huai Xue.. iv.

(5) 摘要交連線在深次微米及奈米技術中日益重要，因此，交連線的可測試性及良率之問題引起眾多學者投入研究。本博士論文是以震盪環測試結構與演算法(Oscillation Ring Architectures and Algorithms)來解決交連線的可測試性及良率之問題。我們所提出的震盪環測試機制符合 IEEE1500標準並用以測試與診斷系統單晶片 (System on Chip,SoC)的交連線。我們面對兩項技術挑戰，第一項、設計複雜度使得交連線的可測試性及良率之問題不可避免。第二項、串音雜訊使得交連線的訊號整合性及延遲錯誤之問題受到重視。為了面對第一項設計複雜度的挑戰，我們的作法是將震盪環測試機制嵌入多接繞線器中以增進交連線的可測試性，並且提出以降低與平均繞線壅塞度的方法來增進交連線的良率之問題。為了面對第二項交連線的訊號整合性及延遲錯誤的挑戰，我們的作法是進行一些基礎分析與研究，茲列舉如下。 (1) 為了建立交連線震盪環結構與演算法的分析架構，我們擴充早先可在交連線上加入緩衝器的研究，所以我們所提出的震盪環測試機制是可與常用的緩衝器加入技術 (buffer insertion)相容。 (2) 為了測試交連線的訊號整合性及延遲錯誤，我們提出交連線串音整合偵測機制，其作法是不直接測試延遲錯誤，而是利用串音突波與串音延遲的關係來直接測試串音突波。為了證. v.

(6) 明此測試機制的有效性，我們以蒙地卡羅模擬來說明此機制即使在百分之二十的製程飄移下仍達成百分之九十二以上的測試良率。此處所發展的串音突波偵測器電路設計可用於交連線震盪環測試結構中。 (3) 為了提高交連線的可測試性，提出交連線震盪環測試結構與演算法。我們先提出基本的測試方法論，再進一步提出另一個交連線診斷與最佳化的方法與技術。 (4) 最後我們將交連線震盪環結構與演算法加以修改應用到全晶片繞線器上以及同步序向電路中。本博士論文提出以交連線為中心加強系統晶片可測試性及良率之震盪環結構與演算法來解決交連線的可測試性及良率之問題。綜結以上各觀點，完成了五篇國際論文與提交了六篇期刊論文。. vi.

(7) INTERCONNECT-CENTRIC OSCILLATION RING ARCHITECTURES AND ALGORITHMS FOR SOC TESTABILITY AND YIELD ENHANCEMENT. Katherine Shu-Min Li, Ph.D. National Chiao Tung University, 2006. Supervisor: Dr. Chung-Len Lee. Interconnects play a dominant role in deep-submicron and nanotechnologies. As a result, testability and yield problems of interconnects attract increasing attention. The paradigm shift of the interconnect-related problems is indispensable to cope with two major challenges as technology advances into nanometer territory: z. The ever increasing design complexity of gigascale integration renders testability (detection and diagnosability) and yield enhancement inevitable.. z. The complicated physical effects inherent from the scaling effects in nanoscale technology make crosstalk noise (crosstalk-induced glitch faults and crosstalk-induced delay) inevitable, and thus signal integrity and delay faults can no long be ignored. The motivation of this research is targeted at testability and yield enhancement. with test time reduction at design stages by our proposed Oscillation Ring (OR) test mechanism. These advantages of the oscillation ring test mechanism have made interconnects detectable and diagnosable through a systematic graph modeling approach. As a relatively novel methodology, OR mechanism for system-level interconnects should be compliant to IEEE Std. 1500. Thus, it is desirable to consider vii.

(8) test architectures and algorithms for interconnect testing for System on Chip (SoC) under IEEE Std. 1500, and develop interconnect-centric computer-aided-design tools including design, detection, and diagnosis. To handle the first challenge, the ever increasing design complexity of gigascale integration, we integrate our proposed oscillation ring test techniques into a signal-integrity-aware router. We propose an integrated multilevel full-chip routing algorithm that improves testability and diagnosability, manufacturability, and signal integrity for yield enhancement. Two major issues are addressed. (1) An oscillation ring test and diagnosis scheme for interconnects, based on IEEE Std. 1500, is integrated into the multilevel routing framework to achieve testability enhancement. We augment the traditional multilevel framework by introducing a preprocessing stage of Interconnect Oscillation Ring Detection (IORT) that analyzes the oscillation ring structure for better resource estimation before the coarsening stage, and a postprocessing (final) stage of Interconnect Oscillation Ring Diagnosis (IORD) after uncoarsening that improves testability to achieve 100% interconnect fault coverage and maximal diagnosability. (2) We present a heuristic to balance routing congestion, and the goals of this router include minimizing multiple-fault probability, reducing crosstalk effects, and improving. yield. for. optical-proximity-correction. both. chemical-mechanical-polishing. (OPC). induced. (CMP). manufacturability. and. problems.. Experimental results on the MCNC benchmark circuits demonstrate that the proposed OR method achieves 100% fault coverage and the optimal diagnosis resolution for interconnects, and the multilevel congestion-driven routing algorithm effectively balances the routing density to achieve 100% routing completion. Experimental. viii.

(9) results show that our method significantly improves routing quality for testability and yield enhancement. To deal with the second challenge for signal integrity problem, the crosstalk-induced faults have caused significant impact on interconnect performance as technology advances into nanometer era. The crosstalk is a phenomenon of parasitic capacitance caused by continuous scaling effects. It directly influences reliability, manufacturability and yield of VLSI circuits. (1) We present buffer planning techniques for designing and analyzing crosstalk noise together with performance during floorplanning, and show theoretically and experimentally that our interconnect-aware floorplanner outperforms currently available ones with simultaneously considering crosstalk and timing as our preliminary work which paves the base for IORT and IORD. (2) There are two types of crosstalk: crosstalk-induced glitch and crosstalk-induced delay. We analyze and design the detection of crosstalk faults for interconnect bus, and show experimentally that the unified detection scheme for crosstalk-induced glitch and crosstalk-induced delay is feasible and effectively. This scheme is based on a built-in pulse detector with an adjustable threshold voltage, and we show that this design works well under process variations. Furthermore, the pulse detector in the crosstalk unified detection scheme is embedded into IEEE Std. 1500 wrapper compliant cells so that oscillation ring test for the interconnect test can handle the delay fault, which poses challenges to system performance. (3). We study interconnect detection and diagnosis problems for interconnects. We show a class of oscillation ring approximation algorithms for an interconnect. ix.

(10) detection and diagnosis problem and prove that oscillation ring mechanism with IEEE Std. 1500 compliant test architecture guarantees 100% fault detection (by IORT) and the optimal diagnosis resolution (by IORD) not only under the fault models of traditional stuck-at and open faults, but also delay and crosstalk glitch faults. Solutions to the interconnect problems by applying oscillation ring methodology pave the way for developing a novel integrated multilevel routing framework with a congestion metric for routing as mentioned above. (4) Finally, the oscillation ring test method has been successfully modified and applied to synchronous sequential circuits to facilitate at-speed test for delay fault detectable in addition to traditional stuck-at and open fault models. In summary, both testability and signal integrity issues have significant impact on interconnect design and test. In my PhD dissertation, an interconnect-centric oscillation ring architectures and algorithms targeted for SoC testability and yield enhancement is proposed to deal with system-level interconnect test and diagnosis, full-chip integrated multilevel router framework, and RTL (register transfer level) synchronous sequential circuits for at-speed testability.. x.

(11) Acknowledgements I am greatly indebted to my thesis advisor, Professor Chung Len Lee, for his tremendous support, encouragement, and guidance throughout my graduate study. Many discussions with him helped me progress in the right directions. I am also very grateful to him and Ms. Lee, also known as Prof. Hsu, for their help in many other matters, academically and socially. I would like to thank Professor Chauchin Su, Professor Yao-Wen Chang, for inviting me to join in their research groups and to be exposed to the bright research environments. They provided me with invaluable advice and encouragement. I wish to thank Professor Jwu E Chen in Department of Electrical Engineering of National Central University for his constant, immense encouragement and support, and inviting me to join multiple participation of EDA Forum between Academia and Industries. I greatly appreciate the members of my dissertation committee. Professors Shih-Chieh Chang, Tsin-Yuan Chang, Yao-Wen Chang, Jwu E Chen, Chung-Len Lee, Jing-Yang Jou, Chauchin Su and Chen-Wen Wu for their interest in my work, for their invaluable comments and suggestions, and for their kind assistance in many occasions. Thanks are due to all members of the SoC Testing & DFT group for providing a forum to discuss my research. Specifically, I wish to thank Dr. Wen-Ching Wu and Dr. Yeong-Jar Chang, Prof. Soon-Jyh Chang, Ming-Sheu Wu, Sheu Ping Lin. I especially appreciate Yoyo Chang at the department's Graduate Office for her professional assistance in all administrative and project matters. Special thanks go to EDA Lab leading by Professor Yao-Wen Chang including Dr. Tsung-Yi Ho, Tai-Chen Chen, Tung-Chen Chen of National Taiwan University xi.

(12) for their pioneering work on Routing and for providing me with the LEDA packages for my comparative studies. Also special thanks go to Mixed-Signal Circuit Lab leading by Professor Chauchin Su for all the valuable discussion about circuit related characteristics with Hung Wen Lu, Hung Kai Chen, Ren-Qian Xu, Yu Hwai Tseng in Department of Electrical and Control Engineering of National Chiao Tung University. Thanks also go to many wonderful friends who made my life in Hsin Chu so pleasant and unforgettable. Especially, I would like to express my appreciation to Prof. Pu Hsu for her assistance and support. Also, many thanks to my co-labs and classmates in SoC Testing & DFT Lab in Department of Electronics Engineering, National Chiao Tung University and EDA Lab in Department of Electrical Engineering, National Taiwan University (also previously known as VLSI&EDA Lab in Department of Computer and Information Science, Chiao Tung University). My deepest appreciation goes to my parents, sisters and brothers for their unending love and support, and my uncle Yuan-Cai Lee and aunt Li-Zhou Gao, uncle Ru-Mao Xue and aunt Mei-Yun Zheng for their encouragement and help. Last, but not least. I am very grateful to the rest of my family: without their sacrifices and patience, the completion of this thesis would not have been possible. Katherine Shu-Min Li National Chiao Tung University January 2006. xii.

(13) Table of Contents. Chinese Abstract. v. English Abstract. vii. Acknowledgements. xi. Table of Contents. xiii. List of Tables. xviii. List of Figures. xix. Chapter 1.. Introduction. 1. 1.1 Interconnect-Centric Study vs. Oscillation Ring Test Methodology ..... 1. 1.2 Challenges of Interconnect-Centric Research........................................ 4. 1.3 Interconnect Issues in Design and Test Process..................................... 8. 1.4 Overview of the Dissertation ................................................................. 11. 1.4.1. A unified approach to detecting and optimizing ........................ 12. 1.4.2. IEEE Standard 1500 Compatible Interconnect Delay and Crosstalk Test Methodology ...................................................... 12. IEEE Standard 1500 Compilant Interconnect Diagnosis for Delay and Crosstalk Glitch Faults.............................................. 14. Oscillation Test for Synchronous Sequential Circuits (also known as Finite State Machine Synthesis for At-Speed Oscillation Testability) ............................................................... 15. Multilevel Full-Chip Routing with Testability and Yield Enhancement .............................................................................. 16. 1.5 Organization of the Dissertation ............................................................ 18. 1.4.3 1.4.4. 1.4.5. Chapter 2.. Preliminaries. 20. 2.1 Interconnect Models............................................................................... 20. 2.1.1. Interconnect Model for Detection .............................................. 20. 2.1.2. Interconnect Model for Diagnosis.............................................. 22. 2.2 Oscillation Ring Test Methodology....................................................... 24. 2.2.1. Oscillation Ring Test Architecture & Operations ...................... 24. 2.2.2. Effectiveness of Oscillation Ring Test Scheme ......................... 26. xiii.

(14) 2.2.2.1 Effectiveness for Delay Fault ................................................. 26. 2.2.2.2 Effectiveness for Crosstalk Faults .......................................... 27. 2.2.3. IEEE 1500 Compliant Wrapper Cell Design ............................. 30. 2.2.3.1 Pulse Detector......................................................................... 30. 2.2.3.2 Wrapper Cell with Embedded Pulse Detector........................ 31. 2.2.4. Delay Measurement Formula ..................................................... 34. 2.3 Interconnect-driven Floorplanning ........................................................ 34. 2.3.1. Crosstalk Noise and Signal Integrity.......................................... 35. 2.3.2. System-Level Framework for Oscillation Ring Test ................. 38. 2.4 Interconnect-driven Routing................................................................... 38. 2.4.1. Applications of the Oscillation Ring Test Methodology as a DFT technique............................................................................ 39. 2.4.2 Congestion vs. Design for Yield ................................................ 40. 2.4.3. Multilevel Routing Framework .................................................. 40. 2.4.4. Our Integrated Multilevel Routing Framework.......................... 42. 2.5 Assumptions and Limitations ................................................................ 43. 2.6 Interconnect-Centric Detection and Diagnosis Techniques................... 43. 2.6.1. Interconnect Detection Technology ........................................... 44. 2.6.2. Interconnect Diagnosis Technology .......................................... 45. 2.6.3. Summary of Interconnect Technologies. ................................... 45. 2.7 Previous Works ...................................................................................... 46. 2.7.1 Interconnect Detection and Diagnosis Architectures & Algorithms.................................................................................. 46. 2.7.2 Oscillation Test Schemes ........................................................... 48. Chapter 3.. 2.7.2.1. Analog and Mixed Signal Domain ............................ 49. 2.7.2.2. Digital Domain........................................................... 49. A Unified Approach to Detecting Crosstalk Faults of Interconnects in Deep Submicron VLSI. 51. 3.1 Introduction............................................................................................ 52. 3.2 The Crosstalk Detection Analysis Problem ........................................... 53. 3.2.1 Circuit Model for Crosstalk........................................................... 53. 3.2.2. Crosstalk Fault Effects ................................................................. 55. 3.3 Analysis to Relationships between Crosstalk-Induced Glitches and Crosstalk-Induced Delay ........................................................................ 59. xiv.

(15) 3.3.1 Glitch vs. Delay............................................................................. 59. 3.4 Pulse Detector with Adjustable Detection Threshold............................ 61. 3.5 Some Considerations for Unified Detection Scheme ............................ 63. 3.5.1. Glitch Amplitude and Width ...................................................... 63. 3.5.2 Effect of Skew between Aggressor and Victim Signals ............. 65. 3.5.3 Process Variation Effect on Pulse Detector ................................ 66. 3.6 Experimental Results of Monte Carlo Simulation on Unified Detection Scheme Considering Process Variations ............................. 67. Chapter 4.. IEEE Standard 1500 Compatible Oscillation Ring Based Interconnect Delay and Crosstalk Test Methodology. 71. 4.1 Introduction............................................................................................ 71. 4.2 Interconnect Test Architecture for Oscillation Ring Test...................... 75. 4.3 IEEE Standard 1500 Compliant Modified Wrapper Cell Design.......... 77. 4.4 Oscillation Ring Construction: Model and Analysis ............................. 80. 4.4.1. Graph Model for Oscillation Ring Tests.................................... 82. 4.4.2. Analysis of Rings and Test Cost................................................ 84. 4.5 Oscillation Ring Construction Algorithm.............................................. 86. 4.5.1. Exact Algorithm......................................................................... 86. 4.5.2. Ring Generation Algorithm: A Heuristic Algorithm ................. 87. 4.6 Experimental Results ............................................................................. 89. 4.6.1. Simulated Results on HP benchmark circuit ............................. 90. 4.6.2. Oscillation Ring Generation for Interconnect Detection Algorithm................................................................................... 93. Chapter 5.. IEEE Standard 1500 Compliant Interconnect Diagnosis for Delay and Crosstalk Faults. 5.1 Introduction........................................................................................... 100 5.2 Oscillation Ring Test Scheme for Interconnect Diagnosis ................... 104 5.2.1 Oscillation Test Architecture ..................................................... 104 5.2.2 Enhanced IEEE Standard 1500 Compliant Wrapper Cell Design ........................................................................................ 107 5.2.3 Crosstalk Glitch Detection ......................................................... 108 5.2.4 Interconnect Graph Models........................................................ 110 5.2.5 Motivation and Problem Formulation........................................ 113. xv. 99.

(16) 5.2.5.1. Problem Complexity .................................................... 113. 5.2.5.2. Problem Formulation and Constraints ......................... 114. 5.3 Interconnect Diagnosability .................................................................. 116 5.3.1 Diagnosability Analysis .............................................................. 116 5.3.2 Heuristic Diagnosability Check .................................................. 119 5.3.3 Number of Test ........................................................................... 123 5.4 Interconnect Diagnosis Algorithm........................................................ 125 5.4.1 Fast Heuristic Diagnosability Check .......................................... 125 5.4.2 Interconnect Oscillation Ring Construction for Fault Detection 126 5.4.3 Interconnect Oscillation Ring Generation for Fault Diagnosis... 127 5.5 Optimization Techniques for Interconnect Diagnosis .......................... 129 5.5.1 Concurrent Tests ......................................................................... 129 5.5.2 Adaptive Tests ............................................................................ 132 5.6 Experimental Results ............................................................................ 133 5.6.1 Comparison between Predetermined and Adaptive Methods ...... 133 5.6.2 Comparison between Predetermined and Concurrent Methods ... 136 5.6.3 Comparison between Theoretical Bounds and Experimental Results ..............................................................................................137 Chapter 6.. Oscillation Test for Synchronous Sequential Circuits. 6.1 Introduction to Finite State Machine Synthesis for At-Speed Oscillation Testability ........................................................................... 140 6.2 Problem Formulation: Oscillation Test for Sequential Circuits ........... 143 6.2.1 Oscillation Ring Test Architecture at Logic Level ..................... 143 6.2.2 Modified State Register Design .................................................. 146 6.2.2.1. Modified State Register Design for Asynchronous Test...................................................................................146. 6.2.2.2. Modified State Register Design for Synchronous Circuits......................................................................... 148. 6.3 Synchronous Oscillation Ring Test ...................................................... 149 6.3.1 Constructing Oscillation Signals from FSM............................... 149 6.3.2 MSR State Transition Algorithm ................................................ 150 6.3.3 Test Pattern Generation Algorithm for Oscillation Test............. 155 6.4 Experimental Results of Oscillation Test Pattern Generation Algorithm .............................................................................................. 156. xvi. 140.

(17) Chapter 7.. Multilevel Full-Chip Routing with Testability and Yield Enhancement. 160. 7.1 Introduction........................................................................................... 161 7.2 Preliminaries ......................................................................................... 168 7.2.1. OR Test Architecture for Interconnects .................................... 168. 7.2.2. Process Variation Effects on Oscillation Signals ...................... 170. 7.2.3. Interconnect Models in Oscillation Ring Test........................... 171. 7.2.4. Interconnect Diagnosis Model with Oscillation Ring Tests...... 172. 7.2.5. Chemical Mechanic Polishing Model ....................................... 173. 7.2.6. Signal Integrity .......................................................................... 174. 7.3 Multilevel Routing Framework............................................................. 176 7.3.1. Routing Model........................................................................... 176. 7.3.2. Testability-Aware Multilevel Routing ...................................... 178. 7.3.3. Diagnosability-Aware Routing Structure.................................. 178. 7.3.4. Cost Metric for Routing Density Control.................................. 181. 7.4 Experimental Results............................................................................. 184 7.4.1. Testability Enhancement ........................................................... 184. 7.4.2. Congestion Control for Multi-objective Optimization.............. 187. Chapter 8.. Conclusions. 193. 8.1 A Unified Approach to Detecting Crosstalk Faults of Interconnects in Deep Submicron VLSI .......................................................................... 193 8.2 IEEE Standard 1500 Compatible Oscillation Ring Based Interconnect Delay and Crosstalk Test Methodology ................................................ 194 8.3 IEEE Standard 1500 Compliant Oscillation Ring Based Interconnect Diagnosis for Delay and Crosstalk Faults ............................................. 195 8.4 Oscillation Ring Test for Synchronous Sequential Circuits.................. 195 8.5 Multilevel Full-Chip Routing with Testability and Yield Enhancement ......................................................................................... 196 8.6 Future Work .......................................................................................... 196. Bibliography. 199. Vita. 208. Publication List. 209. xvii.

(18) List of Tables. 2.1. Control signals for the modified input wrapper cell. ............................. 33. 2.2. Control signals for the modified output wrapper cell. ........................... 33. 4.1. Control signals for the modified input wrapper cell (also same as Table 2.1) ............................................................................................... 79. Control signals for the modified output wrapper cell (also same as Table 2.2) ............................................................................................... 79. Comparison between the number of rings generated for experimental and theoretical results of Lower Bounds ............................................... 94. 4.4. Analysis of Ring Length Characteristics ............................................... 95. 5.1. Experimental results for Interconnect Diagnosis both for Predetermined and Adaptive Methods................................................... 138. 5.2. Comparison between Predetermined and Concurrent Methods............. 138. 5.3. Comparison of number of test rings between theoretical bounds and experimental results ............................................................................... 139. 6.1. Statistics of benchmark circuits ........................................................... 158. 6.2. Experimental comparison between our proposed oscillation test generation and pure scan methods. ...................................................... 159. Experimental Results based on the MCNC benchmarks for testability enhancement of interconnect detection and diagnosis........................... 185. 7.2. Routing benchmark circuits ................................................................... 186. 7.3. Comparison of routing results of maximum density with both maximum delay and average delay........................................................ 191. Comparison of routing results of statistical density with Lin’s in ICCAD 2002 .......................................................................................... 191. Comparison of routing results of statistical density with Ho’s in ICCAD 2003 .......................................................................................... 192. 4.2 4.3. 7.1. 7.4 7.5. xviii.

(19) List of Figures. 1.1. Interconnect (a) Moore’s Law, (b) Scaling effects on memory and microprocessor. (Source: Intel for (a); Source: Intel at ISSCC-03 for (b)) ........................................................................................................ 2. For 90 nm technology, interconnect delay will account for 75% of the overall delay. (Source: Cadence Design System) ............................ 3. Important effects of global interconnects (Source: Tutorial of ICCAD’00) ........................................................................................... 4. 1.4. An SoC circuit. (Source: on the courtesy of Prof. K. –J. Lee) ............ 6. 1.5. Crosstalk Effects (a) Crosstalk-induced Delay, (b) Crosstalk-induced Glitch. (Source: Magma Design Automation, Inc.) ............................. 7. Comparison of probability of faults between short and open faults (Source: de Gyvez, SLIP01) ................................................................. 9. (a) The interconnect diagram for SoC, (b) hypernet graph, (c) interconnect graph model with 2-pin nets for detection. ..................... 21. 2.2. Graph model for delay faults. .............................................................. 22. 2.3. (a) a multiple-sink hypernet, and (b) an interconnect diagnosis graph model. ................................................................................................... 23. 2.4. Test architecture of system-level interconnect test for SoC ICs............ 25. 2.5. Simulated waveforms of the longest (a) and shortest rings (b) of benchmark circuit hp. ........................................................................... 26. Oscillation signal on the ring, induced glitches on the victim net, and counter output. ..................................................................................... 27. Illustration on how the glitches are detected, an oscillation signal (top), the resulting crosstalk-induced glitch, the detector output, and the signal after 5 wrapper cells (middle), the counter output with the verified state change (bottom). ............................................................ 28. A pulse detector (PD) with an adjustable threshold by W/L ratio of INV1 ...................................................................................................... 31. Enhanced wrapper cells with forced inversion (a) input (b) output .... 32. 2.10 Switch-level RC circuits for buffers and wires .................................... 35. 2.11 Noise due to crosstalk-induced current.................................................. 35. 2.12 The respective feasible regions Φ in , Φ di and Φ ni ∩ Φ di for inserting a buffer that meet the delay, noise and both delay and noise constraints .............................................................................................. 36. 1.2 1.3. 1.6 2.1. 2.6 2.7. 2.8 2.9. xix.

(20) 2.13 (a) The buffer placement: x is the optimized length between the source node and the first buffer, y is the optimized length between every pair of neighboring buffers, and z is the length between the last inserted buffer and the sink node. (b) The corresponding buffer model and wire (π) model...................................................................... 36. 2.14 The victim net suffers from multiple aggressor nets for the coupling capacitance ........................................................................................... 37. Four cases for the intersection of Φ id and Φ in ................................. 37. 2.16 Previous Multilevel Routing Framework Flow of [70] ....................... 41. 2.17 Crosstalk-Driven Multilevel Routing Framework Flow [49] .............. 41. 2.18 Our Integrated Multilevel Routing Framework with Testability and Yield Enhancement .............................................................................. 42. 2.19 A worst-case scenario of interconnect structure or topology in SoC .... 48. 3.1. Circuit model for the crosstalk analysis ............................................... 55. 3.2. Simulated crosstalk effects for large enough coupling capacitance, (a) the induced glitch and, (b) the induced delay ...................................... 56. Simulated crosstalk effects for smaller coupling capacitance, (a) the induced glitch, and (b) the induced delay ............................................ 58. 3.4. Superposition of crosstalk-induced delay ............................................ 60. 3.5. Monotonic relationships between the peak of the induced glitch and the induced delay ................................................................................. 60. A pulse detector (PD) with an adjustable threshold by W/L ratio of INV ...................................................................................................... 62. Simulated relationships between the threshold of detected pulse amplitude (Vth) with respect to the W/L ratio of the pulse detector (PD) ...................................................................................................... 62. 3.8. Glitch analysis with different resistances and coupling capacitances. 64. 3.9. Monte Carlo simulation of the induced delay vs. the induced glitch peak (Vp) ............................................................................................... 64. 3.10 The induced delay v.s. the peak of the induced glitch for three different cases: (1) SK1 = SK2 = 0 , (2) SK1 = SK2 = –80ps, and (3) SK1 = 0, SK2 = 45ps ............................................................................. 66. 3.11 Monte Carlo simulation of the threshold of detected pulse amplitude (Vth) with respect to the W/L ratio of the pulse detector ..................... 67. 3.12 Monte Carlo simulation of the Escape Probability and Overkill Probability with respect to (W/L) ratio ................................................ 68. 3.13 Monte Carlo simulation of the “Yield” with respect to process variation on parameter values .............................................................. 70. 2.15. 3.3. 3.6 3.7. xx.

(21) 4.1. Test architecture for interconnect crosstalk detection and delay measurement (also known as Figure 2.4) ............................................ 75. The oscillation signal, A, on the oscillation ring and the induced glitches, B, on the victim interconnect ................................................. 76. Modified wrapper cells: (a) input cell (b) output cell (also same as Figure 2.9) ............................................................................................ 78. (a) The interconnect diagram, (b) hypernet graph, (c) graph model with 2-pin nets (also same as Figure 2.1) ............................................ 81. 4.5. Graph model for delay faults (also same as Figure 2.2) ...................... 84. 4.6. Hypernet branches and rings ................................................................ 85. 4.7. Rings for adjacent output pins ............................................................. 85. 4.8. Interconnect Oscillation Ring Test (IORT) Algorithm. ...................... 89. 4.9. The placement and routing of an illustrative example of the OR testing for a benchmark circuit hp ....................................................... 91. 4.10 Simulated waveforms of the longest (a) and shortest rings (b) of benchmark circuit hp (also same as Figure 2.5) .................................. 92. 4.11 Simulated waveforms of glitches induced by oscillation signals in the longest ring of “hp” (also same as Figure 2.6) ............................... 93. 4.12 Distribution of the ring lengths for the benchmark circuits by applying OR testing ............................................................................. 97. 4.13 Relationship between fault coverage versus number of rings ............. 98. 4.2 4.3 4.4. 5.1. An example SOC circuit: (a) a hypergragh and 3 hypernets in the interconnect structure, (b) labelling all net segments or edges ............ 111. (a) a hypernet, and (b) the corresponding interconnect diagnosis graph model (Similar to Figure 2.3) .................................................... 112. An illustration example for the complexity of the interconnect diagnosis problem for a bus-structure .................................................. 114. 5.4. An interconnect diagnosis graph example ........................................... 119. 5.5. Flow chart of the heuristic for diagnosability checking ...................... 121. 5.6. A diagnosability example for Figure 5.5(b) ......................................... 122. 5.7. Matrices for the heuristic diagnosability checking .............................. 123. 5.8. The ring generation for interconnect fault detection algorithm (IORT) ............................................................................................................... 127. The ring generation for interconnect fault diagnosis algorithm (IORD) ................................................................................................. 128. 5.10 Diagnosis ring generation procedure ................................................... 129. 5.11 Scan chain constraint ........................................................................... 130. 5.2 5.3. 5.9. xxi.

(22) 5.12 (a) Conflict graph (b) Graph coloring .................................................. 131. 5.13 Pin reordering for interleaving configuration ...................................... 131. 5.14 An adaptive diagnosis tree ................................................................... 132. 6.1. Oscillation test architecture for sequential circuits: (a) Oscillation rings; (b) MSR states are controlled through scans, and (c) Oscillation test is controlled by system clock ...................................... 145. 6.2. MSR cell (a) normal mode, and (b) oscillation test mode ................... 147. 6.3. Control state table of an MSR cell ....................................................... 147. 6.4. MSR cell for synchronous oscillation test: (a) normal mode, (b) oscillation test mode ............................................................................ 148. 6.5. Oscillation Test Pattern Generation (OTPG) Algorithm ..................... 149. 6.6. State transition and output table of an FSM ........................................ 150. 6.7. Modified State Transition Table .......................................................... 151. 6.8. (a) Truth Table of a state bit, (b) Operation Table of the MSR cell state ...................................................................................................... 152. 6.9. Operation values of (a) {L, L}, (b) {R, F} .......................................... 153. 6.9. Operation values of (c) {R, R}, (d) {H, L} ......................................... 154. 6.9. Operation values of (e) {R, L}, (f) {F, H} ........................................... 154. 6.9. Operation values of (g) {R, H}, (h) {F, L} .......................................... 155. 6.10 Oscillation Test Pattern Generation (OTPG) Algorithm ..................... 156. 6.11 MSR cell state for state pair (a, e) ....................................................... 156. 7.1. (a) Yield enhancement in routing stage, and (b) Balancing routing congestion reduces multiple fault probability, CMP induced variation, OPC and crosstalk effects, all of which improve yield ....... 164. Test architecture among IPs for delay and crosstalk detection, and delay measurement (same as Figure 2.4) ............................................. 169. Simulation waveform with process variation effects on the oscillation ring test scheme .................................................................. 172. (a) hypernet, and (b) interconnect diagnosis graph model (Same as Figure2.1) ............................................................................................. 173. 7.5. Noise due to crosstalk-induced current ................................................ 175. 7.6. Routing Graph (a) partitioned layout, (b) routing graph ..................... 177. 7.7. Integrated multilevel routing framework ............................................. 179. 7.8. Two routing trees: (a) a spanning tree with three segments (b) a Steiner tree with the minimum number of intermediate nodes, resulting in five segments .................................................................... 180. (a) Shortest path algorithm, (b) n(v) computation ............................... 181. 7.2 7.3 7.4. 7.9. xxii.

(23) 7.10 Routing density distribution for mcc1 for (a) the performance-driven MR, (b) the routability-driven MR, (c) and the proposed algorithm ... xxiii. 190.

(24) Chapter 1 Introduction. Interconnect becomes the most critical concern in handling performance demand, design complexity and signal integrity, which are the most crucial challenges for designers in nanotechnology. However, to meet all the challenges in performance, complexity, cost, time-to-market, and nanotechnology related issues, the development of sophisticated testability methodology and Electronics Data Automation (EDA) tools for interconnects is essential. This thesis addresses issues on optimizing interconnect-centric oscillation testability and yield enhancement by architectural and algorithmic approaches.. 1.1. Interconnect-Centric Study The motivation arises in dominant effects of interconnects (Figure 1.1),. especially for square scaling effects in global interconnects (Figure 1.1(b)), and a more obvious trends appears with the nanotechnology in Figure 1.2 since for 90 nm technology, interconnect delay will account for 75% of the overall delay. A limitation of global interconnect routing (Figure 1.3) specially for SoC lies in their high complexity and density—due to the restricted nature of the interconnect structures, the complexity of the SoC ICs grow too quickly as the number of transistors increase due to Moore’s Law (Figure 1.1(a)). One feasible approach to significantly improving chip capacities based on interconnect architectures is to incorporate testability and. 1.

(25) diagnosability on an SoC chip with IEEE Std.1500 standards. To deal with a very high complexity and criticality of interconnect structure, it is desirable to develop a new technology and methodology for interconnect testing and diagnosis.. (a). (b) Figure 1.1 Interconnect (a) Moore’s Law (b) Scaling effects on memory and microprocessor (Source: Intel for (a); Intel at ISSCC-03 for (b)). 2.

(26) Figure 1.2 For 90 nm technology, interconnect delay will account for 75% of the overall delay. (Source: Cadence Design System). In Figure 1.3, by observing the relative relationship of the interconnect wirelength and device size (die size), the global wires dominates in nanometer process and SoC eras since intrinsic delay of device scales down by a factor of s, local interconnect delay remains the same, and the global interconnect delay increases by square of the scaling factors. The occurrence rates in both local and global wires of nanometer process are more than traditional process technology, with especially obvious difference in global wires.. 3.

(27) Local wires. Traditional Process Occurrence. Nanometer. Rate (Normalized). Global wires. Process. + System on Chip. wirelength die _ size. ~0. Source: Tutorial of ICCAD ‘00. Figure 1.3 Important effects of global interconnects (Source: Tutorial of ICCAD ‘00).. 1.2. Challenges of Interconnect-Centric Study The challenges in interconnects are listed as follows:. z. Design complexity, performance, and time-to-market (pull force): make interconnects critical in deciding performance. ¾. Testing and diagnosability (DfT): It combines the scalable interconnection structure in SoC with considerations of compliant IEEE Std.1500 for DfT (Design for Test), congestion for DfY (Design for Yield), and their applications in physical design including floorplanning and routing frameworks.. ¾. Testability and yield enhancement (DfM): . Furthermore, testability and yield enhancement is important in dealing those CMP, OPC related issues in DfM. Thus, our approach is that interconnect congestion influences multiple fault probability, CMP and. 4.

(28) OPC issues, which could be optimized by testability and yield enhancement technologies [81-82]. . Research has shown that decisions made during the design period determine 70% of the product's costs while decisions made during production only account for 20% of the product's costs. Further, decisions made in the first 5% of product design could determine the vast majority of the product's cost, quality and manufacturability characteristics. This indicates the great leverage that DfM can have on a company's success and profitability [33].. z. Signal Integrity: Crosstalk, process variation and related issues in design for manufacturing are caused by deep submicron and nanotechnology (push force). The motivation of our study focuses in analysis and detection of crosstalk effects including crosstalk-induced delay and glitches as shown in Figure 1.5. A typical interconnect-centric SoC circuit as illustrated in Figure 1.4 is. composed of three major components: modules or IPs, routing resources, and input/output (I/O) cells. In an SoC, a two-dimensional of IP/modules is surrounded by general interconnect/routing bounded by I/O cells. The modules or IPs contain combinational and sequential circuits that implement logic functions. The interconnections between the modules or IPs and the I/O cells are general and independent topology. We develop our proposed oscillation ring test methodology targeted for system-level interconnects in SoC circuits [77-80]. In physical design, the optimized circuits are then converted into geometric patterns called layouts. The Interconnect-centric physical design process consists of three steps: technology mapping, placement, and routing.. 5. A technology mapper.

(29) maps the optimized circuits into a circuit of logic gates. Thus, we develop an oscillation ring test mechanism targeted for at-speed testability in logic-level synthesis [83-84]. Then, the logic modules are placed by a placement program. In the final step of the physical design, a router assigns interconnects to establish the required connections among the modules or IPs. We integrated our proposed oscillation ring test architectures and algorithm into a congestion-driven multilevel router to enhance testability and yield [81-82]. Note that, in order to meet all the mentioned challenges, we propose an oscillation ring test schemes and test architectures, an effective DfT technique. Though not mentioned in details in the above paragraphs, testing and diagnosibility are integrated into many stages of the design process to show the effectiveness of oscillation ring test methodology.. Figure 1.4 An SoC circuit. (Source: on the courtesy of Prof. K. –J. Lee). 6.

(30) While the system-level interconnect design and test process is important, currently existing testing approaches for traditional interconnects do not apply to delay and crosstalk glitch faults. This is due to the intrinsic difference between the architectures and algorithms for oscillation-based and those for traditional interconnect test methods. Therefore, it is desirable to develop specific computer-aided-design (CAD) tools for the interconnect-driven oscillation ring methodologies with applications in other design stages, especially for physical design.. (a). (b) Figure 1.5 Crosstalk Effects (a) Crosstalk-induced Delay, (b) Crosstalk-induced Glitch. (Source: Magma Design Automation, Inc.). 7.

(31) As a relatively novel application of ring oscillator technology in digital domains, oscillation. ring. test. architectures. are. constantly. evolving,. and. so. are. Oscillation-Ring-specific CAD tools. Therefore, it is of particular importance to design interconnection detection and diagnosis architectures, to develop OR-specific CAD tools for the new test architectures, and to explore the interaction between the architectures and the CAD tools.. 1.3 z. Interconnect Issues in Design and Test Process Signal Integrity Problem for Interconnects:. (1) crosstalk noise, (2). crosstalk-induced glitch, crosstalk-induced delay. ¾. We present techniques for designing and analyzing crosstalk noise together with performance for interconnects during floorplanning, and show theoretically. and. experimentally. that. our. interconnect-aware. floorplanner outperform currently available ones with simultaneously considering crosstalk and timing [73-74]. ¾. There are two types of crosstalk: crosstalk-induced glitch and crosstalk-induced delay. We analyze and design for detection of interconnect bus, and show experimentally that the unified detection scheme for crosstalk-induced glitch and crosstalk-induced delay is feasible and effectively [75-76].. z. Testability Enhancement for Interconnect Detection and Diagnosis Problem ¾. We show a class of oscillation ring approximation algorithms for an interconnect detection and diagnosis problem and prove that oscillation ring (OR) mechanism with IEEE Std.1500 compliant test architecture guarantees. 8.

(32) 100% fault detection and the optimal diagnosis resolution not only to traditional stuck-at and open faults, but also to delay and crosstalk glitch faults [77-80]. ¾. The motivation of open faults is that open faults are significantly (3x) more likely to occur in Figure 1.6.. z. Yield Enhancement for interconnects by congestion-driven approach ¾. Solutions to the interconnect problems by applying oscillation ring methodology pave the way for developing a novel integrated multilevel routing framework with a congestion metric for routing. Experimental results show that the new metric significantly improves a router's average and balanced congestion [81-82].. Shorts: Opens: (opens). (shorts). Defect size. (Source: de Gyvez, SLIP01). Figure 1.6 Comparison of probability of faults between short and open faults (Source: de Gyvez, SLIP01).. 9.

(33) More specific, our approaches to study the related interconnect issues are listed as follows: z. An analysis of crosstalk noise framework for system-level interconnects: as preliminary study to study the problem of crosstalk effects on interconnects among modules or intellectual property (IP) ¾. Interconnect-Driven Floorplanning with Noise-Aware Buffer Planning [73-74].. z. An fundamental analysis of crosstalk noise detection scheme for system-level interconnect: to study the problem of crosstalk effects on interconnects among modules or IPs ¾. z. A unified approach to detecting and optimizing [75-76].. An Oscillation Ring Detection Methodology for System-Level Interconnects: to study the problem of crosstalk effects on interconnects among modules or IPs ¾. z. Oscillation ring based interconnect test scheme for SOC [77-78].. An Oscillation Ring Diagnosis Methodology for System-Level Interconnects: to study the problem of crosstalk effects on interconnects among modules or IPs ¾. IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults [79-80].. z. An Oscillation Ring Testability for Logic Synthesis: to study the problem of crosstalk effects and. delay issues on interconnects among modules or IPs at. gate level ¾ z. Finite State Machine Synthesis for At-Speed Oscillation Testability [83-84].. An Oscillation Ring Testability and Diagnosability for Routing: to study the problem of crosstalk effects on interconnects among modules or IPs. 10.

(34) ¾. Multilevel Full-Chip Routing with Testability and Yield Enhancement [81-82].. 1.4. Review of the Dissertation In this thesis, we focus on two closely related issues of Oscillation Rings:. interconnect architectures and interconnect algorithms. Interconnect is a crucial step in implementing circuits. Researchers have shown that the feasibility of interconnect design is most constrained by routing resources [70]. and routing delays dominate the performance (Figure 1). Congestion induced by scaling effects results in limited interconnect testability and diagnossability. On the other hand, congestion in interconnect would reduce routability. Thus designing interconnects to maximize their routability, testability and diagnosability under the area and delay constraints is desirable. Routing in the interconnect environment is more complicated than that in the traditional IC technologies by the constraints that all of the available routing resources are fixed in place. This constraints present new challenges in interconnect design, test and diagnosis in design stages including floorplanner and router which have not been encountered in the traditional IC technologies before and become dominant in SoC and nanotechnology. This thesis addresses two classes of problems in frameworks of system-level, logic-level and physical design (P&R): testability/diagnosability/yield enhancement designs and signal integrity for interconnects. More specifically, we consider the following issues and each topic is briefly introduced in the following subsection followed by detailed description in the following chapters. z. Crosstalk analyses and resulting in a unified detection scheme (Chapter 3). 11.

(35) z. System-level interconnect test structure designs by Oscillation Ring test scheme (Chapters 4 and 5). z. Synthesis for gate-level structure by Oscillation Ring test method (Chapter 6). z. Interconnect routing with oscillation ring detection and diagnosability technologies (Chapter 7).. 1.4.1. Interconnect Detection Analysis. Crosstalk-induced faults are the most important fault-models to study the signal integrity effects on interconnects in nanotechnology. The analysis problem, as discussed in Chapter 3 is informally described as follows. Crosstalk-induced delay consists of an original signal waveform and a crosstalk-induced glitch. The question is to determine if there exists both a feasible and unified detection mechanism for interconnect buses. The analysis problem focuses on an interconnect bus structure since the bus structure has parallel and long enough lines to induce excessive coupling capacitance, as is the main source of crosstalk faults. The above analysis has important applications to: z. The system-level interconnect design (Chapters 4 and 5).. z. Gate-level interconnect synthesis (Chapter 6).. z. Interconnect routing framework: The interconnect routability evaluation considering crosstalk fault detection and diagnosability.. 1.4.2. Interconnect Test Structure Design. Given an interconnect architecture and a set of nets, the interconnect detection problem is to find the faulty ring in which the faulty net belongs to under single fault. 12.

(36) assumption. Therefore, we design the oscillation ring test architectures according to IEEE Std. 1500 in Figure 4.1 and its compliant wrapper cell design in Figure 4.3. As to oscillation ring algorithms, an exact algorithm based on cover covering problem based on graph theory techniques was presented in our works [77-78]. However, since test ring generation problem as an automatic test pattern generation (ATPG) is NP-complete [44], thus QM-based (Quinn MacClusky) algorithm in the worst case is computationally expensive. Whether the analysis problem can be solved in polynomial time is still open. In Chapter 3, we first consider an approximation algorithm for analyzing the testability of interconnect detection modules in SoC circuits. We show that the proposed algorithm has provably good performance with 100% fault coverage for any interconnect for the two types of target faults of delay and crosstalk glitch faults, respectively, in additional to traditional stuck-at and open faults. Extensive experiments show that the algorithm is highly accurate and runs much faster than the exact QM algorithm. In Chapters 4 and 5, we consider the interconnect design problems, respectively. The main consideration in the interconnect design is the trade-off between the testability, diagonsability, congestion, routability, and yield of any interconnect structure. In Chapter 4, we study the oscillation ring test architectures and methodologies for general interconnect topologies, thus, 100% interconnect detection fault coverage achieved. In Chapter 5, we further explore the interconnect diagnosability and the optimal interconnect diagnosis resolution achieved by our algorithms. Interconnects usually occupy large areas with specially long and parallel global. 13.

(37) bus routing, and hence the testability and diagnosability of interconnects in SoC ICs is usually limited and results in reduction in yield. On the other hand, fewer interconnects would reduce its routability. Thus, it is desirable to design interconnect test structures and algorithms such that the number of its routable interconnects is maximized with provable testability and diagnosabilty, subject to the area and performance constraints. Experimental results show that our approach consistently outperforms the recent work in [106] and the works before [106] by a large margin in fault models, interconnect topology constraints and test clock control overhead.. 1.4.3. Interconnect Diagnosis Analysis. Given an interconnect architecture and a set of nets, the interconnect diagnosis problem is to find the wire segments for each net so that all faults of the net are located in addition to fault detection under single fault assumption. Interconnect diagnosis is a very complex problem. In order to make it manageable in any interconnect structure, the diagnosis problem is often solved using the two-stage method of detection followed by diagnosis. The goals of these two stages are: detecting the faulty oscillating ring of interconnects and diagnosing the faulty wire net segment in the faulty oscillating ring respectively. Unlike existing previous interconnect diagnosis schemes for traditional stuck-at or bridging faults, such as walking-0/walking-1, counting sequence, maximal independent test sets, we target at delay and crosstalk glitch faults [8-10]. There are much important interconnect diagnosis, such as FPGA or bus structures which can take full advantage of the special structures of the interconnect topology. Those two previously researches of traditional fault models and special structures (FPGA [46], bus-driven [108], sparsely. 14.

(38) [26]) interconnect diagnosis algorithms do not resemble their counterparts in the general interconnect structure or topology technologies. In particular, the diagnosis resolution information of interconnect structural limitation essentially is still measured by the numbers of test rings. Since the internal architecture of an interconnect topology decides what can generate oscillation test rings through the grids, the traditional measure of interconnect diagnosis capacity is no longer accurate especially for delay and crosstalk faults. The interconnect diagnosis resolution problem was previously considered by Shi and Fuchs [106]. In [106], a heuristic algorithm based on behavioral diagnosis techniques was proposed: however, the algorithm is only targeted at short, open and stuck-at faults. Our approach is targeted at crosstalk faults and delay faults without involving two-pattern clock control problem, and thus outperforms the traditional diagnostic approaches.. 1.4.4. Finite State Machine Synthesis for At-Speed Oscillation Testability. To study the delay test by using oscillation test mechanism, we study the problem of synchronous sequential test. However, gate-level structure limits oscillation testability. And thus, interconnect topology in logic level mainly determines the fault coverage. In order to release the interconnect structural limitations, we propose finite state machine synthesis with target faults of delay faults in addition to traditional stuck-at and open faults. Our proposed oscillation ring test mechanism in logic level is how to construct oscillation ring conditions by given a Finite State Machine (FSM). The idea is to choose candidates primary outputs of oscillating candidates “0” and “1” and force. 15.

(39) their next states to alter mutually. This approach is to release the interconnect structural limitations by the DfT techniques of embedding oscillation characteristics in logic synthesis scheme. The main difficulty is that this approach is only suitable to sufficient primary outputs or else oscillation signals can not propagate properly. The proposed method has three major advantages over the scan test. (1) It enables at-speed test, since oscillation test is triggered by system clock and thus operates at normal speed. (2) Faults are detected if outputs fail to oscillate, thus it is not necessary to store and analyze output response. Thus, the communication bandwidth between the automatic test equipment (ATE) and CUT is greatly reduced, which partly solves the problem of test data compression in SOC testing. (3) Our method does not need complex test clocks, which is required for two-pattern tests used in transitional delay tests. Test vectors can be derived directly from the finite-state machine (FSM) model in our OTPG algorithm, and it greatly simplifies the ATPG process accordingly.. 1.4.5. Multilevel Full-Chip Routing with Testability and Yield Enhancement. Interconnection delay plays an increasingly significant role in determining circuit performance, and thus timing-driven routing has received much attention recently. A model of graph-theoretic problem for finding minimum spanning trees with bounded diameter/radius was studied in [49]. This model assumes that the maximum signal delay, denoted by the tree diameter/radius, is in proportion to wiring length (path length in a tree). To improve circuit performance and maintain reasonable routability simultaneously, the congestion in routing channels is usually dense, and thus routing tracks consist of wires with a versatile set of lengths. Researchers have shown that the. 16.

(40) number of wire segments, instead of wire-length, used by a net is the most critical factor in controlling routing delay [50]. In other words, due to the segmented routing architectures, a signal delay is not necessarily in proportion to the geometric distance (wire-length) of the signal. Therefore it is desirable to consider the timing-driven routing-tree problem with four independent weights, two for the traditional signal delay and area, and the other two for the routability and the routing cost of congestion. To precisely capture the interconnect nature, we show in Chapter 7 a novel way to measure the congestion at individual routing blocks. We model interconnects as a weighted graph. The weights on the edges are proportional to the congestion on the corresponding resources. In particular, the routing congestion information of interconnect structural limitations essentially is still measured by the numbers of available grid boundaries in the interconnect topologies. Since the internal architecture of an interconnect topology decides what can route through the grids, the traditional measure of interconnect routing capacity is no longer accurate. We need to develop a new cost function and weight to include congestion-driven interconnect routing. Thus, we develop a technique that dynamically updates the weights based on the available resources. Experiments show an average congestion improvement of 1.0X-4.52X in the routing required to route MCNC benchmark circuits compared with an algorithm based on the traditional methods for density control [70]. In Chapter 7, recent works [81-82] have also shown that the higher the interconnect routability, the more difficult the testability and yield to achieve 100% fault coverage. Hence, it is of significant importance to consider the detection analysis for interconnects and we propose interconnect routing framework considering. 17.

(41) oscillation testability accordingly. In summary of Chapter 7, we consider a model of congestion-driven routing, based on the idea of finding minimum average congestion and variance of congestion in spanning trees (minimum congestion cost) with bounded delays, in a multiple weighted graph. We explore the complexity in two prospectives: (1) testability enhancement: this oscillation detection and diagnosability problem in multilevel routing framework, (2) yield enhancement: congestion-driven routing metric; and present simple, yet efficient and effective approximation algorithms for the problem. Experimental results show that our algorithms are very promising compared with previous works [49-50, 70].. 1.5. Organization of the Dissertation The rest of this dissertation is organized as follows. Chapter 2 presents related. issues for interconnects, problem formulation, some backgrounds on oscillation ring architectures and algorithms, and some fundamental frameworks to discuss interconnect-driven floorplanning with noise-aware buffer planning and multi-level routing. Chapter 3 discusses a unified approach to detecting and optimizing on-chip buses for speed and acceptable crosstalk problem. Chapter 4 introduces IEEE Std.1500 compatible oscillation ring interconnect delay and crosstalk test methodology and Chapter 5 explores the design problem for the IEEE Std.1500 compliant interconnect diagnosis for delay and crosstalk faults. Chapter 6 addresses the oscillation-specific routing problem and its application in multilevel full-chip routing with testability and yield enhancement. Chapter 7 studies the logic synthesis with oscillation testability to cover at-speed test problem. Finally, Chapter 8. 18.

(42) concludes this dissertation and gives future research directions. In order to make the following chapters self-contained, the interconnect models used in each chapter and some notations and definitions associated with the oscillation ring detection and diagnosis formulation are repeated in each chapter.. 19.

(43) Chapter 2 Preliminaries. This chapter gives the models of interconnect detection and diagnosis based on oscillation ring test scheme and the test architecture for system-level interconnects, crosstalk detectors for interconnect buses, synchronous sequential circuits based on the oscillation ring scheme, fundamentals of interconnect routing framework and technologies including the routing model and the cost function, the assumptions and limitations of our formulation, a brief survey on the related research in interconnect detection and diagnosis architectures and algorithms, previous work on both interconnect issues and oscillation test.. 2.1. Interconnect Models. 2.1.1. Interconnect Model for Detection. The interconnect detection model used in this thesis is shown in Figure 2.1. In order to simplify the problem of interconnect test, we represent the circuit interconnection by using an abstract hypergraph to represent the SoC circuit in Figure 2.1 (a) and a hypernet to represent a multiple-terminal signal net in Figure 2.1 (b). We define the terminology formally in Chapter 4.4.1. However, this hypernet graph model is not good enough for interconnect detection problem. It is obvious that the two branches of N1 in Figure 2.1 (a) should belong to two different rings, and they cannot be tested simultaneously. Therefore, we consider each branch of a hypernet. 20.

(44) individually, and decompose each branch of a hypernet to a 2-pin net. For example, nets N11 and N12 in Figure 2.1(c) are two 2-pin nets for hypernet net N1 in Figure 2.1 (b). Without loss of generality, an n-terminal hypernet is thus broken into (n–1) 2-pin nets as shown in Figure 2.1 (c), and transform our interconnect detection problem into edge-covering problem by using the 2-pin net graph modeling. Signal path C1 Scan path N1 N3 N2 C3. C2. (a) Hypernet C1 Scan path N1 N3 N2 C3. C2. (b) Interconnect C1 Scan path N3. N11. N12 N2. C2. C3. (c) Figure 2.1 (a) The interconnect diagram for SoC, (b) hypernet graph, (c) interconnect graph model with 2-pin nets for detection. 21.

(45) For our graph modeling of interconnect test, we have a normal graph G = (V, E), where E is the set of 2-pin nets. There are two rings in Figure 2.1 (c): R1 = {N11, N3}, R2 = {N12, N2, N3}. A complete test for stuck-at faults and open faults for all interconnections is thus reduced to a problem of finding a set of rings that cover all edges corresponding to interconnection structure in the graph G. A minimum test is thus the set of rings with minimum cardinality. To model the delay fault, we use a weighted graph G = (V, E) consisting of a vertex set V and an edge set E. In E, each edge, ei ∈ E, is an ordered pair (u, v), where u, v∈ V, and has a weight wi.. For the delay fault testing, signal delay on each. net along the ring is considered. To deal with the delay fault, a weight wi, which is the timing specification, on a 2-pin net ei by a 2-tuple wi = (li, ui), where li and ui are lower and upper bound on the distribution of normal path delay respectively, is defined in Figure 2.2.. C1. (l3, u3). (l11, u11). (l12, u12). (l2, u2) C2. C3. Figure 2.2 Graph model for delay faults.. 2.1.2. Interconnect Model for Diagnosis. For interconnect diagnosis problem, our proposed oscillation ring test scheme. 22.

(46) can also be used for interconnect diagnosis, the process of locating the exact fault site in interconnects. However, the two-pin net model for hypernets is not sufficient for diagnosis. Therefore, the interconnect structure is transformed into a diagnosis graph model as follows. The scan path and wrapper cells in a core are lumped into a single terminal node, as we assume that they are fault-free. The fanout points of a hypernet form dummy intermediate nodes, and a wire segment connecting two nodes is an edge. For example, the diagnosis graph model for the hypernet of Figure 2.3 (a) is shown in Figure 2.3 (b), in which the white node is a terminal node and gray nodes are intermediate nodes. An edge is the smallest unit of a wire segment that can be uniquely diagnosed. In Figure 2.3 (b), any stem affects all the downstream nodes and edges. If edge e1 is faulty, all three rings will not oscillate correctly. A faulty e3 affects rings 2 and 3, while faults on edges e2, e4, and e5 affect rings 1, 2, and 3, respectively. For diagnosis purpose, all these five segments are different. For a test set, our goal is to diagnose the single fault in any edge in the interconnect diagnosis model, and thus the optimal diagnosis resolution is achieved.. Ring 2 e1 Ring 1. e1. e3 e4. e2. Ring 3 e5. e2. e3 e4. (a). e5. (b). Figure 2.3 (a) a multiple-sink hypernet, and (b) an interconnect diagnosis graph model.. 23.

(47) 2.2. Oscillation Ring Test Methodology In this subsection, we will give a overall view of our proposed oscillation ring. test scheme (OR) including test architecture & operations, effectiveness, IEEE 1500 compliant wrapper cell design and finally delay measurement formula. As to the details, please refer to Chapter 4.. 2.2.1. Oscillation Ring Test Architecture & Operations. In this subsection, we propose the architecture for the oscillation ring test for interconnects as shown in Figure 2.4. Figure 2.4 shows the proposed architecture, where C’s are circuit cores implemented with boundary scan cells and a local counter, which is to capture the induced glitches for crosstalk fault detection and to measure delays of oscillation rings for delay measurement. For this architecture, oscillation ring(s) will be formed as shown during the testing mode. If the formed oscillation ring fails to oscillate, it implies that there exists stuck-at or open fault(s) in components of the oscillation ring. If there is a crosstalk fault between a victim interconnect line and the oscillation ring interconnect lines, glitches will be induced on the victim interconnect line. Figure 2.4 shows the oscillation signal at the oscillation ring and the induced glitches at the victim interconnect line. These induced glitches will be captured by the local counter of the core and be shifted out for observation. To test the delay fault, the delay of the oscillation ring will be measured through using the local counter and the central counter of TAM of the SOC. At this time, the central counter is enabled by signal OscTest and triggered by the system clock, and a local counter is connected to one wrapper cell of the oscillation ring so that the oscillation signal is fed to the local counter. When the oscillation test session starts (OscTest = 1), the. 24.

(48) central counter as well as all local counters in cores are enabled. After the counter in TAM counts to a specific number n, the oscillation test session terminates and all local counters are disabled (OscTest = 0). The counter contents are shifted out to an ATE for inspection. Assume that the frequency of the system clock to be f and the local counter content of the ring to be ni. The ring’s oscillation frequency, fi, is: fi = f × ni / n. (2.1). According to the timing specification, for a good oscillation ring connected by interconnect lines and boundary scan cells, fmin ≤ fi ≤ fmax. That is: nmin ≤ ni ≤ nmax.. SOC TAM. System clock Central counter. …. …. …. C1. C2 …. b1. Core counter for delay detection. …. a2. a1 …. …. C4. C3. …. …. b2. Oscillation Ring. Core counter for glitch detection. Figure 2.4 Test architecture of system-level interconnect test for SoC ICs.. 25.

(49) 2.2.2 2.2.2.1. Effectiveness of Oscillation Ring Test Scheme Effectiveness for Delay Fault. The simulation results are shown in Figure 2.5, where Figure 2.5(a) shows the oscillation signal of the longest ring; and Figure 2.5(b) shows the oscillation signal of the shortest rings. The cycle time of the longest rings (with nine interconnects) is about 38ns and that of the shortest rings is about 2.8ns. Thus, the oscillating frequency ranges from 26 MHz to 357 MHz, and this shows that this oscillation detection scheme is feasible.. (a). (b) Figure 2.5 Simulated waveforms of the longest (a) and shortest rings (b) of benchmark circuit hp.. 26.

(50) 2.2.2.2. Effectiveness for Crosstalk Faults. In order to verify that the proposed architecture can be applied to detect crosstalk-induced glitches, we conduct HSPICE simulation with TSMC 0.18μm technology. An oscillation signal is generated on a ring as shown in Figure 2.4, and a 1 mm wire with three times of normal coupling capacitance is assumed. The results are shown in Figures 2.6 and 2.7. Figure 2.6 shows the oscillation signal on the ring, the induced glitches on the victim net, and the output of the counter. The crosstalk-induced glitch shown in Figure 2.6 can be detected and verified since the counter changes the state on every positive glitch.. Oscillation Signal. Counter output. Glitches on victim net. Figure 2.6. Oscillation signal on the ring, induced glitches on the victim net, and counter output.. 27.

(51) Oscillation Signal. Detector output. After 5 wrapper cells. glitch. Counter output. Figure 2.7. Illustration on how the glitches are detected, an oscillation signal (top), the resulting crosstalk-induced glitch, the detector output, and the signal after 5 wrapper cells (middle), the counter output with the verified state change (bottom).. Figure 2.7 gives an illustration on how to detect the glitches. The oscillation signal is shown in top of Figure 2.7, and the induced positive glitch, whose peak value is about 0.8V, is shown in the middle set of figures. This glitch is amplified by a detector, which is a specially designed inverter in our P1500-compliant input wrapper cell. We may adjust the W/L ratio of the detector’s transistors to determine the. 28.