Oscillation Ring Construction: Model and Analysis

To apply the OR testing to an SOC with many cores connected with interconnect lines, it needs to form oscillation rings which can cover all interconnects in order to completely test all interconnects of the SOC. In the two sections which follow, we will present the model and analysis and the algorithm to construct oscillation rings respectively.

As mentioned previously, the proposed methodology is targeted for SOC with IEEE Std. 1500. A more detailed example of the test mechanism is illustrated in Figure 4.4, where there are three cores, C1, C2, and C3. All pins in a core are connected into a scan path during the test mode, which is indicated by the broken line in Figure 4.4(a). Oscillation rings can be constructed with the help of scan paths provided by wrapper cells. The interconnect wires connecting cores are also shown by heavy lines in Figure 4.4(a), where an arrow indicates the direction of signal transmission. There are three nets in the figure, in which net N1 connects three terminals (pins), while N₂ and N₃ connect two pins each. Only the heavy lines are the target of interconnect test.

For example, there are two rings in Figure 4.4. The first ring consists of nets N1

(and its right-hand side branch), N₂, and N₃, and it passes all three cores. The second ring consists of N1 (and its left-hand side branch) and N3, and scan paths in C1 and C3. In order to make the signal on a ring oscillate, we must ensure that the number of inversions on a ring is odd, and this includes the inversions on wire segments as well as those in wrapper cells.

C3 C2

Figure 4.4 (a) The interconnect diagram, (b) hypernet graph, (c) graph model with 2-pin nets. (Also same as Figure 2.1)

4.4.1 Graph Model for Oscillation Ring Tests

In order to simplify the problem under investigation, we represent the circuit interconnection by using an abstract hypergraph.

Definition 1: A hypergraph G’ = (V, L) consists of a vertex set V and an edge set L, which consists of multi-terminal edges connecting a set of vertices Vi ⊆ V and | Vi | ≥ 2. Such an edge is referred to as a hypernet.

For example, N₁ in Figure 4.4(b) is a hypernet. Furthermore, we assume that in an n-terminal hypernet, one terminal is the source node (i.e., sending signal) while the others n–1 are the sink nodes (i.e., receiving signals).

The circuit structure of an SOC can be directly transformed into a hypergraph, in which each pin is a vertex while each signal net is a hypernet. However, this graph model is not good enough for our problem. Consider net N1 in Figure 4.4(a) again. It is obvious that the two branches of N₁ should belong to two different rings, and they cannot be tested simultaneously. Therefore, it would be better to consider each branch of a hypernet individually or separately instead of treating them all as a whole. Each branch of a hypernet is thus a 2-pin net. For example, nets N₁₁ and N₁₂ in Figure 4.4(c) are two 2-pin nets, which correspond to hypernet net N1 in Figure 4.4(b), and each 2-pin net connects the source vertex to one of its sink vertices. An n-terminal hypernet is thus broken into (n–1) 2-pin nets. The result is a normal graph G = (V, E), where E is the set of 2-pin nets. There are two rings in Figure 4.4(c): R1 = {N11, N3}, R2 = {N12, N₂, N₃}.

Definition 2: A weighted graph G = (V, E) consists of a vertex set V and an edge set E, in which each edge, e_i ∈ E, is an ordered pair (u, v), where u, v∈ V, and has a weight w_i.

A complete test for stuck-at faults and open faults for all interconnections is thus reduced to a problem of finding a set of rings that cover all edges corresponding to interconnection structure in the graph G. This is equivalent to find a set of sub-circuits (rings) R = {G₁, G₂, …, G_n}, such that:

z ∀G_i, G_i ⊆G , Gi = (Vi, Ei), Gi is a ring.

z

U

A minimum test is thus the set of rings with minimum cardinality.

For the delay fault testing, signal delay on each net along the ring is considered.

To deal with the delay fault, a weight w_i, which is the timing specification, on a 2-pin net ei by a 2-tuple wi = (li, ui), where li and ui are lower and upper bound on the distribution of normal path delay respectively, is defined. The graph model for Figure 4.4(c) with aforementioned weights is shown in Figure 4.5.

Let ti be the actual propagation delay on net ei, and the variance of delay on net ei

be δi = ui – li. The following lemma gives a sufficient condition under which the delay fault t_i is detectable by applying oscillation test.

Lemma 1: Consider a ring of n edges, e1, e2, …, e_n. The delay fault on edge e_i, 1 ≤ i ≤ n, is detectable if the following condition holds:

∑∈{ }−

≥

− i j 1..n {i} j

i u

t δ (3)

Proof: In a fault-free circuit, the maximum delay in a ring will be the summation of the upper bounds of individual nets. A large delay t_i will not be masked if:

{ } ∑

∑∈ − ≥ =

+ _{j ..n i j} ⁿ_{j j}

i l u

t _{1 {} 1} (4)

Eq. (3) can be obtained by rearranging Eq. (4).

(l₃, u₃) C1

C₂ C₃

(l₁₁, u₁₁) (l₁₂, u₁₂) (l₂, u₂)

Figure 4.5 Graph model for delay faults. (Also same as Figure 2.2)

From Lemma 1, it can be seen that a delay fault may be masked when ti > ui but Eq . (3) is not satisfied. In order to reduce the probability of undetectable faults, we shall try to construct short rings, so that the accumulation of delay variance will not mask delay faults.

4.4.2 Analysis of Rings and Test Cost

Test cost is dominated by test application time. In the case of oscillation ring test, the single factor affecting test application time is the number of rings required to cover all nets. The number of rings is closely related to interconnect structure. We can analyze it by using the hypernet model.

For a hypernet, at most one of its fanout branches can be tested at a time. The reason is that no two branches belong to the same ring, and any two rings containing the two branches under consideration share the stem of the hypernet before fanout point. If both rings are formed simultaneously, the two oscillation signals will interfere with each other. Therefore, at most one of the fanout branches can be tested at a time. This condition is illustrated in Figure 4.6.

. . .

Ring 1 Ring 2

Figure 4.6 Hypernet branches and rings.

Since two interconnect wires are connected by a scan path in a core, the positions of pins (i.e. relative position between input pin and output pin) in a core will also affect the interconnection structure. The following lemma explains why pin location will affect the number of rings.

Lemma 2: Any two 2-pin nets driven by adjacent pins of a core must belong to two