(lower voltage swing)
Fig. 2-6 Optimal load resistance determined by load-line analysis
The black color load-line is the optimal load resistance determined by load-line analysis. And the optimal load resistance value also equals “VMAX/IMAX”. It shows that the black color load-line has maximal output power under this voltage and current swing limitation. The red color load-line is the load resistance which is smaller than the optimal resistance. It will have the same current swing but smaller voltage swing and resultant smaller output power. The blue color load-line is the load resistance which is larger than the optimal resistance. It will have the same voltage swing but smaller current swing and resultant smaller output power.
Based on the figures and equations of load-line analysis above, the load-line analysis can be used for quickly determining optimal load resistance, but not reactance. That is, only the real part of the load impedance (ZL) can be determined by this analysis, the effect of imaginary part caused by the parasitic effect of the circuit will be completely neglected. Because the load-line analysis bases on I-V curve, the junction parasitic effect is exclusive. Unfortunately, when the signal is operated at high frequency, the parasitic effect induces lose. Besides, the larger size of the transistor it is, the parasitic effect is worse and cannot be ignored.
Considering the parasitic effect and comparing to the load-line analysis, the load-pull analysis can be used to determine the load impedance ZL, both real and imaginary part, of power amplifiers. The load-pull analysis is mainly to sweep ZL to see how PAs perform. The analysis procedures are：First, add a load tuner (ZL) at the output of power amplifier. Second, sweep the value of load tuner (ZL) to see the difference of output power (POUT) and power-added efficiency (PAE). Because of each point on Smith chart is a reflection coefficient, and the reflection coefficient and impedance are one-to-one mapping for 50 Ω characteristic impedance. When changing the value of load tuner (ZL), the swept data of the same output power and the same PAE was recorded. The swept data can be used to construct constant POUT and constant PAE contours. Third, choose one reflection coefficient (load impedance) on Smith chart by trade-off between constant POUT and constant PAE contours. Using load-pull analysis to determine ZL has several advantages. Because the constant POUT
and PAE contours are drawn on the same Smith chart, it is easy and obvious to trade-off between them. Besides, because of the one-to-one mapping characteristic, both real and imaginary part of ZL can be determined as soon as the trade-off point has been chosen.
Another difficulty for designing power amplifier is the parasitic effect. Because high output power is required, a large size of each transistor and resultant seriously parasitic effect are inevitable. Large parasitic Cgd provides a short path between input and output at high frequency in common-source amplifier. Therefore, a resonated inductor (Lgd) must be added between these two nodes shown in Fig. 2-7 for resonating parasitic Cgd for stability consideration.
Fig. 2-7 Neutralization for resonating parasitic Cgd
The small-signal model for a common-source amplifier is shown in Fig. 2-8.
Because the S-parameter S12 is desired, input phasor E2 is placed at port 2 (drain).
Fig. 2-8 Small-signal model of common-source transistor
According to the definition of S12 shown in (2.4) [16], the term “VO1/E2” can be expressed by (2.5). Although equations (2.4) and (2.5) can show the effect for value of ZX, it is not obvious. In order to further simplify this equation, the matched condition at output node is assumed. This condition is always true for RF systems. The S22 of common-source amplifier can be calculated through (2.6) to (2.7). α and β are the substituted variables for the numerator and denominator in (2.6), respectively. Under the matched condition, the condition “ZO2β=α” can be derived as shown in (2.8). Thus the equation (2.5) can be further simplified by this derived condition and the final result for S12 of common-source amplifier is shown in (2.9).
For a traditional common-source amplifier, ZX is “1/jωCgd” and S12 will become the equation in (2.10). Thus larger the transistor size it is, larger the value of parasitic
Cgd it has and worse the reverse isolation it becomes. For extremely case of infinitely large Cgd value, the S12 will become the equation shown in (2.11) and equal to 1 (or 0 dB) in general for RF circuits (for ZO1 = ZO2 = ZO = 50 ohm, general case in RF circuits). 0-dB S12 means this circuit has no any reverse isolation or the equivalent circuit for this two-port network is short circuit. It is reasonable because the infinitely large Cgd provides a zero-impedance short path between port-1 and port-2.
If the resonated inductor Lgd is adopted and placed between gate-drain, the impedance ZX in (2.9) will become (2.12). Thus S12 can be zero as long as the condition in (2.13) is achieved. That is the reason why a resonated inductor is always adopted for large-sized common-source amplifier.
O 2 O 1
(((( ))))
capacitor, Cb, comes from the consideration during measurement. The cable inherent resistance between probe and DC power supply is around 3 Ω. It’s not a serious issue for small-signal systems such as receiver front-end. However, for hundreds milli-ampere transmitter front-end, it may cause milli-volt or even several volts drop during measurement. Because such voltage drop may downgrade internal biasing points by different levels, DC current may be sunk into unexpected path when measurement. In order to avoid this phenomenon, a capacitor must be added to block DC current from stage to stage.Fig. 2-9 is the equivalent network between gate-drain of common-source transistor. If Cb is an ideal blocking capacitor (infinite large), parasitic Cgd can be resonated by Lgd at desired frequency to increase reverse isolation. However, the effective value of inductor (L’gd in Fig. 2-10) is slightly smaller than Lgd. It will slightly shift the resonant frequency caused by L’gd and parasitic Cgd. This problem can be corrected by fine tuning the value of Lgd [10].
Fig. 2-9 Equivalent network between gate-drain of common-source transistor
Fig. 2-10 Equivalent network between gate-drain of common-source transistor (L’gd is the combination of Lgd and Cb)
By (2.2)–(2.3), the transistors’ dimensions and optimal load resistance can be roughly predicted by hand calculation. Because the biasing is fixed to VDD, the variable for transistor itself is size. And the operation mode is class E, the gate biasing is also fixed to the transistor threshold voltage. The transistor’s size is also determined by the required output power. In order to determine the transistor’s size, some analysis steps
operates at ideal case which means that the transistor turn-on resistance ideally equals zero. According to the assumption, some initial design steps can be provided. But because of the assumption, these initial design steps are not suited to design the circuits. These initial design steps can only determine some initial circuit parameters.
Therefore, the transistor turn-on resistance should be considered and the modified design steps could be provided. These design steps are shown below. The load network of ideal case class E power amplifier is shown in Fig. 2-11.
Fig. 2-11 The load network of ideal case class E power amplifier
At first, the output node Vo is described in (2.14). And we get Io in (2.15). The voltage of the shunt capacitor Vc can be calculated through (2.16) to (2.18). In order to get c1, we use the Fourier integral as shown in (2.19) and (2.20). Equation (2.21) and (2.22) show the results of the Fourier integral. Because RF choke has no voltage drop, the average voltage of Vc is Vcc. Therefore we can get equation (2.23). By the equation (2.23), we can define the equal load resistance RDC measured from the power supply. According to this, the output AC power can be shown in (2.24). The overall drain efficiency η also can be shown in (2.25). The amplitude A of output waveform equals a constant c.
( ) t [cos( ) cos ], B (2.18) equation (2.26) and (2.27). We can get (2.28) from (2.26) and (2.29) from (2.27). So the φ equals -32.4820 or -0.5669 rad. Because the ideal drain efficiency of class E power amplifier η is 100 %, we can get a group of initial design values through (2.30) to (2.36).
L network of Ron case class E power amplifier is shown in Fig. 2-12.
Fig. 2-12 The load network of Ron case class E power amplifier
At first, the output node Vo also can be described in (2.37). Therefore we get Io in (2.38). So the node V1 can be described in (2.39). Because the transistor has the on state and off state, the voltage of the shunt capacitor Vc can be calculated in two equations (2.40) and (2.41). According to the two boundary equations (2.42) and (2.43), we can get (2.44). The amplitude A of output waveform equals a constant c.
( ) sin( ) (2.37)
1 1 1
Next, we also use the Fourier integral to get c1 which is described through (2.45) to (2.48). For high efficiency of class E power amplifier, Vc(θ=π) equals zero at the instant that the transistor turns on as shown in (2.49). Therefore we can get equations (2.50) and (2.51). For high efficiency of class E power amplifier, dVc(θ)/dθ at θ=π equals zero. As a result, we can get equation (2.52). And the average voltage of
Vc(θ) equals Vcc’, equation (2.53) can be obtained. According to (2.53), we can define
1 1 parasitic effect. Third, we can figure out the initial design parameters from ideal case.
Fourth, we can use equations (2.50) to (2.52) to get an initial design parameter φinitial. Fifth, according to this design parameter φinitial value, we can get some other design parameter such as φ and ρ. Sixth, we can define an error value ε between the left and the right of the identically equal equation form our calculate process. Seventh, we can set up the error ε tolerate value. The set up error ε tolerate value which we define is ε0. The error ε tolerate value ε0 is as small as possible. Eighth, if the absolute value of ε is smaller or equal than ε0 , the design parameter B and φ are got with the designed parameters such as R, Ron, and f. If the absolute value of ε is larger than ε0, it describes
that the iteration is not convergence. According to this, the iteration should be continued until the iteration is convergence. Ninth, in accordance with every Ron, we can build up a design table. Tenth, we can design a matching network to transform the 50 Ω terminal to Ron. Eleventh, because of parasitic resistance of tank circuit, it will produce appended power loss. And the quality factor of the tank is defined as Qtank. And the quality factor of the load R of the LC tank is defined as loaded-Q, QL. When the Qtank increases, the power loss decreases. Therefore, the quality factor of inductor must be high enough. And the bandwidth of the class E PA is depended on the QL. At the same time, the Ltank and Ctank are resonated at operating frequency. Twelfth, to consider the MOS drain capacitor Cj, there are two ways to design our circuit. If the shunt-to-ground capacitor Cshunt is larger than Cj, we must shunt capacitor at the drain terminal of MOS to compensate. If the shunt-to-ground capacitor Cshunt is smaller than Cj, we must shunt inductor at the drain terminal of MOS to compensate. Thirteenth, we merge all the components and achieve final class E PA.
Shown in Fig. 2-13 is the designed power amplifier. The proposed PA consists of two push-pull amplifiers to amplify the signal which comes from the voltage-controlled oscillator.
By (2.2)-(2.3), the transistors’ dimensions and optimal load resistance can be roughly predicted by hand calculation. Because the biasing is fixed to threshold voltage and VDD, the variable for transistor itself is size. The transistor’s size of class E power amplifier is determined by the required output power.
Two on-chip inductors, Ld1 and Ld2, are used to resonate out the parasitic capacitance of the drain (that is, node B1 and B2) and to bias the drain DC voltage to VDD. Because of large size transistors and resultant seriously parasitic capacitance, two on-chip inductors, Lgd1 and Lgd2, are used to resonate out the gate-drain parasitic capacitance Cgd,Mpa1 and Cgd,Mpa2 of transistors Mpa1 and Mpa2, respectively.
The inductors Ld1 and Ld2, which are used for resonating parasitic capacitance of the internal nodes of power amplifier (B1 and B2), are determined and simulated with core circuit of power amplifier during the load-pull analysis. When the inductors Ld1
and Ld2 are modified, the output impedance transformation network which is determined by load-pull analysis will be affected. However, the chosen ZL and its corresponding transformation network are for previous circuit – core circuit of PA with non-modified inductors, load-pull analysis has to be simulated again for modified inductors. Therefore the load-pull analysis has to be simulated again as long as any part of circuit is modified; iterative simulations may be needed to determine the values of resonated inductors and output impedance transformation network. For iterative procedure, it is endless if it is not convergent. From this point of view, the better way is to increase reverse isolation so that these resonated inductors need no any modification when the output impedance transformation network is connected to the circuit. That is the reason why both two inductors (Lgd1 and Lgd2) are used between
gate-drain for both stages of PA.
Two capacitors, Cb1 and Cb2, are adopted to cut out unnecessary DC paths provided by Lgd1 and Lgd2. To consider the stability effect, the k and b stability factor are shown in Fig. 2-14 – 2-15. The stability factor (k factor) is described in (2.56).
And the stability means (b factor) is also described in (2.58). The output impedance transformation network is composed of Cshaping, Lshaping, Cm and the parasitic capacitance of the output pad Cpad.
0 5 10 15 20 25 30 35 40
Fig. 2-14 Stability factor (k factor)
0 5 10 15 20 25 30 35 40
2 2 2
1 11 22
(2.56) 2 12 21
S S
k S S
− − + ∆
=
11 22 12 21 (2.57)
S S S S
∆ = −
2 2 2
1 11 - S22 - (2.58)
b= + S ∆
In order to minimize chip area, internal nodes such as PA’s input (connected to VCO) are not implemented any matching networks. Instead, shunt inductors are adopted to resonate out the parasitic capacitance of these nodes. Because any parasitic capacitance is equivalent as a short path for high frequency, it may degrade RF signal by leakage RF signal to ground. The output node, however, is connected to external 50-Ω impedance probe during measurement. Therefore, output transformation network is needed and implemented by load-pull analysis. Fig. 2-16 is the constant Pout, constant PAE contours and the chosen ZL by trade-off between them. Fig. 2-17 is the impedance transformation network, which transfers 50-Ω port to chosen ZL
determined by the load-pull analysis. The transferred load impedance seen by power amplifier is shown in Fig. 2-18.
Fig. 2-16 Constant Pout, constant PAE contours and the chosen ZL
Fig. 2-17 Impedance transformation network of power amplifier
Fig. 2-18 Load impedance transferred by transformation network
2.2.2. Voltage-Controlled Oscillator with Cascode Buffer
We can design a voltage-controlled oscillator as a voltage source of class E power amplifier. There are several ways to build a VCO. In research work, we adopt the LC tank VCO which has the best normalized phase noise compared to other fully integrated structures like ring oscillators, relaxation oscillators, and gm-C oscillators.
In other words, this architecture has the lowest phase noise for a given amount of power. The various VCO constructed by modern CMOS technology are also reported.
Due to the lack of high Q elements in the conventional CMOS technology, the differential oscillator feature is the mostly often-used configuration.
LC-tank voltage-controlled oscillators are designed in NMOS cross-coupled pair with an inductor L in parallel with a capacitor C resonates at a center frequency and a PMOS current source. The design of LC-tank VCO is shown in Fig. 2-19.