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2.3. Post-Simulation Results
The K-Band integrated transmitter circuits are designed in 0.13-µm 1P8M CMOS technology. And the TSMC 1.2 V NMOS with DNW components are used.
From the supply voltage of 1.2 V, the current consumption of the LC tank voltage-controlled oscillator, cascode buffer and class E PA are 4.8 mA, 7.97 mA and 25.91 mA, respectively. The total power dissipation is 46.42 mW.
With and without neutralization technique analysis, neutralization technique phase shift, neutralization technique phase shift effect, drain voltage and current waveforms, large signal S-parameter (LSSP), output power (Pout) and PAE versus input power (Pin) of re-matching stand-alone class E power amplifier presented by post-simulation are illustrated in Fig. 2-24, Fig. 2-25, Fig. 2-26, Fig. 2-27, Fig. 2-28, and Fig. 2-29, respectively. As shown in Fig. 2-24, the S12 of re-matching stand-alone class E power amplifier presented by post-simulation with neutralization technique analysis at 25 GHz equals -23.6 dB which has better performance than the S12 which equals -7.8 dB of that without neutralization technique analysis. Therefore, the neutralization technique can improve the reverse isolation of class E power amplifier.
As shown in Fig. 2-25, we can find that the neutralization technique phase shift (fundamental tone 25 GHz) equals 1.9 degree. As shown in Fig. 2-26, the 1.9 degree neutralization technique phase shift can improve PAE (7.49 %) and output power (0.72 dB). As shown in Fig. 2-27, we can find that it still has overlapping waveform and DC power consumption. The overlapping waveform is formed by the parasitic effect which can provide phase shift on the drain voltage and current waveforms. And the DC power consumption is formed by the turn-on resistance effect which can provide a DC voltage on the drain voltage waveform. Meanwhile, the switch waveform is not a square-wave because that the input signal comes from VCO. Due to turn-on resistance and parasitic effect, the ZVS and ZDS points are not exactly on
the point when the switch turns on. And the peak voltage value is about 1.81 Vdd. The terminal at the same time. Because the class E PA operates in large signal, the S21 has positive gain. Because of the load-pull analysis, the S22 will not be matched to 50 ohm terminal. “Pout versus Pin”, “PAE versus Pin” and “Drain Efficiency versus Pin” curves in Fig. 2-29 show this power amplifier has variable power gain because class E power amplifier is a kind of nonlinear power amplifier. The maximum PAE is 38.67
% at the input power of 4 dBm and output power of 10.49 dBm.
Fig. 2-24 With and without neutralization technique analysis of re-matching stand-alone class E power amplifier
0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 -200
-175 -150 -125 -100 -75 -50 -25 0 25 50 75 100 125 150 175 200
Phase (degree)
Frequency (GHz)
Gate Waveform Drain Waveform
Fig. 2-25 Neutralization technique phase shift of re-matching stand-alone class E power amplifier
Fig. 2-26 Neutralization technique phase shift effect w/i neutralization
w/o neutralization
Fig. 2-27 Drain voltage and current waveforms with gate voltage waveform of re-matching stand-alone class E power amplifier
0 5 10 15 20 25 30 35 40
Fig. 2-28 Large signal S-parameter (LSSP) for re-matching stand-alone class E power amplifier
0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0
-30 -25 -20 -15 -10 -5 0 5 10 15
Fig. 2-30–Fig. 2-31 show the post-simulation performance of voltage-controlled oscillator and cascode buffer with the loading equaled to the PA’s input impedance.
Fig. 2-30 is the tuning range of voltage-controlled oscillator. When the tuning voltage changes from 0 V to 1.2 V, the frequency changes from 23.99 GHz to 24.79 GHz. Therefore, the tuning range of voltage-controlled oscillator is 0.8 GHz.
Fig. 2-31 is the phase noise of voltage-controlled oscillator. From this figure, it’s obvious that the chosen bypass capacitor Cc and PMOS current source can improve the phase noise of voltage-controlled oscillator. Therefore, the phase noise of voltage-controlled oscillator is -117 dBc at 10 MHz.
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
Fig. 2-30 Tuning range of voltage-controlled oscillator
1000 10000 100000 1000000 1E7 1E8
-120
The post-simulation results for whole circuits are shown in Fig. 2-32–2-34. Fig.
2-32–2-33 illustrate the output power and overall drain efficiency versus tuning voltage. As Fig. 2-32 shown, it is obvious that the output power is all about 10 dBm when the tuning voltage changes from 0 V to 1.2 V. As Fig. 2-33 shown, it is obvious that the overall drain efficiency is all about 20 % when the tuning voltage changes from 0 V to 1.2 V. The DC power consumption mentioned in Fig. 2-33 is included with the DC power consumption of whole circuits not only class E power amplifier.
Fig. 2-34 shows the output power spectrum for whole circuits. As Fig. 2-34 shown, it has about 50 dB harmonic rejection capability. Due to the differential architecture, it has a good harmonic rejection capability.
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 4
5 6 7 8 9 10 11 12 13 14
Output Power (dBm)
Tuning Voltage (V)
Fig. 2-32 Pout vs Vtune for whole circuits
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 16
17 18 19 20 21 22 23 24
OverallDrain Efficiency (%)
Tuning Voltage (V)
Fig. 2-33 Overall drain Efficiency vs Vtune for whole circuits
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 -60
-50 -40 -30 -20 -10 0 10 20
Output Power (dBm)
Frequency (GHz)
~ 50 dB
Fig. 2-35 shows the post-simulation results for the cascode buffer with power amplifier. “Pout versus Pin”, “PAE versus Pin” and “Drain Efficiency versus Pin” curves are shown in Fig. 2-35. The maximum PAE is 21.25 % at the input power of 0 dBm and output power of 9.73 dBm. It is because that the input of cascode buffer is off-chip Bias-Tee and the DC power consumption is included with the DC power consumption of cascode buffer not only class E power amplifier.
Table 2-3 and Table 2-4 give the performance summaries of voltage-controlled oscillator, power amplifier, and integrated whole circuits.
-30 -25 -20 -15 -10 -5 0 5 10 15
Table 2-3 Summaries of original post-sim results1
Post-Sim (Original)
Technology 0.13-µm CMOS
Supply Voltage (V) 1.2
RF (GHz) 25
Voltage-Controlled Oscillator with Cascode Buffer
15.3
Class E Power Amplifier 31.1
Power (mW)
Total 46.4
Table 2-4 Summaries of original post-sim results2
Post-sim (Original) Spec.
Tuning Range (GHz) 0.8 -
VCO
Phase Noise @ 10 MHz (dBc) -117 -
Peak PAE (%) 38.67 -
Max. Pout (dBm) 10.49 >10
Power Amplifier
S11 / S22 (dB) –30.3 / –3.3 -
Tuning Range (GHz) 0.795 -
Phase Noise @ 10 MHz (dBc) -117 -
Max. Pout (dBm) 10.15 >10
Whole Circuits
Overall Drain Efficiency (%) 22.31 -
Cascode Buffer with Power Amplifier
Peak PAE (%) 21.25 -
Chapter 3
Experimental Results
The proposed K-band CMOS class E power amplifier integrated with voltage-controlled oscillator is designed and fabricated using TSMC 0.13-um CMOS process. This chapter presenting the chip layout, test environment, and experiment results. Measured performance is compared with post-simulation results and discussion which is made for further study.