Once ILP produces an optimal solution for a given CQG, certain operations should follow to further derive the optimal solution for the original QG. Then, we present two operations, edge split and path expansion, for this purpose.
Edge Split:
Assume an edge ed(wd, qd, cd) is a selected dominating edge and ek(wk, qk, ck) is ed’s removed Fig. 12 (a) The edge split operation. (b) The path expansion operation. (c) The solution
for original QG.
(b) (a)
(c)
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parallel edge. After applying ILP, qd is set large enough to ensure that (10) holds for every cycle C passing through ed in reverse direction. When putting ek back to CQG, qk must also be properly set to ensure that (10) still holds for any newly generated cycle C’ derived from C by just replacing ed with ek. It follows that (10) is guaranteed to hold for every such cycle C’ if the following inequality can be satisfied:
qk – ck qd – cd (or qk ck + qd – cd) (12) Therefore, minimal queue size of an edge removed by edge unification previously can be derived using (12). For example, in Fig. 12(a), queue size of the blue selected dominating edge (v1, v5) is set to 4 after ILP. After edge splitting, the minimal queue size of the lower red non-dominating edge is set to 1 + 4 – 3 = 2 by (12).
Path Expansion:
While recovering from a condensed edge ep regarding the condensable path p, (7) ensures that (10) automatically holds for any cycle C originally passing through ep in forward direction and now passing through p. Hence, a path expansion operation merely has to further ensure that (10) also holds for such cycle C but in reverse direction; and this can be done if the following constraint can be satisfied:
)
In general, the way for distributing q(ep) to those edges along p is not unique. However, the following proposed strategy must be adopted to guarantee minimal queue insertion. Let em E(p) be the edge with lowest burden factor along a condensable path p, i.e., b(em) b(e) for all e E(p), then q(e) of each edge e along p can be determined as:
If there are two or more edges with lowest burden factor, pick one arbitrary. It is apparent that using (14) for queue sizing can ensure that (13) always holds. Fig. 12(b) illustrates an
Fig. 13 Overall flow of the proposed method.
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example of path expansion. At last, as shown in Fig. 12(c), edge split and path expansion can be performed repeatedly until the complete optimal solution for the original QG is obtained.
At the end of this section, Fig. 13 summarizes the overall flow of our proposed method for minimal queue insertion. Unlike [34], [35], identifying strongly connected components (SCCs) is unnecessary here since the testcases are acylic.
The proposed approach has been implemented in C++/Linux environment. Since it is difficult for us to get a bunch of real-world systems, alternatively, we decide to randomly build a set of different-sized directed acyclic graphs (DAGs) as QGs for evaluation, which is similar to the approach used in the experimental setup of [35]. Furthermore, latency of every edge in a DAG (i.e., communication channel in a system) is also randomly assigned with an integer within the interval [1, L]; that is, the number of relay stations required inserting at each edge (channel) is within the range [0, L – 1]. All experiments are conducted on a workstation with an AMD 1.81GHz CPU and 2GB RAM. The package lp_solve is adopted when solving ILP [41].
Our first experiment is to verify whether the proposed compaction techniques are effective.
Johnson’s algorithm [42] is applied to identify all cycles in both the original QG and the minimal CQG. The experimental results shown in Table 5 clearly indicate that the proposed technique can successfully reduce the number of vertices and edges as well as achieve a remarkable reduction of cycle count. Before compaction, the cycle count for several test cases even exceeds one million, which makes ILP virtually impossible to find a feasible solution.
In our second experiment, we compare our proposed method with Collins’ heuristic method roposed in [35]. Table 6 and Table 7 report the results with L = 3 and 16, respectively. The results show that our proposed method can achieve an average reduction of 23% and 28% in queue size
Table 5 Experimental results of cycle reduction.
Case Name Original QG Minimal CQG
(V, E) #Cycles (V, E) #Cycles
Testcase1 (11,15) 55 (8,11) 12
Testcase2 (17,21) 51 (13,17) 14
Testcase3 (45,61) 30540 (20,35) 10123
Testcase4 (58,76) 48590 (39,45) 10497
Testcase5 (104,121) 42435 (56,73) 19754
Testcase6 (126,172) > 1Million (77,98) 132415 Testcase7 (175,201) > 1Million (66,84) 15423 Testcase8 (297,318) > 1Million (116,142) 23862
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for L = 3 and 16 respectively as compared to Collins’ method. The results also imply that the improvement can slightly increase as fabrication process keeps scaling (i.e., L increases).
Meanwhile, our method needs about 58% more runtime than Collins’ on average. However, it should be acceptable since all test cases can be completed within 24 minutes. Table 2 also shows that ILP fails in several test cases (denoted as ‘*’) if it directly applies to QG instead of minimal CQG. The reason is obvious that the size of the constraint set is too large at QG level. It is also worth to mention that several test cases contain hundreds of vertices and edges, which positively suggests our approach is capable of handling moderately large systems in practice.
四、 結論
First of all, the number of IICs has been reported to better model the global interconnect cost and then can be considered as a major QoR evaluation metric at early design stages in DRFM. In this project, we propose a resource-constrained synthesis algorithm for IIC minimization. The iterative binding-then-rescheduling procedure is first utilized for island assignment. A better island binding result can be expected because the solution search space is significantly expanded through rescheduling. The proposed algorithm also incorporates the consideration of read port restriction into scheduling and binding procedures to minimize the potential access conflicts. A post-processing procedure is then conducted to eliminate all remaining access conflicts.
The experimental results indicate that the proposed algorithm reduces the number of IICs by 21.0% ~ 24.7% on average as compared to the prior art. While adopting the read port restriction,
Table 6 Experimental results with L=3.
L L=3
Case Name
Proposed Method Collins’ Method [12] ILP directly to QG
#Queues Run-
time #Queues Run-
time #Queues Run- time
Testcase1 20 0 20 0 20 1
Testcase2 9 0 9 0 9 0
Testcase3 51 5 80 4 51 14
Testcase4 43 14 46 13 43 44
Testcase5 29 40 78 27 29 340
Testcase6 77 867 90 542 * *
Testcase7 84 32 90 23 * *
Testcase8 114 73 141 47 * *
Ratio 0.77 1.57 1 1 - -
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the proposed method also outperforms the previous work by about 12% in terms of average latency. As a result, the proposed algorithm should be regarded as a better alternative while performing architectural synthesis targeting DRFM.
Furthermore, a throughput optimization technique for LIS with minimal queue size is presented. First, an LIS is transformed as a newly proposed quantitative graph; next, the size of QG can be minimized through the developed compaction operations; ILP then follows to get an exact solution of minimal queue size, which can further be converted into an optimal solution for the original LIS. The experimental results demonstrate that our algorithm can achieve an average reduction of up to 28% in queue size as compared to the prior art. Moreover, the required runtime is merely about half an hour for a system with hundreds of cores. Consequently, we believe that the proposed technique is a better alternative to resolve the issue of queue sizing for moderately large systems in practice. The proposed algorithm can only handle acyclic systems at this moment. We are currently working on developing on improved version that can deal with cyclic systems as well.
Table 7 Experimental results with L=16.
L L=16
Case Name
Proposed Method Collins’ Method [12] ILP directly to QG
#Queues Run-
time #Queues Run-
time #Queues Run- time
Testcase1 68 1 68 0 68 1
Testcase2 76 0 77 0 76 0
Testcase3 290 9 437 6 290 19
Testcase4 291 31 351 19 291 52
Testcase5 256 77 386 48 256 459
Testcase6 519 1438 793 913 * *
Testcase7 673 69 753 40 * *
Testcase8 641 131 1035 83 * *
Ratio 0.72 1.58 1 1 - -
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六、 成果自評
在學術論文發表方面, 在今年度我們發表了以下國際會議期刊：
1. Che-Hua Shih, Ya-Ching Yang, Chia-Chih Yen, Juinn-Dar Huang, and Jing-Yang Jou,
“FSM-Based Formal Compliance Verification of Interface Protocols,” Journal of Information Science and Engineering, vol. 26, no. 5, pp. 1601–1617, Sep. 2010.
2. Juinn-Dar Huang, Chia-I Chen, Yen-Ting Lin, and Wan-Lin Hsu, “Communication synthesis for interconnect minimization targeting distributed register-file microarchitecture,” IEICE Trans. on Fundamentals, vol. E94-A, no. 4, pp. 1151–1155, Apr. 2011.
3. Juinn-Dar Huang, Chia-I Chen, Wan-Ling Hsu, Yen-Ting Lin, and Jing-Yang Jou,
“Performance-driven architectural synthesis for distributed register-file microarchitecture with inter-island delay,” IEICE Trans. on Fundamentals, to appear.
及以下國際會議論文：
1. Ya-Shih Huang and Juinn-Dar Huang, “Throughput-Driven Hierarchical Placement for Two-Dimensional Regular Multicycle Communication Architecture,” Asia Symposium on Quality Electronic Design, pp. 134–139, Aug. 2010.
2. Juinn-Dar Huang, Chia-I Chen, Wan-Ling Hsu, Yen-Ting Lin, and Jing-Yang Jou,
“Inter-Island Delay Aware Communication Synthesis for Island-Based Distributed Register Architecture,” Proc. of the 16th Workshop on Synthesis and System Integration of Mixed Information Technologies, pp. 58–63, Oct. 2010.
3. Juinn-Dar Huang, Yi-Hang Chen, and Ya-Chien Ho, “Quantitative Graph-Based Minimal Queue Sizing for Throughput Optimization in Latency-Insensitive Designs,” Proc. of the 16th Workshop on Synthesis and System Integration of Mixed Information Technologies, pp.
430–435, Oct. 2010.
4. Juinn-Dar Huang, Yi-Hang Chen, and Ya-Chien Ho, “Throughput Optimization for Latency-Insensitive System with Minimal Queue Insertion,” Proc. of IEEE Asia and South Pacific Design Automation Conference, pp.585–590, Jan. 2011.
5. Juinn-Dar Huang, Yi-Hang Chen, and Wan-Hsien Lin, “Performance-Optimal Behavioral Synthesis with Degenerable Compound Functional Units,” Proc. of IEEE International Symposium on VLSI Design, Automation, and Test, pp. 337–340, Apr. 2011. (Best Paper Candidate)
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在專利方面，通過以下國內外專利：
1. 黃俊達，林步青，李耿維，周景揚，“精細頻寬調控的仲裁器及其仲裁方法＂ 中華民 國專利案號 I332615，2010 年 11 月 1 日。
2. Juinn-Dar Huang and Chia-I Chen, “Dynamical sequentially-controlled low-power multiplexer device,” US 7881241 B2, Feb. 2011.
3. 黃俊達，陳嘉怡，“低功率動態序向控制多工器＂ 中華民國專利案號 I342670，2011 年5 月 21 日。
並有以下專利正在申請中：
1. 黃俊達、呂智宏、林步青、周景揚，“應用於查找表式 FPGA 的壓縮樹延遲最佳化”。
2. 黃俊達、王毓翔、林步青、周景揚，“可參數化管線式快速傳利葉轉換硬體產生器”。
3. 黃俊達、呂智宏、林步青、周景揚，Delay optimal compressor tree synthesis for LUT-based FPGAs
如果和我們當初在計劃提案中的預計的目標相比較，我們自評今年度計劃的完成度相 當不錯, 尤其在學術論文發表方面更有不錯的表現。(預期目標為發表一篇國際長篇期刊和 三篇國際會議論文）
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