3-3-1 The effects of various thermal treatments on the electrical performance of the gate stacks with ALD Al2O3 films deposited at 200 °C.
Figures 3-1~3 illustrate the electrical characteristics of the films with PDA 400
°C+PMA 400 °C, No PDA+PMA 400 °C, No PDA+PMA 500 °C, and No PDA+PMA 600 °C thermal treatments. The solid line located at about 1.1 V is labeled to indicate
the ideal flat band voltage (Vfb) in our cases. By comparing the first two cases − PDA 400 °C+PMA 400 °C and No PDA+PMA 400 °C, we preferred a PMA process rather than a PDA one which increased the gate leakage current severely and interface states somewhat. It also shows that increase of PMA temperature would eliminate the hump near conduction band in spite of the deviation of Vfb rising up with increase of annealing temperature. Fig. 3-3 (a) presents the trend of shift of Vfb against the thermal treatments. Vfb could be extracted while the measured capacitance is equal to the flat band capacitance defined as eq. 3.1;
acc
⎟⎟⎠ lower doped Ge substrte we used and lower CFB that always has a calculated value out of the range of measured C-V. So, we use eq. 3.2 instead of eq. 3.1 to estimate Vfb;
The dash line designates the position of ideal Vfb. There are two possible mechanisms to cause the Vfb shift up;
1- Negative fixed oxide charge (NFOC).
2- Electron trap (ET).
And, there are two possible mechanisms to cause the Vfb shift down;
1- Positive fixed oxide charge (PFOC).
2- Hole trap (HT).
Based on the trap analyses of the films deposited at various temperature with 60 cycles in Figs. 3-19 and 3-20, we could conclude that PDA 400 °C+PDA 400 °C would leaded to a lot of NFOC in comparison to No PDA+PDA 400 °C case. By combining with the results from chapter 2, we could find that more incorporation of Ge and GeO2 into the ALD films would build up many HT and more PFOC for severely destroyed film resulted from Ge out-diffusion through the vapor-like GeO while increasing the PMA temperature. Both those two mechanisms would lower down the value of Vfb. In addition, from Figs. 3-19 and 3-20, we could find that the ALD films are easily to trap electron disregarding what the deposition temperature you chose. Based on those discussed above, we could understand why the hysteresis has the behavior showed in Fig. 3-3 (b). Then, further taking consideration of the proper temperature range [40, 41, 42, 43] for activating the boron (B) doped P-N junction that will be discussed in chapter 4, we studied the effects of PMA 400 and 600 °C on those gate stacks with ALD dielectrics deposited at various temperatures.
3-3-2 The effects of various thermal treatments on the electrical performance of the gate stacks with ALD Al2O3 films deposited at R.T. (~ 50 °C), 100 °C, 200 °C, and 300°C.
Figures 3-4~5 show the essential C-V and I-V electrical performance. The I-V implies that the films deposited at 100 and 200 °C were robust to resist the thermal
stress while suffering to PMA 600 °C. For the film deposited at 50 °C, we considered that the increase of gate leakage current after annealing at 600 °C is due to the high
conc. of non-reacted CH3− bond incorporated (caused by less complete ALD reaction) into the film as leakage medium for carriers. For the film deposited at 300 °C, that is the contribution of higher Ge incorporation and interface roughness to such high gate leakage while suffering from PMA 600 °C thermal treatment. Fig. 3-6 implies that the hump near conduction band increased with deposition temperature and got eliminated while being annealed at 600 °C. By extracting Vfb and hysteresis in Fig. 3-7 and combining the results showed in Fig. 3-19~20 and chapter 2, we could boldly conclude that an unsound film deposited at 50 °C and high Ge-related compounds (Ge, GeOx, and GeO2) incorporated film deposited at 200 ~ 300 °C would produce many HT and NFOC, respectively. We could also find that the destroyed film suffered from Ge out-diffusion would cause many PFOC from the case of film deposited at 300
°C while being subjected to PMA 400 and 600 °C thermal treatments. Fig. 3-8 shows the relationship between Capacitance Equivalent Thickness (CET) and gate leakage current extracted at Vg = Vfb – 1.5 V along with the results on SiO2/Si gate stacks. The same color of the symbols represents the films subjected to one kind of thermal treatments and the same kind of symbols represents the films deposited at the same temperature. It shows that the dielectric constant of the films deposited at 100 or 300
°C can achieve 9.6 ~ 9.8 while suffering from PMA 600 °C thermal treatment. For that of the film deposited at 200 °C, we could only receive a film with dielectric constant about 6 due to thicker GeOx interfacial layer or higher Ge-related compounds incorporation. For that deposited at 50 °C, both higher C incorporation and more porous like of the film leaded to unacceptable gate leakage and lower dielectric constant about 6. We believe that higher CET of those samples annealed at 400 and 500 °C is due to thicker GeOx interfacial layer. Based on High-Low frequency (HLF) method, we did further calculation of Dit of those gate stacks with PMA 400 °C and summarized that in Fig. 3-9. It shows that the gate stack with ALD film deposited at 100 °C would own the minimum amount of Dit due to flat interface and less formation of GeOx compared with that of the 50 °C one. Because of higher interface roughness, we obtained a film with higher Dit at higher deposition temperature. For more precision calculations and a more consistency result, we calculated Dit by the powerful method − Conductance (G-V) method − in comparison to that calculated by HLF method mentioned above.
3-3-3 The powerful Dit calculation method − Conductance (G-V) method.
Figures 3-10 ~ 11 show the <GP>/w (discrete symbols) calculated by eq. 3.3 and the curves (solid lines) simulated by eq. 3.4 for the films subjected to PMA 400 and
600 °C [44, 45] thermal treatments and Fig. 3-12 shows that for Vg = Vth for rough
By simulating the calculated data from Cm and Gm by eq. 3.4, we could extract the
value of Dit that had been summarized in Fig. 3-13. It shows a consistent result with that of the Dit calculation by HLF method. The film deposited at 100 °C still has the minimum amount of Dit (~ 2x1012 /cm2) and all of the Dit of those films deposited at various temperatures increased with increase of PMA temperature. For further improving the Dit of the gate stack with ALD film deposited at 100 °C, we performed the FGA thermal treatment to minimize the value of Dit. Figs. 3-14 and 3-15 show, respectively, the multi-frequencies of the measured C-V characteristics and fitting results of the calculated <GP>/w for the as-deposited and FGA treated films. We summarized the Dit extraction in Fig. 3-16 from the simulated results in Fig. 3-15 and got a Dit improved film about 1/10 times Dit of that as-deposited. We also displaced the effects of all the thermal treatments on the gate stacks with Al2O3 dielectrics deposited at 100 °C in Figs.3-17 ~ 18. We could do really get a film with Dit less than 1012 /cm2 after subjecting it to the thermal treatment − FGA.
3-4 Summary
We had displaced all the electrical performances what should be present of those ALD films deposited at 50, 100, 200 and 300 °C in this chapter. By analyzing the trap characteristics through continuing increasing the bias voltage in one sweep direction, extracting Vfb while getting the measured capacitance equal to the value of CFB
defined by eq. 3.2, and calculating the hystereses of those samples with different thermal processes, we figured out the possible mechanisms contributing to HT, ET, PFOC, and NFOC along with the results from chapter 2. We also showed the relationship between CET and leakage current of our results in comparison to that on the traditional SiO2/Si gate stacks and estimated the dielectric constants (about 6 ~ 9.8) roughly by inserting the physical thicknesses measured by HRTEM of those as-deposited ALD films. Based on the results from chapter 2, we pointed out the possible reasons for those unacceptable conditions showed in Fig. 3-8. We have tow consistent results of Dit calculation by G-V and HLF methods and succeed further improving it of the best condition (deposition temperature ~ 100 °C) to form a gate stack with Dit less than 1012 /cm2 by use of the thermal treatment − FGA.
Fig. 3-17 Calculated <GP>/ (for Vg= Vth), by 1 kHz ~ 1 MHz C-V and G-V electrical performance, of the 60 cycs. ALD Al2O3films deposited at 100 C with various thermal treatment. The symbols and solid lines represent the calculated and simulated data, respectively.