4-3-1 The Id – Vg , Id – Vd , and Ijunc – Vjunc essential electrical performance of the Ge p-MOSFETs with various implantation and activation conditions.
Figures 4-2 ~ 4 illustrate the electrical characteristics of the devices with 10 μm gate length and 100 μm gate width. Fig. 4-7 (a) and (b) show the comparison between the 550 °C activated MOSFETs with different implantation energy. From those figures mentioned, we could find that the Id – Vg performance of a device with higher implantation energy and lower activation temperature shows a more ideal Vth (ideal Vth is about ~ -0.2 V) and higher saturation current. For the Id – Vd characteristics, we preferred the 60 keV implantation energy and 550 °C activation temperature to fabricate the MOSFET. It shows higher series resistance while suffering to 600 and 650 °C activations that might be due to high dopant lost into air during the activation process [40, 41]. With increase of activation temperature, both 30 and 60 keV implanted MOSFETs have degraded Id – Vg and Id – Vd curves. By inspecting the performance of the P-N diodes illustrated in Fig. 4-4 and 4-7 (c), we presumed that the suddenly increase of reverse junction current at high reverse bias resulted in the suddenly increase of drain current at high drain forward bias. Besides, it shows that 60 keV and 550 °C activation temperature is the best condition to form a P-N junction.
The decrease of forward current (increase of series resistance) and increase of reverse current imply getting worse of dopant lost and substrate stress while increasing the activation temperature.
4-3-2 The Vth , RSD , ΔL , S.S. , μeff , and μFE extracted from the essential electrical performance of the Ge p-MOSFETs with various implantation and activation conditions.
From essential measurements of Id – Vg and Id – Vd, we could extract and calculate those important parameters such as Vth , RSD , ΔL , S.S. , μeff , and μFE to judge by the quality of the MOSFETs more professionally.
− Vth −
Vth was extracted by Linear Extrapolation (LE) method with the drain current measured as a function of gate voltage at a low drain voltage of typically 50-100 mV to ensure operation in the linear MOSFET region. According to eq. 4.2 which is valid only above threshold for non-zero and asymptotic decrease of Id below threshold, we have zero drain current for ) 0
2 V V
(Vg − th − d = . Hence the Id v.s. Vg curves are extrapolated to Id = 0, we can determine Vth from the extrapolated or intercept gate voltage Vg, ex by eq. 4.3 with some error due to non-negligible series resistance.
)
All the extrapolating results of devices with 10 μm gate length were summarized in Fig. 4-9 against the mask channel length. We dug out short channel effect (SCE) regarding which device was discussed and reverse short channel effect (RSCE) for the 650 °C activated devices. We considered that RSCE is due to parallel MOSFETs (Series Transistor Effect) resulted from B transient enhanced diffusion (TED) and compensation effect (CE) at the damaged region caused by implantation (where B aggregated) near substrate surface. RSCE got more appreciable for the 650 °C activated devices.
− S.S. −
We used the definition of S.S. as eq. 4.4 (CD, max is the equivalent semiconductor capacitance corresponding to maximum substrate depletion width − Wmax) to extract this parameter which is related intimately to switch ability of a MOSFET.
C )
The ideal value of S.S. for our case is about 60 mV/decade calculated by the second term in eq. 4.4. Fig. 4-10 illustrates all the extracted values against the mask channel length for all the MOSFETs mentioned. It shows the usual and unusual occurrence of SCE and S.S.-related RSCE, respectively. We presumed that S.S.-related RSCE was due to increase of Wmax resulted from Charge Sharing Effect (CSE). And the somewhat lower values of S.S. of the 600 °C activated MOSFETs might be also due to CSE for high diffusion ability of B.
− RSD and ΔL −
behavior at linear region. We had summarized the calculated outcome and linear fitting curves in Fig. 4-8. Table. 4-2 summarized the extracted values of Vth , S.S. ,
RSD , and ΔL of the devices with 10 μm gate length. The lost extraction of RSD and ΔL for higher activation temperature might be resulted from ΔL-related RSD and severe B out-diffusion into air. We had the minimum value of RSD for 60 keV implanted and 550
°C activated devices and found that higher implantation energy and activation temperature would lead to longer dopant in-diffusion (larger ΔL). The increase of RSD
is another evidence of dopant lost while increasing the activation temperature.
− μeff and μFE − respectively. The black dash-dot-dot line represents the outcome of Si-based MOSFETs for easy comparison. The lower value of μeff compared with μeff might be
due to higher RSD . Lower value of mobility compared with that of Si might be resulted from severe surface roughness and phonon scattering.
4-4 Summary
We had succeeded in demonstrating a Ge-based p-MOSFET by the standard 4 mask process. Almost all the electrical performances and indicative parameters that should be present and calculated were illustrated for those Ge p-MOSFETs with different dopant activation conditions in this chapter. High carrier diffusion coefficient, high intrinsic carrier conc, and narrower energy bandgap lead to high junction leakage in our studies. Junction leakage may be the most severe issue in realizing a high mobility, excellent switch ability, and low power consumption Ge-based transistor. By analyzing the Id – Vg and Id – Vd electrical characteristics and extracting those parameters such as Vth , RSD , ΔL , S.S. , μeff , and μFE , we have the ideal about what would happen and should be paid heed to when deal with such a nasty substrate material. 60 keV and 550 °C is the best condition to form a P-N junction. Dopant lost during activation process is another issue in Ge p-MOSFET fabrication. It should be better to continue improving the Ge-based P-N diode for realization of an acceptable transistor in the future.
Fig. 4-3 The Id Vd electrical performance of the Ge p-MOSFETs with dopant implantation energy (a) (b) 30 keV and (c) (d) 60 keV. Gate length (L) = 10 m and gate width (w) = 100 m.
(a) (b)
(c) (d)