For wrapped-select-gate SONOS-type TFT memory, we have two transistor characteristic in one cell which were controlled by word-line gate and select gate respectively. Fig. 3.1 - Fig. 3.3 show basic ID-VWL characteristics for three types of
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WSG TFT memory. On the other hand, Fig. 3.4 - Fig. 3.6 show inner IDVSG characteristics of Nitride-based (Nitride) cells, Nitride with Si dot (Nitride_Dot) cells, and N+ floating gate (Floating gate) cells. They have similar on/off ratio and threshold voltage in low drain voltage measurement. We additionally observe that Floating gate cell have serious floating gate coupling problem in Fig. 3.6. The off current is rise when VSG is larger than 8V.
As mentioned before, split gate structure can offer a more effective way for electrons to tunnel into trapping layer that we called source side injection [3.4]. Fig.
3.7 shows program speed characteristics of Nitride cell with different word-line gate voltage. We can observe that VWL=18V case has the fastest speed for programming.
3V memory window can be achieved in few micro-second. The same results also occur in Nitride_Dot cell and Floating gate cell, as shown in Fig.3.8 and Fig. 3.9.
Although having faster speed in short programming time, Floating gate cell cannot separate program operation for bit1 and bit2 due to floating gate coupling. That is to say, in this operation bias, Floating gate cell no longer has two bit per cell operation characteristics. So we also exhibit another operation bias for program in Fig. 3.10 which apparently has slower speed and acceptable 2nd bit effect with 2V memory window. In order to make it clear to understand where is the main injection location for electron tunneling by source-side-injection mechanism, the simulated electric field is performed both laterally and vertically, as shown in Fig.3.11 and Fig.3.12.. Channel region ranges from x=-0.5m to x=0.5m and voltage bias are set to be VWL=16~18V, VBL=8V, and VSG=2V. We find that VWL=18V case has both strongest lateral and vertical electric field in ONO gap between word-line gate and select gate. By increasing word-line gate voltage, the voltage difference between word-line gate and inversion layer increases. Thus, we have larger vertical electric field. At the same time,
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the bit-line voltage becomes easier to couple into gap region by inversion region. In this way, higher voltage difference between two inversion regions gives rise to larger lateral electric field. That is why VWL=18V case shows the fastest program speed and largest memory window.
Let’s talk about the influence of bit-line voltage in program speed measurement.
Voltage bias are set to be VWL=17V, VBL=7~9V, and VSG=0.6V. As shown in Fig. 3.13 to Fig. 3.15, the larger bit-line voltage is applied, the faster program speed we have. In order to attain acceptable two bit operation, junction breakdown injection mechanism was performed to single side programming, as shown in Fig. 3.16. Also, the results of simulated lateral and vertical electric field are shown in Fig. 3.17 and Fig. 3.18. When we increase bit-line voltage, higher voltage difference between word-line inversion and select gate inversion regions gives rise to larger lateral electric field. Besides, the voltage difference between word-line gate and its inversion region decreases which suppress vertical electric field of gap region.
In wrapped-select-gate structure memory, not only word-line gate voltage and bit-line voltage but also select gate voltage can control the programming current and electric field during program speed measurement. The following measurements are divided into two parts, large VSG (VSG=1, 2, 3 V) and small VSG (VSG=0, 0.4, 0.8 V).
Fig. 3.19 shows that large VSG could result in the suppression of electron tunneling from channel to nitride trapping layer. However, in small VSG measurements, three cases exhibit comparable program speed characteristics, as shown in Fig. 3.20.
Without the suppression of electric field, programming current becomes dominant in these tests. We find that VSG=0V case still have equal programming current compared to VSG=0.8V case due to large operation bias like VWL=18V and VBL=8V. The same results are repeated in Nitride_Dot cell and Floating gate cell, as shown in Fig. 3.21 to
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Fig. 3.24. Regarding the single side programming for Floating gate cell by junction breakdown injection mechanism, programming current no longer plays a key role in these measurements, as shown in Fig. 3.25 and Fig. 3.26. When select gate voltage is increased, both lateral and vertical are suppressed which give rise to slower program speed. The simulations of electric field are also carried out to demonstrate the influence of select gate voltage, as shown in Fig. 3.27 and Fig. 3.28.
In this thesis, we use reverse read and forward read techniques to determine the states of bit1 and bit2. However, traditional SONOS memory device exists the interference between two states we called 2nd bit effect [3.5]-[3.7]. Fig. 3.29 shows the interference between programmed bit1 and erased bit2 of WSG TFT memory Nitride cell. Threshold voltage variation of bit2 is smaller than 1V under applying VBL=6V and VSG=4V. In this way, we indeed have memory window larger than 4V. Fig. 3.30 also shows the interference between programmed bit1 and erased bit2 of WSG TFT memory Nitride_Dot cell. Under reading voltage VBL=6V and VSG=4V operation, Nitride_Dot still exhibits acceptable VT variation of bit2 although bit1 is programmed to larger memory window. Based on single side programming, Floating gate cell also shows 2V memory window in spite of serious floating gate coupling effect, as shown in Fig. 3.31.
Erase operation is performed by band-to-band tunneling hot hole injection and junction breakdown mechanism. Holes are accelerated by large positive bit-line voltage and tunnel into trapping layer. Fig. 3.32 shows erase speed of WSG TFT memory Nitride cell with VWL=-6~-8V. We observe that VWL=-8V, VBL=18V, VSG=0V case exhibits the fastest erase speed due to the largest tunneling opportunity resulting from vertical electric field. Fig. 3.33 shows the influence of VBL in erase speed measurements. We know that larger junction reverse bias would generate more holes
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around junction region. As we expected, among three cases of VBL=16, 17, 18V, VBL=18V shows the greatest erase ability, about 6V in one second. Fig. 3.34 and Fig.
3.35 show erase speed characteristics of WSG TFT memory Nitride_Dot cell with various word-line voltages and bit-line voltages. Compared to the results of Nitride cell, they have comparable erase speed in both measurements. For Floating gate cell, owing to floating gate coupling, they have faster erase speed in short erase time, as shown in Fig. 3.36 and Fig. 3.37. After measurement with different word-line bias and bit-line bias, we still need to confirm the hot holes injection location during erase. We observe that both lateral and vertical direction have large electric field peak right in the overlapped region of word-line gate and drain region, as shown in Fig. 3.38 and Fig. 3.39. However, operation bias of BTBTHH may lead to unwanted situation that bit 1 and bit 2 are erased at the same time. In order to achieve two bit operation, single side junction breakdown mechanism with smaller operation voltages is performed again with VWL=-8V, VBL=15V, and VSG=0V. Fig. 3.40 and Fig. 3.41 shows slower erase characteristics of Floating gate cell with acceptable 2nd bit effect.
In the end of this chapter discussion, all programming and erase mechanism of different cells are listed in Table 3.1. Speed, 2nd bit effect, and endurance to 10K time P/E cycle are carried to comparison sheet.