Summary

Owing to the development of portable electronic devices, people are looking forward memory devices with fast program speed, fast erase speed, and high density characteristics. Wrapped-select-gate structure memory devices show excellent P/E speed with source-side injection and BTBTHH injection mechanism. Moreover, WSG structure memory devices also perform two bit operation exhibiting good immunity to

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2^nd bit effect. We also observe that the increase of word-line gate voltage will enhance both lateral and vertical electric field during programming. On the other hand, the increased bit-line voltage will enhance lateral electric field but suppress vertical electric field at the same time. For erase operation, bit-line voltage is responsible for generation of excess holes while word-line voltage take charge of tunneling efficiency.

Among three types of WSG TFT memory, Floating gate cell suffers serious floating gate problems. Nitride cell and Nitride_Dot cell show great potential to scaling down and outstanding P/E characteristics.

29 Nitride trapping layer on the different select gate voltage

-4 -2 0 2 4 6 8 Nitride + Si dot trapping layer on the different select gate voltage

-4 -2 0 2 4 6 8 N⁺ floating gate trapping layer on the different select gate voltage

30 Nitride trapping layer on the different select gate voltage

-4 -2 0 2 4 6 8 Nitride + Si dot trapping layer on the different select gate voltage

-4 -2 0 2 4 6 8 N⁺ floating gate trapping layer on the different select gate voltage

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Fig. 3. 7 Program speed characteristics of WSG SONOS-type TFT memory with Nitride trapping layer on the various word line bias

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Fig. 3. 8 Program speed characteristics of WSG SONOS-type TFT memory with Nitride + Si dot trapping layer on the various word line bias

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Fig. 3. 9 Program speed characteristics of WSG SONOS-type TFT memory with N⁺ floating gate trapping layer on the various word line bias

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Fig. 3. 10 Program speed characteristics of WSG SONOS-type TFT memory Floating gate cell on the various word line bias exhibiting acceptable 2^nd bit effect

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Lateral Distance (  m)

Fig. 3. 11 The simulated results of lateral electric field start from VWL=16V to VWL=18V in the channel of WSG SONOS TFT memory device

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Lateral Distance (  m)

V_WL=16V

Fig. 3. 12 The simulated results of vertical electric field start from VWL=16V to VWL=18V in the channel of WSG SONOS TFT memory device

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Fig. 3. 13 Program speed characteristics of WSG SONOS-type TFT memory with Nitride trapping layer on the various bit line bias

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Fig. 3. 14 Program speed characteristics of WSG SONOS-type TFT memory with Nitride + Si dot trapping layer on the various bit line bias

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Fig. 3. 15 Program speed characteristics of WSG SONOS-type TFT memory with N⁺ floating gate trapping layer on the various bit line bias

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Fig. 3. 16 Program speed characteristics of WSG SONOS-type TFT memory Floating gate cell on the various bit line bias exhibiting acceptable 2^nd bit effect

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Lateral Distance (  m)

Fig. 3. 17 The simulated results of lateral electric field start from VBL=7V to VBL=9V in the channel of WSG SONOS TFT memory device

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Lateral Distance (  m)

V_BL=7V

Fig. 3. 18 The simulated results of vertical electric field start from VBL=7V to VBL=9V in the channel of WSG SONOS TFT memory device

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Fig. 3. 19 Program speed characteristics of WSG SONOS-type TFT memory with Nitride trapping layer on the large select gate bias

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Fig. 3. 20 Program speed characteristics of WSG SONOS-type TFT memory with Nitride trapping layer on the small select gate bias

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Fig. 3. 21 Program speed characteristics of WSG SONOS-type TFT memory with Nitride + Si dot trapping layer on the large select gate bias

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Fig. 3. 22 Program speed characteristics of WSG SONOS-type TFT memory with Nitride + Si dot trapping layer on the small select gate bias

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Fig. 3. 23 Program speed characteristics of WSG SONOS-type TFT memory with N⁺ floating gate trapping layer on the large select gate bias

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Fig. 3. 24 Program speed characteristics of WSG SONOS-type TFT memory with N⁺ floating gate trapping layer on the small select gate bias

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Fig. 3. 25 Program speed characteristics of WSG SONOS-type TFT memory Floating gate cell on the large select gate bias exhibiting acceptable 2^nd bit effect

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Fig. 3. 26 Program speed characteristics of WSG SONOS-type TFT memory Floating gate cell on the small select gate bias exhibiting acceptable 2^nd bit effect

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Lateral Distance (  m)

L_WL/W/L_SG=1/10/0.4 (m)

Fig. 3. 27 The simulated results of lateral electric field start from VSG=0.5V to VSG=2V in the channel of WSG SONOS TFT memory device

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Lateral Distance (  m)

VSG=0.5V V_SG=1V V_SG=1.5V V_SG=2V

Fig. 3. 28 The simulated results of vertical electric field start from VSG=0.5V to VSG=2V in the channel of WSG SONOS TFT memory device

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@ Program Bit1: V_WL/V_BL/V_SG=8/15/0V_100msec Read: V_WL sweep -4 to 9V, V_SG=4V

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Fig. 3. 31 The schematic of 2^nd bit effect of WSG TFT memory Floating gate cell

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Fig. 3. 32 Erase speed characteristics of WSG SONOS-type TFT memory with Nitride trapping layer on the various word line bias

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Fig. 3. 33 Erase speed characteristics of WSG SONOS-type TFT memory with Nitride trapping layer on the various bit line bias

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Fig. 3. 34 Erase speed characteristics of WSG SONOS-type TFT memory with Nitride + Si dot trapping layer on the various word line bias

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Fig. 3. 35 Erase speed characteristics of WSG SONOS-type TFT memory with Nitride + Si dot trapping layer on the various bit line bias

45 N⁺ floating gate trapping layer on the various word line bias

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Later al Elec tric F ield ( MV/c m)

Lateral Distance (  m)

Fig. 3. 38 The simulated results of lateral electric field with bias VWL=-8V, VBL=18V, and VSG=2V in the channel of WSG SONOS TFT memory device

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Ver tical Elec tric F ield ( MV/c m)

Lateral Distance (  m)

Fig. 3. 39 The simulated results of vertical electric field with bias VWL=-8V, VBL=18V, and VSG=2V in the channel of WSG SONOS TFT memory device

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Fig. 3. 40 Erase speed characteristics of WSG SONOS-type TFT memory Floating gate cell on the various word line bias exhibiting acceptable 2^nd bit effect

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Fig. 3. 41 Erase speed characteristics of WSG SONOS-type TFT memory Floating gate cell on the various bit line bias exhibiting acceptable 2^nd bit effect

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Table 3. 1 Comparison sheet of operation bias of WSG SONOS-type TFT memory

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Chapter 4

Reliabilities of WSG-SONOS-type TFT memory

4.1 Introduction

Besides struggling for better performance characteristics of memory device, the reliabilities of memory device are still concern issues as scaling down. The most frequently mentioned reliabilities include gate disturbance, drain disturbance, data retention, and P/E endurance [4.1]-[4.3]. The scaling down of conventional floating gate memory devices has met limitations beyond 60-nm node technology. Further scaling of tunneling oxide below 7nm may face challenges including stress induced leakage current (SILC), short channel effect, floating gate coupling effect, and drain-induced turn on effect, etc. [4.4]-[4.6]. Storing charges in discrete trapping sites layer can offer us an excellent immunity to above serious problem. Moreover, we can have two bit operation and better data retention characteristics. When we apply program or erase operation in a memory array, the neighboring un-selected cell may suffer word-line disturb or bit-line disturb. Hence, in this chapter, we will discuss disturbance phenomena, P/E cycle endurance, and date retention at different temperature values in detail.

4.2 Results and Discussions

We have discussed the program and erase mechanism in detail in previous chapter. According to the results of discussions before, Wrapped-Select-Gate structure memory cells exhibit fast program speed and erase speed. However, disturbance phenomena always happen in memory array operation. In order to make an

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investigation of word line disturb and bit line disturb, Nitride-based (Nitride) cells, Nitride with Si dot (Nitride_Dot) cells, and N⁺ floating gate (Floating gate) cells are programmed to memory window of 3V, 3V, 2V, respectively. First of all, Fig. 4.1 shows word line disturbance characteristics of a Nitride cell with stress bias, 16V, 17V, and 18V. The normalized window axis means the remaining window over initial window after a period of stress time. We find that all three positive word line biases give rise to charge loss by gate leakage. Trapped electrons tunnel to word line gate away from channel and then amount of negative threshold voltage shift (0.33V) is observed in long disturb time. On the other hand, bit line disturb biases are applied to Nitride cell, as shown in Fig. 4.2. Trapped electrons tunneling through bottom oxide result in much severer charge loss problem in disturb test. The worst case is that about 0.7V threshold voltage shift under 18V bit line stress bias.

Similarly, two kinds of disturb bias are applied to Nitride_Dot cells, as shown in Fig. 4.3 and Fig. 4.4. The results different to those of Nitride cells are word line disturb phenomena. Nitride_Dot cells seem to have severer word line disturb problem than Nitride cells because of the existence of Si nanocrystals in trapping layer. Under overall positive word line bias, electrons trapped in Si nanocrystals may accumulate on the upper side and have larger chance to tunnel through blocking oxide compared to bulk nitride trap. As for bit line disturb of Nitride_Dot cells, regardless of thinner tunneling oxide layer, because only partial trapping region are directly affected by V_BL, charge loss slightly decrease when lower bit line voltage is applied.

Fig. 4.5 shows the word line disturb phenomena of Floating gate cells. Due to smaller operation biases of Floating gate cells, memory states are almost unaffected until long stress period time. Unlike to previous discussions, floating gate coupling in word line disturb test causes electron trapping. Electrons of N⁺ source/drain region go

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to floating gate by Fowler-Nordheim tunneling mechanism and then raise the threshold voltage of device. It is worth to note that VWL=6V is not enough to make electron tunneling happen. Therefore, the normalized window remains constant even longest stress time is reached. Because of inferior trapping capability, however, Floating gate cells still have comparable charge loss with lower bit line voltage in disturbance test, as shown in Fig. 4.6.

In order to achieve two-bit or multi-bit operation, hot electron injection and band-to-band tunneling induced hot hole erase have been widely used for a long time.

However, endurance and retention are still two concerns related to repeat P/E stress [4.2]. Memory window closure with program/erase cycling especially in thin film transistor memory devices is a serious reliability concern in novel discrete charge trapping devices. Window closure is believed to arise from build-up of permanent excess electrons trapped in ONO stack and defect generation [4.7]. Fig. 4.7 shows the endurance characteristic of a Nitride cell. The trend of window narrowing is observed due to increasing V_T of erase state and, at the same time, decreasing V_T of program state. When cycling times is rising, more and more defects are generated in channel grain boundaries and TEOS oxide interface. The other reason may be attributed to long channel length. Accumulated electron in trapping layer didn’t recombine with hot holes which results in programming efficiency lowering. In the meanwhile, excess holes are ejected to the overlap region between word line gate and drain. Once these holes didn’t recombine with trapped electrons, they have limited capability of reducing threshold voltage of memory device. That is why 3.5V window is left to be less than half of initial window after 10k times P/E cycling. Although bit 1 underwent repeated P/E stress, we can find that these operations of bit 1 completely do not carry

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any influence on bit 2 state. In other words, wrapped-select-gate structure memory device has excellent immunity to second bit effect.

Fig. 4.8 shows the endurance characteristic of a Nitride_Dot cell. Under the same bias condition, Nitride_Dot cell have larger initial memory window. However, as cycling time increases, the threshold voltage of program state and erase state become closer to each other. This phenomenon can be attributed to the poor quality of TEOS tunneling oxide and mismatch of electrons and holes. More and more charges pile up in tunneling oxide and trapping layer which hinders P/E operation. As mentioned before, we can observe that only about 1.6V memory window is left over after 10k P/E cycling times. There also have no interference between bit1 state and bit2 state in endurance test. That is to say, in wrapped-select-gate structure Nitride_Dot cell, it shows great potential in multi-bit operation because of outstanding immunity to 2^nd bit effect.

We can see the endurance characteristics of wrapped-select-gate structure Floating gate cell in Fig. 4.9. Unlike to Nitride cell and Nitride_Dot cell, Floating gate cell have no charge mismatch problem that suppress the happening of window closure.

However, poor quality of TEOS tunneling oxide still brings influence on defect generation and interface state issue. We find that both threshold voltage of program state and erase state keep on a rise as cycling times increases. Owing to the lack of ability to stop charges moving from bit 1 to bit 2 in program state, we can observe that when bit1 is programmed, bit2 state V_T has large range of variation.

In order to study the impact of different electron injection location by SSI and conventional channel hot electron (CHE) Injection, endurance test was also performed with VWL=12V, VBL=12V, and VSG=0V programming bias in Nitride_Dot cell, as shown in Fig. 4.10. More serious window closure problem occurs because of repeated

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tunneling by hot electrons during programming and hot holes during erase in the same place. This operation process may cause much more defects generated near the overlap region of word-line gate and drain region. Fig 4.11 and Fig. 4.12 again demonstrate the electron injection location of CHE is near the drain side. Because we have major electric field both laterally and vertically near the drain region.

The other serious concern is long-tern retention of cycled charge trapping device.

First of all, Fig. 4.13 shows data retention characteristics of 1 cycled WSG SONOS-type TFT memory device Nitride cell with various temperatures, 25^oC, 55^oC, and 85^oC. Due to a lot of original defects in TEOS tunneling oxide, long-term 85^oC retention case has more than 20% charge loss in Nitride cell of 3V window. However, 10k cycled Nitride cell exhibits worse data retention characteristics in all three temperature cases, as shown in Fig. 4.14. The degraded retention characteristic refers to accumulated oxide damage from P/E cycling.

Despite high temperature and oxide defects enhance the opportunity of charge detrapping, Nitride_Dot cell still shows better retention characteristics in both 1 cycle and 10k cycled case, as shown in Fig. 4.15 and Fig. 4.16. All of these improvements may be attributed to deeper trap state of Si nanocrystal. Charges trapped in Si nanocrystal rather than bulk nitride native trap have less chances to tunnel out, especially in long-term data retention measurement. However, there one thing we might need to note is that electron injection location has great influence on retention characteristics of cycled devices. Repeat P/E operation in the same region (CHE/Drain Avalanche Hot Carrier program and BTBTHH erase) generates excess defects in tunneling dielectric which causes extra charge loss in high temperature retention measurement.

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Fig. 4.17 shows data retention characteristics of 1 cycled WSG SONOS-type TFT memory device N⁺ floating gate with cell various temperatures. Inferior to charge trapping devices in data retention characteristics, the existence of defect offer a tunneling path of charge and high temperature may speed up the velocity of charge loss. All charges in floating gate can move to the easiest tunneling path, however, charges in charge trapping device cannot move randomly. For 1 cycled Floating gate cell with 2V memory window, long-term 85^oC retention case has more than 40%

charge loss. This phenomenon reminds us it is very important to control the quality of tunneling oxide for floating gate memory device. As for 10k cycled Floating gate cell, as shown in Fig. 4.18, it is an extremely tough mission to keep charges staying in floating gate device with excess defects and oxide damage. Both short-term and long-term retention suffer serious charge loss problem.

4.3 Summary

In this chapter, we discuss the characteristics of word line disturb, bit line disturb, P/E cycle endurance, and date retention. We observe that Nitride cell has better word line disturb performance than Nitride_Dot cell. Floating gate cell has no gate leakage issue in word line disturb due to floating gate coupling phenomenon. Regarding bit line disturb performance, Nitride_Dot cell shows better performance than Nitride cell under the same stress bias.

On the performance of endurance test, Nitride cell and Nitride_Dot cell have comparable characteristics. Both of them suffer from electron/hole mismatch problem which results in obvious window closure phenomena. Because of the absence of the disadvantage charge trapping device, charges can move around in floating gate. So no window closure problem is observed in endurance measurement of Floating gate cell.

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In the last part of this chapter is the discussion about data retention characteristics. All three types of memory device has serious charge loss problem due to poor quality of TEOS tunneling oxide. Nevertheless, Nitride_Dot cells still exhibit the greatest performance of date retention characteristic among three types of devices.

Compared to 10k-cycled Nitride cell, 10k-cycled Nitride_Dot cell has 6-8%

improvement on high temperature retention measurement.

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Fig. 4. 1 Word line disturbance characteristics of WSG SONOS-type TFT memory with Nitride trapping layer on the various stress bias

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Fig. 4. 2 Bit line disturbance characteristics of WSG SONOS-type TFT memory with Nitride trapping layer on the various stress bias

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Fig. 4. 3 Word line disturbance characteristics of WSG SONOS-type TFT memory with Nitride + Si dot trapping layer on the various stress bias

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Fig. 4. 4 Bit line disturbance characteristics of WSG SONOS-type TFT memory with Nitride + Si dot trapping layer on the various stress bias

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Program: V_WL/V_BL/V_SG=8/15/0V_20msec

Fig. 4. 5 Word line disturbance characteristics of WSG SONOS-type TFT memory with N⁺ floating gate trapping layer on the various stress bias

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Fig. 4. 6 Bit line disturbance characteristics of WSG SONOS-type TFT memory with N⁺ floating gate trapping layer on the various stress bias

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Fig. 4. 7 Endurance characteristics of WSG SONOS-type TFT memory with Nitride trapping layer

Fig. 4. 8 Endurance characteristics of WSG SONOS-type TFT memory with Nitride + Si dot trapping layer

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Fig. 4. 10 Endurance characteristics of WSG SONOS-type TFT memory with Nitride + Si dot trapping layer by CHE/DAHC injection

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Lateral Distance (  m)

Fig. 4. 11 The simulated results of lateral electric field with bias VWL=12V, VBL=12V, and VSG=2V in the channel of WSG SONOS TFT memory device

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Fig. 4. 12 The simulated results of vertical electric field with bias VWL=12V, VBL=12V, and VSG=2V in the channel of WSG SONOS TFT memory device

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Fig. 4. 13 Data retention characteristics of 1 cycled WSG SONOS-type TFT memory device with Nitride trapping layer on the various temperatures

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Fig. 4. 14 Data retention characteristics of 10k cycled WSG SONOS-type TFT memory device with Nitride trapping layer on the various temperatures

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@ Nitride+Si dot_1 P/E cycled

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Fig. 4. 15 Data retention characteristics of 1 cycled WSG SONOS-type TFT memory device with Nitride + Si dot trapping layer on the various temperatures

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Fig. 4. 16 Data retention characteristics of 10k cycled WSG SONOS-type TFT

Fig. 4. 16 Data retention characteristics of 10k cycled WSG SONOS-type TFT

在文檔中 隱藏式選擇性閘極結構之薄膜電晶體記憶體元件研究 (頁 42-80)