Chapter 2 Literature Reviews
2.2 Reviews of ZnO TFTs
ZnO thin film deposited for TFTs reveals polycrystalline with a hexagonal wurtize structure and has a preferred orientation (002) with the c-axis perpendicular to the substrate. Zinc oxide has several advantages[16, 17]：
1. Cost down and abundant 2. Wide band gap~3.3eV 3. High mobility
4. Bipolarity material (n-type or p-type with different dopants)
And using zinc oxide to replace a-Si as active layer in TFTs has many Advantages[18, 19]：
1. High filed-effect mobility (> 1cm2˙V-1˙S-1) 2. Low deposition temperature
3. Wide band gap (~3.3eV) 4. Stability
2.2.1 ZnO TFTs Fabricated by Atomic Layer Deposition
Atomic layer deposition (ALD) is a thin film deposition technique that is based on the sequential use of a gas phase chemical process. The majority of ALD reactions use two chemicals, typically called precursors. These
precursors react with a surface one-at-a-time in a sequential manner. By exposing the precursors to the growth surface repeatedly, a thin film is deposited.
ALD is a self-limiting (the amount of film material deposited in each reaction cycle is constant), sequential surface chemistry that deposits conformal thin-films of materials onto substrates of varying compositions.
ALD is similar in chemistry to chemical vapor deposition (CVD), except that the ALD reaction breaks the CVD reaction into two half-reactions, keeping the precursor materials separate during the reaction. Due to the characteristics of self-limiting and surface reactions, ALD film growth makes atomic scale deposition control possible. By keeping the precursors separate throughout the coating process, atomic layer control of film growth can be obtained as fine as ~0.1 Å (10 pm) per monolayer. Separation of the precursors is accomplished by pulsing a purge gas (typically nitrogen or argon) after each precursor pulse to remove excess precursor from the process chamber and prevent 'parasitic' CVD deposition on the substrate.
The growth of material layers by ALD consists of repeating the following characteristic four steps as shown in figure 2-4:
(1) Exposure of the first precursor.
(2) Purge or evacuation of the reaction chamber to remove the non-reacted precursors and the gaseous reaction by-products.
(3) Exposure of the second precursor or another treatment to activate the surface again for the reaction of the first precursor.
(4) Purge or evacuation of the reaction chamber.
Transparent ZnO thin film transistor was fabricated on glass substrate.
The field effect mobility is about 1~10 cm2/Vs. The active layer (ZnO), gate insulator (Al2O3 or SiN), and source–drain electrode (ZnO:Al) were deposited by atomic layer deposition as shown in figure 2-5. The carrier density of the ZnO layer was carefully adjusted to reduce off-current of TFT.
Good contact with small contact resistance was formed between the active layer and the source–drain electrode. The on-off ratio of ZnO TFTs fabricated by ALD is about 106~108.
The four main factors contributing to obtain well-behaved ZnO-TFTs by ALD method were the reduction of the carrier amount of ZnO film by lowering the growth temperature, minimal damage to the surface of dielectric during the S/D and active layer processes, the high quality of the dielectric layer grown by ALD, and the good ohmic contact between the S/D and the active layer resulting in ZnO TFT performance suitable for an OLED driving device. Although the wet etching of the active layer degraded the TFT performance, it showed promise as a large area transparent display.
The active layer process temperature was as low as 100°C and was also compatible with a plastic substrate to realize a flexible display.
The major limitation of ZnO TFTs fabricated by ALD is its slowness and high prime cost; usually only a fraction of a monolayer is deposited in one cycle. Fortunately, the films needed for future-generation ICs are very thin and thus the slowness of ALD is not such an important issue. Although the selection of film materials grown by ALD is wide, many technologically
important materials cannot currently be deposited by ALD in a cost-effective way. ALD is a chemical technique and thus there is always a risk of residues being left from the precursors.
2.2.2 ZnO TFTs Fabricated by RF Magnetron Sputtering
Sputter deposition is a physical vapor deposition process for depositing thin films, sputtering means ejecting material from a target and depositing it on a substrate such as a silicon wafer. The target is the source material.
Substrates are placed in a vacuum chamber and are pumped down to a prescribed process pressure. Sputtering starts when a negative charge is applied to the target material causing a plasma or glow discharge. Positive charged gas ions generated in the plasma region are attracted to the negatively biased target plate at a very high speed. This collision creates a momentum transfer and ejects atomic size particles form the target. These particles are deposited as a thin film into the surface of the substrates.
Magnetron sputtering can be done either in DC or RF modes. DC sputtering is done with conducting materials. If the target is a non conducting material the positive charge will build up on the material and it will stop sputtering. RF sputtering can be done both conducting and non
magnetron sputtering on Si substrates held near room temperature. The best devices had field-effect mobility of more than 2 cm2/Vs and an on/off ratio about 105~107. With high optical transparency ~80% for wavelength 400nm.The combination of transparency in the visible, excellent transistor characteristics, and low-temperature processing makes ZnO thin-film transistors attractive for flexible electronics on temperature sensitive substrates.
2.2.3 ZnO TFTs Fabricated by Pulsed laser deposition
Pulsed laser deposition (PLD) is a thin film deposition (specifically a physical vapor deposition, PVD) technique where a high power pulsed laser beam is focused inside a vacuum chamber to strike a target of the material that is to be deposited as shown in figure 2-8. This material is vaporized from the target (in a plasma plume) which deposits it as a thin film on a substrate (such as a silicon wafer facing the target). This process can occur in ultra high vacuum or in the presence of a background gas, such as oxygen which is commonly used when depositing oxides to fully oxygenate the deposited films.
While the basic-setup is simple relative to many other deposition techniques, the physical phenomena of laser-target interaction and film growth are quite complex (see Process below). When the laser pulse is absorbed by the target, energy is first converted to electronic excitation and then into thermal, chemical and mechanical energy resulting in evaporation, ablation, plasma formation and even exfoliation. The ejected species expand into the surrounding vacuum in the form of a plume containing many energetic species including atoms, molecules, electrons, ions, clusters,
particulates and molten globules, before depositing on the typically hot leakage current and enabling the ZnO TFT to operate successfully. The Ion /Ioff ratio of ZnO TFTs fabricated on Si wafers was more than 105 and the optical transmittance of ZnO TFTs fabricated on glass was more than 80%.
These results show that it is possible to fabricate a transparent TFT that can even be operated in the presence of visible light. But the deposition temperature of PLD is too high. It makes ZnO thin-film transistors fabricated by pulsed laser deposition not attractive for flexible electronics on temperature sensitive substrates.
2.2.4 ZnO TFTs Fabricated by Sol-Gel Process
The sol-gel process, known as a chemical solution deposition in atmospheric pressure[20], is a wet-chemical technique widely used in the fields of materials science and ceramic engineering. Such methods are used primarily for the fabrication of materials (typically a metal oxide) starting from a chemical solution which acts as the precursor for an integrated network of either discrete particles or network polymers. Typical precursors
are metal alkoxides and metal chlorides, which undergo various forms of hydrolysis and polycondensation reactions.
In this chemical procedure, the 'sol' (or solution) gradually evolves towards the formation of a gel-like diphasic system containing both a liquid phase and solid phase whose morphologies range from discrete particles to continuous polymer networks. In the case of the colloid, the volume fraction of particles (or particle density) may be so low that a significant amount of fluid may need to be removed initially for the gel-like properties to be recognized. This can be accomplished in any number of ways. The simplest method is to allow time for sedimentation to occur, and then pour off the remaining liquid. Centrifugation can also be used to accelerate the process of phase separation.
Removal of the remaining liquid (solvent) phase requires a drying process, which is typically accompanied by a significant amount of shrinkage and densification. The rate at which the solvent can be removed is ultimately determined by the distribution of porosity in the gel. The ultimate microstructure of the final component will clearly be strongly influenced by changes imposed upon the structural template during this phase of processing.
Afterwards, a thermal treatment, or firing process, is often necessary in order to favor further poly-condensation and enhance mechanical properties and structural stability via final sintering, densification and grain growth.
One of the distinct advantages of using this methodology as opposed to the
more traditional processing techniques is that densification is often achieved at a much lower temperature. Sol-gel process was shown in figure 2-9.
The precursor sol can be either deposited on a substrate to form a film, cast into a suitable container with the desired shape, or used to synthesize powders. The sol-gel approach is a cheap and low-temperature technique that allows for the fine control of the product’s chemical composition. Even small quantities of dopants, such as organic dyes and rare earth elements, can be introduced in the sol and end up uniformly dispersed in the final product. It can be used in ceramics processing and manufacturing as an investment casting material, or as a means of producing very thin films of metal oxides for various purposes.
ZnO films deposited by sol-gel process for TFTs need a thermal treatment over 500℃ to make the grains size becoming larger as shown in figure 2-10. It makes ZnO thin-film transistors fabricated by sol-gel not attractive for flexible electronics on temperature sensitive substrates. The TFTs fabricated by sol-gel have a field effect mobility about 0.5~1 cm2/V s and an on-off ratio 104 ~106 in previous literatures. We find some devices fabricated by different methods data which is listed in table 2-1.
Figure 2-1 (a) Top Gate Structure (b) Bottom Gate Structure
(a) (b)
Figure 2-2(a)PMOLED (b) PMOLED Control Circuit
(a) (b)
Figure 2-3(a)AMOLED (b)AMOLED Control Circuit
Figure 2-4 ALD four steps
Figure 2-5 ZnO TFT fabricated by ALD
Figure 2-6 Magnetron sputtering
Figure 2-7 ZnO TFT fabricated by RF magnetron sputtering
Figure 2-8 Pulsed laser deposition
Figure 2-9 Sol-gel process
(a) 600℃ treatment (b) 700℃ treatment
(c) 800℃ treatment (d) 900℃ treatment
Figure 2-10 ZnO deposited by Sol-gel process with thermal treatments
Table 2-1 Table of electrical properties and conditions
On-off
ratio
Mobility (cm2˙V-1˙S-1)
Temperature (℃℃℃℃)
Condition
ALD 105~107 2~15 <100℃℃℃℃ Vacuum
RF
Sputtering
104~107 1~10 <50℃℃℃℃ Vacuum
Pulsed Laser
104~106 1~5 400 ℃℃℃℃ Vacuum
Sol-gel 103~105 <1 500 ℃℃℃℃ Atmosphere Pressure
Chapter 3 Experiments
3.1 Experimental Procedures
The experimental procedures listed below:
Figure 3-1 Schematic illustration of experimental procedures.
3.1.1 ZnO deposited by APP jet on Si wafer
In our Literature Reviews, the fabrication and properties of bottom gate type thin film transistors using an intrinsic ZnO film as active layers will be described. We chose bottom gate structure to be the fabrication of TFTs on n+type silicon wafer as substrate. We usually adopt bottom gate structure in advanced TFTs fabrication for better quality of semiconductor active layer than top gate structure because the active layer is deposited after gate dielectric layer and drain or source electrode. Using this structure avoids plasma bombarding or thermal treatment injuring active layer .Silicon wafer was TFTs gate electrode, and we chose n+type silicon wafer for lower gate electrode resistance and bias voltage in gate electrode than n-type Si wafer.
After RCA clean procedure, silicon wafer was put in furnace for oxidation process. Silicon dioxide was chosen as the gate insulator. And the thickness of gate insulator was 1000Å. Temperature of thermal oxidation was 1000℃ with 90minutes. We chose this slightly thick thickness because we did not want the gate leakage current to influence device I-V properties.
And then ZnO thin film was deposited by APP jet as active layer with the deposition conditions including hot plate temperature, ZnO thickness, different kinds of main gas and carrier gas, different ratios of oxygen in main gas.
We needed to find out the suitable deposition conditions for promoting the quality of zinc oxide deposited by APP jet. To fabricate ZnO TFTs with good electric properties and high transparence was our goal. So the
procedure of ZnO deposited by APP jet was the most important step in TFT fabrication.
The zinc oxide thin films were deposited by APP jet as shown in figure 3-2 (the sketch of diagram isn’t proportioned to the real size of equipment). N+ silicon wafers were placed on hot plate with suitable process temperature. Zn(NO3)2 water solution was used as the precursors to deposit ZnO thin film. The concentration of Zn(NO3)2 water solution was 0.2M . We chose a suitable gap distance as 5mm to deposit ZnO thin film with good quality. The carrier gas carried mists of Zn(NO3)2 water solution to the plasma region. The carrier gas and mists of Zn(NO3)2 water solution were mixed with main gas, and these gases would become plasma by arcing mechanism because of high pulsed voltage. Zn(NO3)2 , H2O, carrier gas, and main gas would participate with some reactions in plasma region. And then main gas would carry these plasmas to substrate and reduce the plasmas temperature. We could use a computer to control scanning path including starting point and terminal point. The scanning path was shown in figure 3-3.
The main gas carried plasmas to substrate and the zinc oxide films were deposited by chemical vapor deposition.
Chemical vapor deposition (CVD) is the process of depositing a solid film on the wafer surface through one or more volatile precursors, which react or decompose on the substrate surface to produce the desired deposit.
Frequently, volatile by-products are also produced, which are removed by gas flow through the reaction chamber. The sample surface or its vicinity is heated in order to provide additional energy to the system to drive the
reactions. The plasma and radicals would cause reactions and nucleation on samples, and then zinc oxide films would grow from island shape to continuous films.
The experimental parameters of APP jet are shown in table 3-1. The thickness of active layer(scan times), hot plate temperature, carrier gas, and main gas are experimental parameter which we would change in order to discuss the influences to devices and to find out the best parameters for electrical properties. We would use these parameters to fabricate devices on glass substrate. Other experimental parameters are suitable for high quality films so we would not change them during each experiment like gap distance, gas flow rate, and nozzle speed.
3.1.2 Patterning
After ZnO deposited, the next step was to define each TFT’s active layer region. This procedure was carried out in lithography area by photo resist completely, the next step was to define drain and source electrodes . At the first we though the procedures of defining drain and source electrodes were depositing aluminum and etching it by lithography and wet etching. But the active layer was under drain and source electrodes. It is very difficult to
choose suitable acid solution which kept good etching selectivity between aluminum and zinc oxide. Zinc oxide would be etched very quickly by all acid solution which would etch aluminum. So we used a special technique to replace etching process to define drain and source electrodes on active layer.
This special technique was lift-off. The procedures of TFTs fabricated on n+
silicon before lift-off process as shown in figure 3-5. These procedures contained thermal oxidation, ZnO thin films deposited by APP jet, and defining active layer region by lithography technique.
3.1.3 Lift-off
Lift-off process contains several steps as shown in figure 3-6. First we put photo resist as a cover over zinc oxide region which we did not want aluminum deposited. And then we used E-Gun to deposit aluminum about 1000Å on Si wafer. At last, we put Si wafer in acetone with ultrasonic shaking to lift off all photo resist and aluminum on it. So a part of aluminum would stay on active layer as drain and source electrodes. And the device as shown in figure 3-7 would be measured electrical properties and the results would be discussed in next chapter.
3.2 TFTs fabricated on glass substrate
After we found out the best parameters to fabricate zinc oxide active layer in TFTs on silicon substrate, we tried to fabricate devices on Asahi display glass substrate AN100. If the devices on glass substrate could work and still has high performances, we could prove that our experiments are feasible for real and mass manufacturing. The ZnO TFT structure is shown in figure 3-8.And the patterns on mask are shown in figure 3-9. The ZnO TFTs on glass substrate are shown in figure 3-10.
At first TaN 50nm was deposited by sputter on glass substrate as gate electrode, and then we defined the gate electrode region by first mask. We reduced the area of gate electrode to reduce RC time delays.
The reason of using TaN to replace Al is that TaN has better thermal stability. It was very important because the next PECVD process would be proceeded in high temperature(400 ℃ ) conditions. And then we used PECVD to deposit SiN：H (210nm) as the gate insulator. The thickness of SiN：H was chosen because the capacitance of gate insulator would be same to the capacitance of thermal oxide. The reason of using SiN：H to replace SiO2 being gate insulator is the thickness of SiN：H thicker than SiO2 with the same capacitance because of SiN：H has larger dielectric constant than SiO2.
In this way, the gate leakage current would reduce because of thicker gate insulator. Another reason is there is many hydrogen in SiN：H because the raw materials of depositing SiN：H in PECVD are SiH4 and NH3. The
hydrogen in SiN：H would defuse to zinc oxide as donors. Donors near the interface of gate insulator and active layer could reduce the threshold voltage of device[21]. And then we defined gate insulator region by second mask.
The active layer, drain electrode, and source electrode were defined by the same methods of TFTs on silicon substrate. We used the third mask to define active layer region and the forth mask to define drain and source electrodes region including lift-off process.
3.3 Material analysis equipments 3.3.1 SEM
The scanning electron microscope (SEM) is a type of electron microscope that images the sample surface by scanning it with a high-energy beam of electrons in a raster scan pattern[22]. The electrons interact with the atoms that make up the sample producing signals that contain information about the sample's surface topography, composition and other properties such as electrical conductivity.
The types of signals produced by an SEM include secondary electrons,
The types of signals produced by an SEM include secondary electrons,