Due to escalating use of computer, personal notebook, mobile capabilities and electronic portable equipment nonvolatile semiconductor memory (NVSM) are increasingly high demand. The floating gate (FG) non-volatile memory was invented by S.M. Sze and Dawon Kahang in April 1967 with five layers, including control gate, blocking oxide, floating gate, tunneling oxide and semiconductor, as shown in Fig.
1.3(a) [1.10]. The electron trapped inside floating gate creates a built-in electric field that provides an electric force leading to electrons tunneling back to channel.
According to research, tunneling oxide thinner than 4nm can perfect avoid point defects trapping tunneling electrons. In fact, fabricating free defect oxide is impossible. In addition, Probability of Frenkel-Poole emission and direct tunneling occurrence increase as tunneling oxide thickness decreasing. Therefore, floating gate memories require tunneling oxide thickness about 8nm to 11nm resulting in big scaling down hinders beyond 40nm node technology as shown in Table 1.1 [1.11-1.13]. The SONOS type memory which replaced floating gate layer by nitride with discrete traps has been proposed. The electrons are stored in silicon nitride between blocking oxide and tunneling oxide as shown Fig. 1.3(b). The thinner tunneling oxide of SONOS memory can be achieved due to discrete trapping states [1.14-1.17]. Thus, SONOS type memories present longer retention time lower voltage
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operation faster program/erase speed and compatible to CMOS technology. It has high potential in NVSM market.
1.1.3 Bottom Gate and Top Gate Devices
As far as to now, enhancing field effect mobility, decreasing process temperature and developing strategies to reduce the carrier density in the channel are important issues. Changing devices structure is one of common ways. Many papers have compared the difference between top gate and bottom gate devices, as shown in Fig. 1.4 [1.9]. The performance characteristic of the top-gate and the bottom gate TFTs are quite different. The critical channel region in the top-gate TFTs is the surface layer of the Si film which causes significant surface roughness due to large lateral grain growth. This phenomenon results in diminished and non-uniform device performance for the top-gate TFTs [1.18].
For bottom gate devices, the main challenge is cannot self-alignment. So the application of bottom gate device is seriously limited. However, there are many methods have been proposed by performing lithography through the backside of a transparent substrate to solve this problem. The lithography independent self-alignment bottom gate TFT (SABG-TFT) technology is also been reported and experimentally demonstrated [1.18]. Besides, bottom gate devices have higher circuit density and better topography than top gate devices, it still has a great potential.
1.2 Silicon NanoCrystal (Si-NCs) Technology
The metal-oxide-semiconductor (MOS) memory structures based on nanocrystals (NCs) have exhibited faster programming and erasing speed, simple fabrication process and great retention, thus attracting much research attention. The Si-NCs can
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be formed in Si-rich SiN𝑥 layers using different chemical vapor deposition (CVD) techniques or by low energy silicon implantation technique. The reliability of nanocrystal memories depends on their thermal properties, work function, average size, and density. Electrons are trapped inside nanocrystals which isolate to others and stable confine in the well creating by the trapping layer and nanocrystals work function difference. Recently, the Si, Ge, high-k dielectric, metal, silicide and metal oxide are used for storage node application in the NCs non-volatile memory device.
The NCs memory devices can fabricate the thinner tunneling oxide due to discrete trapped states. On the other hand, the deep trapped level states of nanocrystals could future promote data retention [1.19].
Chiang et al. [1.20] invented in situ embedded silicon nanocrystals in silicon nitride method and found 30s SiCl2H2 deposition having maximum trapping cross areas (product of dot size and dot density). We used this method on bottom gate TFT-SONOS memory and characterized it electrical properties.
1.3 Metal Induced Lateral Crystallization (MILC) Technology
Poly-Si deposition usually occurs at high temperature (≥ 550℃) and unwanted nucleation is kept at a maximum during crystal growth resulting in rough films.
Fortunately, for silicon, the nucleation activation energy is higher than the crystallization energy. In other words, a high temperature is needed to form nuclei while a lower temperature is sufficient to cause their growth into a crystal. So keeping a low number of nuclei during a low temperature anneal allows crystal growth but suppresses additional homogeneous nucleation and nucleation at the α-Si substrate interface. External agents like metal or Germanium can be used to cause nucleation at controlled locations using low temperature.
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In MIC of α-Si, certain metals are used to lower the crystallization temperature. A summary of various MIC experiments is given in Table 1.2. In 1992, Hayzelden et al.
[1.6] formed NiSi2 by a Ni implant and 400℃ anneal. Upon further annealing of films at 500℃, they observed a silicide mediated phase transformation of α-Si to crystalline silicon (c-Si). This lateral crystallization is mediated by the silicide formed in the MIC region. NiSi2 precipitates migrated through the α-Si leaving a trail of c-Si and growth occurred parallel to the <111> direction. Hence, MILC is called a catalytic phase transformation, and poly crystals formed via MILC are free from metal contamination. When Ni is used as a catalyst for MILC, the growth rate are about 5 𝑚⁄ at a temperature of 550℃ and 2 𝑚 ⁄ at 500℃ [1.9]. The crystallization
obtained by this method presenting long growth length along unidirectional. This was the first observation of MILC [1.21].
The schematic diagram of MILC mechanism is shown in Fig. 1.5 [1.22]. The needle-like crystal growth during MILC utilizes the lateral migration of metals to enhance the grain size. This method is able to produce poly-Si thin film largely under a low temperature about 500℃, free of metal contamination and low cost; therefore, good quality poly-Si is available and highly efficient poly-Si TFT can also be produced [1.21].
1.4 Dopant Activation
Dopant activation is the process of getting the desired electronic contribution from impurity species in a semiconductor host which is crucial way for obtaining high performance transistors [1.23]. The way is often applied on thermal energy following the ion implantation of dopants. As thermal annealing, the vacancies generate at elevated temperature facilitate the movement of dopants from interstitial to
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substitutional lattice site while damage from implantation process recrystallizes.
The mechanism of dopant activation can be related to rearrangement of silicon and dopant atoms which can get large grains and better devices performance.
1.5 Motivation
The image transport speed, brightness, resolution and 3-DIC performance are significant dependent on the carrier mobility of TFTs which means dependent on the crystallization (grain size) on silicon substrate. Generally, amorphous silicon (α-Si) TFTs have an electron mobility of around 0.5𝑐𝑚2/V∙sec. However, the electron mobility value can be increased up to more than 200𝑐𝑚2/V∙sec when the α-Si is crystallized into poly-Si [1.24]. In addition, poly-Si TFTs usually have defects at the grain boundaries in the channel region, which leads to degradation in device performance. This includes high threshold voltage, low mobility and high leakage current. It is believed that the electrical properties of the TFTs can be improved if the grain size of the poly-silicon can be enhanced and the number of grain boundaries in the channel region can be minimizes [1.25].
In addition, series resistance in transistors and contact resistivity increasing due to continued shrinking is the hurdles in improving drive current. Dopant activation technique is applied to decrease sheet resistance. The interesting application of silicon Nano-crystals, dopant activation and MILC techniques in TFT-SONOS memory is demonstrated and its effects on the reliability are analyzed in this thesis.
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1.6 The Purpose and Value of This Thesis
The past experiment has shown that MILC rate and the crystallization quality are sensitive to the doping type and concentration. Doping with phosphorus or arsenic and damage introduced during ion implantation are found to slow down the MILC rate and to degrade the film morphology, whereas heavy boron doping may showed opposite results [1.26]. T. Ma et al. purposed boron enhanced nickel diffusion phenomenon leading better crystallization quality [1.3]. However, Byun et al. found MILC migration decreased as boron doping before MILC process [1.2]. Whether boron enhanced or reduction MILC growth rate is an uncertain issue. We believe boron would enhance nickel diffusion and demonstrate this effect in SONOS memory.
In addition, enlarging grain size can reduce grain boundaries and intra-grain defects improving devices performance. Therefore, we use different boron doping concentration to examine MILC rate in the experiment. In this work, we systematically investigated the effect of boron dopant atoms on Si-NCs SONOS memory in the aspects of carrier transport with XRD analysis, programming/erasing speed, retention, endurance and sheet resistance measurements, hopefully also providing boron enhance diffusion effect is hold in Si-NCs SONOS memory devices.
1.7 Organization of This Thesis
Chapter 1 starts with an introduction on thin film transistors, bottom gate devices and SONOS memories; it also goes into the techniques of silicon nanocrystals, MILC, and dopant activation. Chapter 2 describes devices fabrication process of Si-NCs SONOS memory, measurement condition, operation machines and giving some theoretical basis of memories parameters. Continuing analysis in electrical characterizations and reliability of Si-NCs SONOS memory are proposed in chapter 3.
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Finally, the conclusions of this work and recommendations for future work are stated in chapter 4.
9 Table 1.1. Technology trends in ITRS 2012 [1.10]
Table 2.2 Summary of Metal Induced Crystallization (MILC) observations. [1.6]
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Fig. 1.1 The top graph is TFT array and color filter substrates which are made into an LCD panel by assembling then with a sealant; the bottom graph is the flowchart of making an amorphous silicon TFT array using a bottom gate TFT structure and an independent storage capacitor [1.1].
Independent Cs Design
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Fig. 1.2. Plan-view electron backscatter diffraction (EBSD) map color-coded with the IPF coloring in the SPC sample normal direction . The grain boundaries are highlighted with black lines and twins are highlighted with white lines [1.6].
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Fig. 1.3. The structure of (a) floating gate device.
Fig. 1.3. The structure of (b) SONOS devices.
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Fig. 1.4. The structure of (a) top gate device.
Fig. 1.4. The structure of (b) bottom gate devices.
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Fig. 1.5. A schematic illustration of the MILC reaction model [1.22].
(Si-Si bond breaking → Silicon atoms hopped to the interface between silicide and single crystalline silicon → Rearranging of the silicon atom to single crystalline silicon)
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Chapter 2
Si-NCs SONOS Device Fabrication and Experimental Setup
2.1 Overview
The poly-silicon material used in the channel of thin film transistor is composed of silicon crystallites (grains) separated by the regions with high density of impurities called grain boundaries. These grain boundaries present in the channel would scatter majority carriers lead to mobility significantly degradation. In addition, Carlo et al.
has also purposed mobility shows strong dependence of grain size [2.1-2.2]. In this work, we want to demonstrate boron enhanced nickel diffusion effect presenting large grain size. We investigate the feasibility of MILC process with different boron doping concentration on embedded Si-NCs SONOS memory in physical and electrical properties.
2.2 Experimental Method
Figure 2.1 to Fig. 2.7 show the schematic of the experimental processes diagrams of the in-situ embedded Si-NCs in silicon-nitride film Si-NCs SONOS memory.
Devices were fabricated on n-type (100) 150mm, 8-12 Ω-cm silicon substrates. First, the 500nm thermal oxide was grown on silicon wafer by furnace. Second, 150nm p+-poly-Si was deposited as the gate electrode with boron implantation (70keV, 5 ∗ 1015cm−2). After defining the active regions, the 20nm blocking oxide was thermally grown on p+-poly-Si. Third, in-situ embedded Si-NCs in silicon nitride film
16 e-beam evaporation and annealed at 520℃. Finally, the contact hole was patterned and 500nm Al was deposited to fabricate the Si-NCs SONOS memories.
2.3 Measurement and Equipment Setup
The measurement setup of this TFT-SONOS device is illustrated in Fig. 2.9, including the electrical characterization system (KEITHLEY 4200), two channel pulse generator (Agilent 8110), low leakage current switch mainframe (KEITHLEY 708A) and the probe station.
KEITHLEY 4200 equipped with programmable source-monitor units (SMU) and provides a high current resolution to pico-ampere range to facilitate the current measurement. Agilent8110A with two pulse channels provides the high timing resolution pulse for the P/E characterization of nonvolatile memory. KEITHLEY 708A configured a 10-input*12-output switching matrix, which can switches the signals from the KEITHLEY 4200 and Agilent 8110A when the device is measured in probe station. Moreover, C++ language is used to achieve the control of the devise measurement instruments.
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2.4 Operation and Parameter Extraction of TFT-SONOS Memory
2.4.1 Threshold Voltage
It means the amount of gate voltage required to increase or decrease drain current by one order of magnitude. The subthreshold swing presents devices gate control ability and number of trap states. [2.4-2.5] It might increase with drain voltage (lower gate control) due to short-channel effects such as charge sharing, avalanche multiplication, and punch through-like effect. And it is also relate to trap states due to dangling bonds and oxide defeats such as programming or erasing operation, stress and strain.
18 2.4.3 Source/Drain Resistance
In order to achieve the density and performance specifications of stat-of-the-art VLSI, MOSFEST’s channel length has been scaled down to nanometers range. To control the fabrication of these devices it is necessary to accurately determine channel length. Moreover, this knowledge is required for circuit designs whose performance mainly relies on the use of these scaled devices. In this thesis, La Moneda method [2.6]
was used to electrically determine channel length, mobility, and source/drain resistance. The model describes range of gate biases and channel lengths. Measurements from two gate biases on each of two devices of different channel length are sufficient to obtain a full characterization. Thus, the method is well suited for automated testing because of its simplicity and efficiency.
2.4.4 Fowler-Nordheim (FN) Mechanism
The Fowler-Nordheim (FN) is the flow of electrons through a triangular potential barrier illustrated in Fig. 2.10. FN tunneling mechanism occurs when applying a strong electric field across a thin oxide. In this thesis, the 20V is applied to the gate terminal and the voltage drop across the tunneling oxide make the electrons injecting from channel into trapping layer during programming; the -20V is applied to control gate and electrons detrap from trapping layer during erasing. Using a free-electron gas
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model for the metal and the WKB approximation for the tunneling probability, one obtains the following expression for current density [2.7-2.8]:
J = 𝑞3𝐹2
1 𝜋2 2𝜑𝐵exp [−4(2𝑚𝑂𝑋)1/2𝜑𝐵3/2
3 𝑞𝐹 ]
Where 𝜑𝐵 is the barrier height, 𝑚𝑂𝑋 is the effective mass of the electron in the forbidden gap of the dielectric, h is the Plank’s constant, q is the electronic charge, and F is the electric field through the oxide.
2.4.5 Pelgrom Plot
Dr. Pelgrom proposed and demonstrated the simple evaluation method of the random variation in 1989 as shown in Fig. 2.11. The method based on simple statistics which described as:
𝜎𝑡ℎ = 𝐴𝑉𝑇
√𝐿𝑊 [2.9]
AVT: the slop beteeen threshold voltage standard devition and device area square root W: channel width, L: channel length.
Since devices scale down, threshold voltage variation is a significant issue. Pelgrom plot can foretell the easy prospect of threshold voltage variation which uses generally.
2.4.6 Arrhenius plot
Arrhenius plot is used to analysis charge loss mechanism. It reported a retention time model with linear variations with temperature. The effective activation energy ( ) to confine the charge loss mechanism were estimated from
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= 𝜕𝐼𝑛𝑡𝑅
𝜕(1 𝑘𝑇)
Where T, 𝑡𝑅 and k are the temperature, the retention time and the Boltzmann constant, respectively. By extracting value, we can determine charge loss reasons from Table 2.1 [2.10].
2.5 Characteristic of Memory
2.5.1 Characteristic of Retention
Retention time describes the ability of devices to store charges after programming at a specific temperature. Generally, the retention time should more than ten years which means the amount of loss charge in storing region must be as minimal as possible. The previous study had reported that retention capability of SONOS memories has to be checked by using accelerated test such that high electric fields or high temperature [2.11-2.13]. In this work, we discuss data retention characteristic after programming with three different temperatures. (25℃, 75℃, 125℃) By measuring the threshold voltage variation, we can find the amount of the excess Time-Dependent-Dielectric-Breakdown (TDDB) characteristics of the charge transfer
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oxides used for erase and program. The other is threshold voltage level disturbance during program and erase cycles [2.15]. In this thesis, we would find the dominate factor for embedded Si-NCs SONOS memory and solve ways to extend the endurance time.
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Mechanism Activation Energy (eV)
Tunnel oxide breakdown ≈0.3
ONO ≈0.35
Oxide defects ≈0.6
Cycling induced charge loss ≈1.1
Ionic contamination ≈1.2
Intrinsic charge loss ≈1.4
Table 2.1. JOE E. Brewer reported the value and mechanism relation in 2007 [2.10].
Fig. 2.1. Thermal oxide was grown on silicon wafer, depositing 150nm amorphous silicon and annealed to poly-silicon.
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Fig. 2.2. Gate was defined and implanted boron with 5 ∗ 1015𝑐𝑚−2 dosage.
Fig. 2.3. Blocking oxide was deposited and used in-situ technique to embed Si-NCs in nitride film, as shown in Fig. 2.2.
24 Fig. 2.4. Tunneling oxide was deposited.
Fig. 2.5. Amorphous silicon was deposited which made as device channel.
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Fig. 2.6. Active region was defined and implanted with boron dosage. 1 ∗ 10𝟏𝟓𝑐𝑚−𝟐 and 5 ∗ 10𝟏𝟒𝑐𝑚−𝟐.
Fig. 2.7. Using MILC technique at 520℃, amorphous silicon was recrystallized to poly-silicon.
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Fig. 2.8 The schematic diagram shows gas flow of in-situ deposition of Si-NCs in nitride [2.3].
Fig. 2.9 The experimental setup for the transfer characteristic and program/erase characteristic of SONOS with Si nanocrystals memory.
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Fig. 2.10 A schematic of the FN tunneling during programming (left) and erasing (right) in the electric field.
Fig 2.11 Different oxide thickness present in Pelgrom plot. If 𝐴𝑣𝑡= 3.8, then 7nm oxide thickness will have about 400mV variation in threshold voltage. If we want to variation smaller than 100mV, than 𝐴𝑣𝑡value should be choose smaller than one. [2.9]
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Chapter3
Characteristics of Si-NCs-SONOS Nonvolatile Memory 3.1 Overview
T. Ma et al. reached a conclusion regarding the effect of implantation boron before MILC process which stated the MILC migration rate will double at 550℃ as boron doping concentration 3 ∗ 1015𝑐𝑚−2 in 1000Å non-crystalline silicon film. [3.1]. Lu et al. has reported 𝑁𝑖𝑆𝑖2 formation at a much lower temperature of 250℃ in heavily boron doped Si. This implies that heavy boron doping effectively reduces the formation energy of NiSi2. So any retardation effects induced by implantation damage are somehow compensated due to boron enhancement effect. However, C.
Byun et al. found that the MILC migration rate showed a decrease as using boron doping comparing to un-doped α-Si. The decrease in the MILC migration rate results from disturbance of dopant migration through segregation and dopant on NiSi2 layer [3.2-3.3].
We curious about boron would enhance or retardate the nickel diffusion and this
effect would hold in the memory devices. Therefore, we designed two different boron doping concentration (5 ∗ 1014𝑐𝑚−2, 1 ∗ 1015𝑐𝑚−2) devices with MILC process to
analyze their physical and electrical properties. In addition, we choose 30s Si-NCs deposition time in SONOS memory for studying standard. Since T.Y. Chuang has reported 30s deposition time Si-NCs SONOS memories show excellent electrical performance, we can decrease other influence factor in memories characteristics [3.4-3.7]. The AFM and TEM Si-NCs graphs are shown in Fig. 3.1 and Fig. 3.2.
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3.2 Source/Drain Doping Dependence
3.2.1 X-ray Diffraction (XRD) Analysis
The atomic planes of a crystal cause an incident beam of X-rays to interfere with one another as they leave the crystal. The phenomenon is called X-ray diffraction (XRD). XRD is a nondestructive technique which can identify crystalline phases, crystalline orientation and grain size. As grain size decreases hardness increases and intensity (peaks) become broader [3.8]. Table 3.5 and Fig. 3.3 show the XRD results of poly-silicon channel with different boron doping (5 ∗ 1014𝑐𝑚−2, 1 ∗ 1015𝑐𝑚−2) devices. The average grain size of high to low boron doping device ratio is 2.4.
The atomic planes of a crystal cause an incident beam of X-rays to interfere with one another as they leave the crystal. The phenomenon is called X-ray diffraction (XRD). XRD is a nondestructive technique which can identify crystalline phases, crystalline orientation and grain size. As grain size decreases hardness increases and intensity (peaks) become broader [3.8]. Table 3.5 and Fig. 3.3 show the XRD results of poly-silicon channel with different boron doping (5 ∗ 1014𝑐𝑚−2, 1 ∗ 1015𝑐𝑚−2) devices. The average grain size of high to low boron doping device ratio is 2.4.