Chapter 6 Experimental Results
6.3 S UMMARY
The configurable I/O cell library has been designed and successfully fabricated in UMC 90-nm salicided CMOS process. The functions of the pull-up/pull-down, driving capacities, schmitt-trigger, and slew-rate control have been measured to verify its effectiveness. The ground bounce effects can be reduced greatly with the slew-rate control mechanism. The analog I/O and power cells have been verified its ESD robustness and it can effectively protect the core circuits and I/O output driver in UMC 90-nm CMOS technology for system-on-a-chip (SoC) applications.
The simulation and measurement results of pull-up/pull-down network.
Parameters Simulation Results Measurement Results
VDDIO
The simulation and measurement results of input stage threshold points.
Parameters Simulated
Measurement results of the driving capability under 2.5-V VDDIO supply voltage.
Measurement results of the driving capability under 1.8-V VDDIO supply voltage.
Parameters Measured Results
Measurement results of the driving capability under 3.3-V VDDIO supply voltage.
The operating frequency of the configurable I/O cell operating in transmitting mode with different driving current and VDDIO supply voltage.
VDDIO Driving Current
2mA 8mA 10mA 14mA 16mA 22mA 24mA
2.5V >66MHz >133MHz >266MHz >266MHz >266MHz >266MHz >266MHz 1.8V >10MHz >133MHz >133MHz >266MHz >266MHz >266MHz >266MHz 3.3V >66MHz >266MHz >266MHz >266MHz >266MHz >266MHz >266MHz
HBM and MM ESD robustness of the UVDD25 and UVDD10 cells.
*ESD level: maximum pass voltage before the chip failing
Tabel 6.8
HBM and MM ESD robustness of the UVSS25 cell.
ESD
HBM and MM ESD robustness of the UVSS10 cell.
ESD
HBM and MM ESD robustness of the 2.5-V analog I/O cells.
HBM and MM ESD robustness of the 1.0-V analog I/O cells.
ESD
HBM and MM ESD robustness of the power break cell.
ESD
HBM and MM ESD robustness of whole-chip protection with power break cell.
ESD Event HBM MM
Cell Name
ESD Stress Whole-Chip Protection with UPBREAK
VSS1-to-VSS2 (+) 3kV 300V
HBM and MM ESD robustness of configurable I/O cell with whole-chip protection.
ESD Event HBM MM
Cell Name
ESD Stress UCIONS UCIOS UINPUT UCIONS UCIOS UINPUT
I/O PAD-to-VSS (+)
> 5kV > 5kV > 5kV > 500V > 500V > 500V I/O PAD-to-VSS (-)
I/O PAD-to-VDD (+) I/O PAD-to-VDD (-) I/O PAD-to-VSSIO (+) I/O PAD-to-VSSIO (-) I/O PAD-to-VDDIO (+) I/O PAD-to-VDDIO (-)
Fig. 6.1 The test chip photograph of the configurable I/O cell library in UMC 90-nm CMOS process.
Fig. 6.2 The PCB view of tested chip.
(a)
(b)
Fig. 6.3 Measurement setup to verify the (a) pull-up resistance and (b) pull-down resistance.
(a)
(b)
Fig. 6.4 Measured waveforms of the (a) pull-up network and (b) pull-down network with 2.5-V VDDIO voltage supply.
(a)
(b)
Fig. 6.5 Measured waveforms of the (a) pull-up network and (b) pull-down network with 1.8-V VDDIO voltage supply.
(a)
(b)
Fig. 6.6 Measured waveforms of the (a) pull-up network and (b) pull-down network with 3.3-V VDDIO voltage supply.
(a)
(b)
Fig. 6.7 Measurement setup to verify input stage threshold points with (a) schmitt-trigger enable (SCHa = 1) and (b) schmitt-trigger disable (SCHa =0).
(a)
(b)
Fig. 6.8 Measured result of input stage with (a) schmitt-trigger enable (SCHa = 1) and (b) schmitt-trigger disable (SCHa =0) under 2.5-V VDDIO.
(a)
(b)
Fig. 6.9 Measured result of input stage with (a) schmitt-trigger enable (SCHa = 1) and (b) schmitt-trigger disable (SCHa =0) under 1.8-V VDDIO.
(a)
(b)
Fig. 6.10 Measured result of input stage with (a) schmitt-trigger enable (SCHa = 1) and (b) schmitt-trigger disable (SCHa =0) under 3.3-V VDDIO.
(a)
(b)
Fig. 6.11 Measurement setup to verify (a) low level output current (IOL) and (b) high level output current (IOH).
Fig. 6.12 Measurement setup to verify simultaneous switching noise (SSN).
(a)
(b)
Fig. 6.13 Measured waveforms of simultaneous switching noise (SSN) issue when the configurable I/O cell operating (a) without slew-rate control (UCIONS) and (b) with slew-rate control (UCIOS).
(a)
(b)
Fig. 6.14 The relation between ground bounce on the power/ground line and driving current with the UCIONS and UCIOS. (a) The undershoot on VDDIOchip power line and (b) the
Fig. 6.15 Measurement setup to test the propagation delay of the UCIONS (UCIOS) cell.
(a)
(b)
Fig. 6.16 Measured waveforms to test the propagation delay when the configurable I/O cell operating (a) without slew-rate control (UCIONS) and (b) with slew-rate control (UCIOS)
Fig. 6.17 Propagation delay comparison between measurement and simulation results of the propagation delay with 2.5-V VDDIO and different driving current.
Fig. 6.18 Propagation delay comparison between measurement and simulation results in different driving current and VDDIO supply voltage.
Fig. 6.19 Measurement setup to test the maximum operating frequency at the output stage of the configurable I/O.
(a)
(b)
(continue to next page, Fig. 6.20)
(c)
Fig. 6.20 Measured waveforms of the configurable I/O cell operating at 266M-Hz operating frequency and 24-mA driving current when receiving 0V-to-VDDIO input signals at pin Ib with (a) 2.5-V, (b) 1.8-V, and (c) 3.3-V VDDIO supply voltage.
Fig. 6.21 Testkey of configurable I/O cell with whole-chip protection circuit.
Fig. 6.22 Protective extend test of whole-chip protection circuit.
Chapter 7
Conclusions and Future Works
7.1 CONCLUSIONS
In this thesis, a set of configurable I/O cell library has been designed to accelerate the design process to achieve the time-to-market requirement, and has been successfully verified in UMC 90-nm salicide CMOS process. The proposed I/O cell library can be applied in the 1.0-V core power supply voltage, 2.5-V/1.8-V/3.3-V I/O output driver power supply voltage with the operating speed of up to 266MHz. The configurable I/O cell of this library can provide 7 different selective driving currents in transmitting mode, an input stage with or without the function of the schmitt-trigger in receiving mode, and function of the pull-up or pull-down in tri-state. The configurable I/O cell with slew-rate control can effectively reduce the ground bounce effects. Furthermore, each of the ESD protection circuit has been successfully verified its ESD robustness in the test chip. Under the normal circuit operating condition, the I/O cells with the whole-chip protection circuit can be operated correctly. Under the ESD stress conditions, the whole-chip ESD protection circuit can effectively protect the core circuits. Thus, this I/O cell library can be applied in the CMOS ICs inside the microelectronic products successfully.
Since the configurable I/O cell is designed with an operating speed of up to 266MHz, the transmission line effect should be considered. Thus, the transmission model should be added into simulation to achieve more accurate results. Beside, the dimensions of ESD protection diodes in the 1.0-V power domain should be enlarged to further improve ESD level of the power break cell.
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