P OWER B REAK C ELL

To overcome the unexpected ESD damage located at the internal circuit, adding the bi-directional diode between the separated power lines of the CMOS IC has been reported [26]-[28]. The design of such bi-directional diode in this thesis is defined as UPBREAK cell

of the CMOS IC. The UPBREAK cell is designed to conduct the ESD current between the separated power lines to avoid the ESD damage located at the internal circuits under the ESD stress condition. When the IC is in the normal operating condition, the UPBEAK cell is designed to block the noise between the separated power lines.

Fig. 3.1 Typical on-chip ESD protection circuits in a CMOS IC.

Fig. 3.2 Whole-chip ESD protection scheme.

(a) (b) Fig. 3.3 Circuit diagram of (a) UVDD25, (b) UVDD10 cells.

(a)

(b)

Fig. 3.4 Simulated results of UVDD25 and UVSS25 cells under (a) power-on condition and (b) ESD stress condition.

(a) (b) Fig. 3.5 Circuit diagram of (a) UVSS25, and (b) UVSS10 cells.

(a)

(b)

Fig. 3.6 Simulated results of UVSS25 cell under (a) power-on condition and (b) ESD stress condition.

(a)

(b)

Fig. 3.7 (a) Layout view and (b) device structures of the I/O cell with double guard rings inserted between input (or output) PMOS and NMOS devices.

(a)

(b)

Fig. 3.8 Circuit diagram of (a) UAIO25 and (b) UAIO10 cells.

Fig. 3.9 Circuit diagram of power break cell.

Chapter 4

Physical Layout of Configurable I/O Cell Library

4.1 CONFIGURABLE I/O CELL WITH SLEW-RATE CONTROL

Fig. 4.1 shows layout implementation of the configurable I/O with slew-rate control cell (UCIOS) and the power line. The power line is drawn with from metal 4 (M4) to top metal (M9). Fig. 4.2 shows the cross section view of bond pad which is used with BOAC (bond over active circuit) structure. And the corresponding layer names are listed in Table 4.1.

Furthermore, the particular block layout views of the UCIOS cell are shown in Fig. 4.3. The difference in physical layout between configurable I/O without slew-rate control cell (UCIONS) and with slew-rate control cell (UCIOS) is the drawing of slew-rate control. As shown in Fig. 4.4, the drain and source terminals of transmission gates are all connected to VSSIO. The gates of NMOS are connected to VSSIO through a resistance, and that of PMOS are connected to VDDIO through a resistance. Thus, the function of the slew-rate control can be turned off when the UCIONS is in normal operation.

4.2 POWER/GROUND CELLS AND ANALOG I/O CELLS

Fig. 4.5(a) shows the layout implement of the UVDD25 cell. In this layout view, only layers below the layer via3 (including the layer via3) are shown, and the other layers not shown are the routing of the power line. The cell width and hight are as same as the I/O cells.

only different between two cells. Fig. 4.5(b) and (c) show the layout implements of the UVSS25 and UVSS10 cells which are designed in gate-couple and STSCR technique, respectively. The layout-top-views of the UAIO25 and UAIO10 cells are shown in Fig. 4.6.

Furthermore, the device layout of STSCR drawn in UVSS10 and UAIO10 cells is shown in Fig. 4.7. The STSCR structure is formed with construction between P+ diffusion of Anode and N+ diffusion of Cathode.

4.3 POWER BREAK CELL

Fig. 4.8 shows the layout of power break cell (UPBREAK). Its cell height is as same as the I/O cells, but the cell width is drawn with 43.97m. The power break cell is composed of bidirectional diode to disconnect two groups of power lines.

4.4 FILLER AND CORNERCELLS

Fig. 4.9 shows the layout-top-view of the filler cells (UFeederXX). The filler cells are used to fill the empty space between the I/O cells. It would connect the power lines to provide a continuous power supply. There are nine different sizes (0.1-m, 0.3-m, 0.5-m, 1-m, 2-m, 5-m, 10-m, 15-m, and 20-m) of the filler cells provided in the I/O cell library.

And Fig. 4.10 shows the layout-top-view of the corner cell (UCorner). It provides a connection between the power and ground rails in die corner areas.

Layer name definition of bond pad.

Layer Name Description

Metal 9 Define 9th Cu metal

TMV_RDL (L1) Define top-metal-and-Al-pad-contacts

AL_RDL (L2) Define Al pad

PASV_RDL (L3) Define Al pad window region

(a)

(b)

(c)

Fig. 4.1 (a) Layout implementations of configurable I/O with slew-rate control cell (UCIOS) and power line. (a) Configurable I/O cell, (b) power line and (c) complete layout implementation.

Fig. 4.2 Cross section view of bond pad.

(a)

(b)

Fig. 4.3 Block layout views of configurable I/O with slew-rate control cell (UCIOS).

(a) Pre-driver, level shifter, input stage, pull-up/pull-down network and slew-rate control;

Fig. 4.4 Slew-rate control circuit layout of configurable I/O without slew-rate control cell (UCIONS).

(a) (b) (c)

Fig. 4.5 Layout-top-view of (a) UVDD25, (b) UVSS25, and (c) UVSS10 cells.

(a) (b)

Fig. 4.6 Layout-top-view of (a) UAIO25 and (c) UAIO10 cells.

Fig. 4.7 Layout-top-view of STSCR drawn in UVDD10 and UAIO10 cells.

Fig. 4.8 Layout-top-view of UPBREAK cell.

Fig. 4.9 Layout-top-view of UFeeder01, UFeeder03, UFeeder05, UFeeder1, UFeeder2, UFeeder5, UFeeder10, UFeeder15, and UFeeder20 cells.

Fig. 4.10 Layout-top-view of corner cell (UCorner).

Chapter 5

Test Chip Arrangement of Configurable I/O Cell Library

5.1 VERIVICATION ON CONFIGURABLE I/OCELL

The definitions of test circuits for function verification are listed in Table 5.1. The function test circuit function 1 (TC_F1) is used to verify the pull-up/pull-down resistance. The TC_F2 and TC_F3 are used to verify the threshold points of schmitt-trigger and driving capability, respectively. The main unit of TC_F4 is the configurable I/O cell with slew-rate control (UCIONS), and that of TC_F5 is with slew-rate control (UCIOS). The SSN and propagation delay can be measured by these two test circuits.

5.1.1 Pull-Up/Pull-Down Resistance (TC_F1)

The test circuit of pull-up/pull-down resistance of configurable I/O cell is shown in Fig.

5.1. Five input cells (UINPUT) are placed between the input signal pins (Ia, Sa, PUa, PDa, and SCHa) and control-signal pins (I, S2, S1, S0, PU, PD, and SCH) to enhance the ESD robustness significantly. Fig. 5.2 depicts the input cell (UINPUT) defined as configurable I/O with slew-rate cell (UCIOS) biased all control-signal pins (I, S2, S1, S0, PU, PD, and SCH) at 0V. In Fig. 5.1, the control-signal pins S2, S1, and S0 are connected commonly to become an enable signal. The UCIOS cell will be in tri-state while the pin Sa receives a logic-0 signal and in transmitting mode while the pin Sa receives a logic-1 signal. When PUa, PDa, and SCHa are set to a high voltage level, the functions of pull-up, pull-down, and schmitt-trigger

voltage level, the functions will be switched off. Note that the functions of pull-up and pull-down should not be turned on at the same time, because it will make a short circuit in the test circuit.

Fig. 5.3 shows the simulated waveforms of pull-up and pull-down resistance. In Fig.

5.3(a), the input signal Sa receives the input signal of 0-to-1.8V, 0-to-2.5V, and 0-to-3.3V with the corresponding VDDIO supply voltages, respectively, and the input signal I receives a DC signal of 0V. The I/O PADa is biased at 0V when the input signal Sa receives the logic high level, and the configurable I/O (UCIOS) cell is in transmitting mode simultaneously.

When the input signal Sa receives a 0V signal to trigger the pull-up network, the UCIOS cell is in tri-state causing the I/O PADa at logic high with a rise time (T_r) of 1.03s closely.

Besides, in Fig. 5.3(b), the input signal Sa receives the same input signal waveform, but the input signal I is biased at logic high level. When the input signal Sa receives the logic high level, the UCIOS cell operates in transmitting mode so that the I/O PADa is biased at the same voltage level as input signal Sa. While the input signal, Sa, receives a 0V input signal to trigger the pull-down network, the UCIOS cell is in tri-state causing the I/O PADa at 0V with a fall time (T_f) of 1.03s closely.

5.1.2 Schmitt-trigger Threshold Points (TC_F2)

To save layout area, the test circuit shown in Fig. 5.1 is used to measure not only pull-up/pull-down resistance, but also low-to-high/high-to-low threshold voltages (V_T+/V_T-) of schmitt-trigger input stage in configurable I/O cell. The input signal pin SCHa is used to control the function of schmitt-trigger switching on (off) with a high (low) level voltage. In order to enhance ESD robustness, the output signal pin, C, of the configurable I/O cell

capacitance that will not affect pin C.

Fig. 5.4, Fig. 5.5, and Fig. 5.6 shows simulation results for voltage-transfer curve (VTC) of configurable I/O cell under different VDDIO supply voltages. The waveforms of output signal pin, C, is simulated while the I/O PADa is swept from logic low to high and then return to its initial voltage level. According to the simulation waveforms shown in Fig. 5.4, Fig. 5.5, and Fig. 5.6, the threshold voltages are listed in Table 5.1. The VT+/- is defined as the voltage level of I/O PADa while the voltage level of C is VDD/2 with the function of schmitt-trigger (SCHa = 1). The VT+ is I/O PADa transmitted from low to high, and the VT- is that from high to low. The V_TH is defined as the voltage level of I/O PADa while the voltage level of C is VDD/2 without the function of schmitt-trigger (SCHa = 0).

5.1.3 Driving Capability (TC_F3)

Test circuit for driving capability of configurable I/O cell is shown in Fig. 5.7. Ib, S0b, S1b, and S2b are input signal pins. The pull-up, pull-down, and schmitt-trigger functions are turned off in this test circuit. To save layout area, the control-signal pins I, S0, S1, and S2 are connected to the points Ia_in, Sa_in, PUa_in, and PDa_in shown in Fig. 5.1. The input cells (UINPUT) are used commonly in test circuits TC_F1 and TC_F3.

Table 5.3, Table 5.4, and Table 5.5 list the simulation results of driving capability in different VDDIO supply voltages. In this simulation, the input signal S2b, S1b, and S0b are changed from 001, 010, 011……to 111 to transform driving current from 2mA, 8mA, 10mA……to 24mA. While the input signal Ib receives logic low level, a sink current is produced at I/O PADb. Furthermore, when the voltage at I/O PADb is biased at V_OL = 0.4V, the sink current is defined as I . Oppositely, while Ib receives logic high level, the source

VDDIO_(min) – 0.4V, the source current is defined as I_OH.

5.1.4 Simultaneous Switching Noise (SSN) and Propagation Delay (TC_F4 & TC_F5)

In actual application, when a lot of I/O cells are switched simultaneously with a joint set of power cells, it will cause serious simultaneous switching noise (SSN). As a result, the comparisons of SSN and delay time between configurable I/O cells with and without slew-rate control (UCIOS and UCIOINS) have to be measured. From the measured results, the ability of slew-rate control in SSN issue reduction can be verified. Fig. 5.8 shows the method of SSN measurement, the noise on the power lines can be measured from pure VDDIO and VSSIO cells while 17 cells switched simultaneously. The I/O pad name of pure VDDIO and VSSIO cells are denoted VDDIOchip and VSSIOchip, respectively.

Since the delay time of single I/O cell is too short, it cannot be measured accurately.

Hence, the multiple-stage I/O cells consisted of I/O cell chain are also used to analyze the delay of single-stage I/O cell as shown in Fig. 5.9. There is no mechanism to turn on or off the input stage of configurable I/O cell. Thus, when these I/O cells is operating in transmitting mode, the signal at the pin I (VSS-to-VDD) will be transmitted to I/O PAD (VSSIO-to-VDDIO) through the output stage. Then the signal will be transmitted to output signal C (VSS-to-VDD) through the input stage. Besides, the output signal C of a configurable I/O cell is associated with the input signal I of the next configurable I/O cell as an input signal pin. Then, an I/O chain (17 I/O cells) can be constructed. Therefore, the data of the PADn1/PADs1 will be transmitted to the PADn17/PADs17 through the I/O cell chain progressively when these I/O cells are operating in transmitting mode. Moreover, an inverter is inserted between the last configurable I/O cell and the first one to form a ring-oscillator.

pull-up, and pull-down. And all the signal, S2, S1, and S0, are connected to input cells individually and denoted the input signal pins as Sn2/Ss2, Sn1/Ss1, and Sn0/Ss0, which control the driving capability to change the oscillatory frequency. When the input signal Sn2/Ss2, Sn1/Ss1, and Sn0/Ss0 are received 0V input signal simultaneously, the ring-oscillator will be turned off and make no output signal at all the I/O PAD of configurable I/O cells. Thus, to measure the delay time from PADn1/PADs1 to PADn17/PADs17 can infer the propagation delay of single I/O cell. Consequently, such test circuit show in Fig. 5.9 can measure the SSN and the propagation delay.

In order to verify the reduction of ground bounce by slew-rate control, a model for ground bounce effects is shown in Fig.5.10. The inductances of wire bonds vary from 3nH to 9nH in the simulation for pseudo worst case with 24mA driving capability and a load capacitance of 12pF which can result in close results to actual conditions in this part. Since the switching currents of configurable I/O cells in transmitting mode are much larger than that in receiving mode, the ground bounce effects are simulated in transmitting mode for clear illustration. The simulation waveforms of ground bounce effects on power lines are shown in Fig. 5.11 and several parameters are defined as follows:

 VDDIO_ext/VSSIO_ext: External power supply;

 VDDIOchip_max/VDDIOchip_min: maximon/minimum value of VDDIOchip power line;

 VSSIO_{chip_max}/VSSIO_{chip_min}: maximon/minimum value of VSSIO_chip power line;

 ΔVVDDIOchip_over: overshoot on VDDIOchip power line (VDDIOchip_max - VDDIOext);

 ΔVVDDIOchip_under: undershoot on VDDIO_chip power line (VDDIO_ext - VDDIO_{chip_min});

The ΔVVDDIOchip_under and ΔVVSSIOchip_over among these parameters are the major concerns since these two terms may result in increasing timing delay and even logic errors on transmitted signals.

The simulation waveforms of UCIOS cells (configurable I/O with slew-rate control cells) which are operated in transmitting mode with the additional parasitic inductances of 5nH and a 2.5-V VDDIO voltage supply are shown in Fig. 5.12. The signal on I/O PADs1 has some glitch due to the ground bounce effect. The simulation results with variation of wire bond inductance on VDDIOchip and VSSIOchip power lines are shown in Fig. 5.13, Fig. 5.14, and Fig. 5.15. Since the current supplied from VDD_chip is much smaller than that from VDDIO_chip, only ground bounce effect on VDDIOchip is shown. As shown in Fig. 5.13, Fig. 5.14, and Fig.5.15, the configurable I/O cell with slew-rate control (UCIOS) improves the ground bounce effects greatly.

Moreover, the simulation waveforms of configurable I/O cells without slew-rate control (UCIONS) which are operated in transmitting mode with the additional parasitic inductances of 5nH, 2.5-V VDDIO voltage supply, and 24-mA driving current are shown in Fig. 5.16. The desired propagation delay of single I/O cell can be estimated as following equation:

^INV

ΔT-Delay Propagation delay of single I/O cell =

17 (4)

Where the ΔT is the time delay from the first I/O cell to the chosen I/O cell, Delay _(INV) is the delay time of the inverter (INV). The simulated comparison between the propagation delays of UCIONS and UCIOS are listed in Table 5.6. As a result, the timing specifications of the UCIOS are somewhat larger than those of the UCIONS.

Fig. 5.17 depicts the testkeys for verifying the ESD robustness of power/ground cells.

Each power/ground cell is associated with a pure ground/power pad. Fig. 5.18 depicts the testkeys of analog I/O cells. In order to test the ESD robustness on the diode and the power clamp circuit of the analog I/O cell, the power and ground line are connected to pure power and ground pad individually. Actually, the I/O pad of analog I/O cell may directly join the VDD and VDDIO power domain are only selected to test the ESD robustness.

5.3 VERIFICATION ON WHOLE-CHIP ESDPROTECTION

Fig. 5.21 shows the simplified scheme of whole-chip protection circuit. In this structure, the ground supply for core circuits and pre-driver are provided by UVSS10 cell, and the ground supply for I/O ring is provided by UVSS25 cell. Furthermore, Fig. 5.22 shows the test circuit of whole-chip protection with power break cell. The purpose is the ESD robustness test on two set of power through a power break cell. The layout-top-view of the test chip in UMC 90-nm process is shown in Fig. 5.23.

Definition of function test circuit.

Test

Circuit Measured Function Pins

TC_F1 Pull-Up/Pull-Down Resistance (RPU and RPD) PAD, I, S, PD, PU

TC_F2 Schmitt-Trigger Threshold Voltage (VT+ and VT-) PAD, C, SCH

TC_F3 Driving Current (IOH and IOL) PAD, I, S0, S1, S2

TC_F4

Simultaneous Switching Output Noise (SSO or

SSN) and Delay Time of Configurable I/O Cell

Simultaneous Switching Output Noise (SSO or

SSN) and Delay Time of Configurable I/O Cell with Slew-Rate Control

S0, S1, S2, PAD1, PAD3, PAD5, ….., PAD15, PAD17,

pure VDDIO, pure VSSIO

Threshold voltages of input stage under different simulation conditions.

Driving capability of configurable I/O cell in 1.8-V VDDIO supply voltage.

Simulation Case

Driving capability of configurable I/O cell in 2.5-V VDDIO supply voltage.

Driving capability of configurable I/O cell in 3.3-V VDDIO supply voltage.

Fig. 5.1 Test circuit for measuring pull-up/pull-down resistance and Schmitt-trigger threshold points.

Fig. 5.2 The implementation of the input cell by making from configurable I/O with slew-rate control cell.

Fig. 5.3 Simulated results of (a) pull-up and (b) pull-down resistance.

Fig. 5.4 Voltage-transfer curve of configurable I/O with (a) SCHa receiving a 1.8-V voltage and (b) SCHa receiving a 0-V voltage in 1.8-V VDDIO supply voltage.

Fig. 5.5 Voltage-transfer curve of configurable I/O with (a) SCHa receiving a 2.5-V voltage and (b) SCHa receiving a 0-V voltage in 2.5-V VDDIO supply voltage.

Fig. 5.6 Voltage-transfer curve of configurable I/O with (a) SCHa receiving a 3.3-V voltage and (b) SCHa receiving a 0-V voltage in 3.3-V VDDIO supply voltage.

Fig. 5.7 Test circuit of configurable I/O driving capability.

Fig. 5.8 Method for measuring SSN (simultaneous switching noise) of UCIOS and UCIONS.

Fig. 5.9 Test circuit for measuring SSN and propagation delay of configurable I/O cells.

Fig. 5.10 Simulated model of ground bounce.

Fig. 5.11 Simulation waveforms of ground bounce effects on power lines.

Fig. 5.12 Simulation waveforms of the UCIOS (configurable I/O cell with slew-rate control) with ground bounce effect in transmitting mode.

(a)

(b)

Fig. 5.13 The relation between ground bounce on VDDIOchip/VSSIOchip power line and wire bond inductance on the UCIONS and UCIOS with 1.8-V VDDIO_ext voltage supply. (a) The

(a)

(b)

Fig. 5.14 The relation between ground bounce on VDDIOchip/VSSIOchip power line and wire bond inductance on the UCIONS and UCIOS with 2.5-V VDDIO_ext voltage supply. (a) The undershoot on VDDIOchip power line and (b) the overshoot on VSSIOchip power line.

(a)

(b)

Fig. 5.15 The relation between ground bounce on VDDIOchip/VSSIOchip power line and wire bond inductance on the UCIONS and UCIOS with 3.3-V VDDIO_ext voltage supply. (a) The

Fig. 5.16 Simulation waveforms for propagation delay of I/O cell with operating in transmitting mode.

Fig. 5.17 Testkeys of power/ground cells, (a) UVDD25, (b) UVDD10, (c) UVSS25, and (d) UVSS10.

(a) (b) Fig. 5.18 Testkeys of analog I/O cells, (a) UAIO25 and (b) UAIO10.

(a) (b)

Fig. 5.19 Testkeys of analog I/O cells, (a) UAIO25 and (b) UAIO10 with inverter stage.

(a) (b)

Fig. 5.20 Testkeys of power break cell for (a) 1.0-V power domain and (b) 2.5-V power domain.

Fig. 5.21 Simplified scheme of whole-chip protection circuit.

Fig. 5.22 Whole-chip protection scheme with power break cell.

Fig. 5.23 Layout-top-view of test chip in UMC 90-nm CMOS process.

Chapter 6

resistance, respectively. In this measurement, the function of pull-up/pull-down network has been measured with the test circuit TC_F1 only. The signals at Sa are generated by a pulse generator and the pull-up/pull-down signals at I/O PADa can be observed by a digital phosphor oscilloscope.

Fig. 6.4, Fig. 6.5, and Fig. 6.6 show the measured waveforms of the pull-up/pull-down network with 2.5-V, 1.8-V, and 3.3-V VDDIO supply voltage, respectively. The signals of the I/O PADa can be pulled up (down) to logic high (low) successfully. Moreover, the simulation and measurement results of the pull-up/pull-down network are summarized in Table 6.1. The compared simulation results are simulated with additional loading capacitance of 12pF under

Fig. 6.7(a) and Fig. 6.7(b) show the measurement setup to verify the threshold voltages

Fig. 6.7(a) and Fig. 6.7(b) show the measurement setup to verify the threshold voltages

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