T HESIS O RGANIZATION

In chapter 2, the DC specification of this configurable I/O cell will be listed, and the circuit design and the simulation results of the configurable I/O cell will be specified. The design of ESD protection circuits will be introduced in chapter 3. The whole layout implementation of the I/O cell library will be shown in chapter 4. Besides, in chapter 5, the test chip arrangement for function verification and ESD robustness tests will be illustrated.

The experimental results will be shown in chapter 6. Finally, the last chapter ends with a few concluding statements pertaining to the research as well as recommendations for future work in the area.

Configurable I/O cell library.

I/O Cells

Cell Name Function Pins

UCIOS Configurable I/O Cell with Slew-Rate Control PAD, I, S0, S1, S2, PD, PU, SCH, C UCIONS Configurable I/O Cell without Slew-Rate Control PAD, I, S0, S1, S2,

PD, PU, SCH, C

UVDD25 Positive Power Source for I/O Ring VDDIO

UVSS25 Ground Supply for I/O Ring VSSIO

UVDD10 Positive Power Source for Pre-Driver and Core

Circuit VDD

UVSS10 Ground Supply for Pre-Driver and Core Circuit VSS

UPBREAK Power Bus Break Cell

Other Cells

Metal Layers Suitable for 4 ~ 9 layers

Fig. 1.1 The four pin-combination modes for ESD test on an IC product: (a) positive-to-VSS (PS-mode), (b) negative-to-VSS (NS-mode), (c) positive-to-VDD (PD mode), and (d) negative-to-VDD (ND-mode).

Fig. 1.3 The ESD current paths of the I/O pad with power-rail ESD clamp circuit under the positive-to-VSS (PS-mode) ESD stress. The ESD current paths are indicated by the dashed lines.

Chapter 2

Design and Simulation Results of Configurable I/O Cell

2.1 INTRODUCTION OF CONFIGURABLE I/OCELL

Fig. 2.1 shows the circuit block diagram of the configurable I/O cell and the function of each block circuit is defined as follows:

 Pre-driver: The driving select signals, S0, S1, and S2, are used to control the configurable I/O cell operating in transmitting mode or in receiving mode (tri-state input mode). When the configurable I/O cell operates in transmitting mode, the pre-driver generates pull up signals, P0, P1, and P2, and pull down signals, N0, N1, and N2. Therefore, the output transistors NMOS and PMOS can be turned on (off) separately to change the output driving capability.

 Level shifter: The voltage level of operation signal is shifted from low (VSS-to-VDD) to high (VSSIO-to-VDDIO).

 Output stage: When the configurable I/O cell operates in transmitting mode, the low voltage level (VSS-to-VDD) at the data input signal, I, will be transformed into the high voltage level (VSSIO-to-VDDIO) at the I/O PAD. Consequently, different amount of output transistors NMOS/PMOS turned on will result in different output driving capability.

 Input stage: When the configurable I/O cell operates in receiving mode, the

stage or schmitt-trigger input stage. Moreover, the configurable I/O cell in receiving mode receives VSSIO-to-VDDIO input signal at the I/O PAD and then transmits VSS-to-VDD output signal to core circuit through the input stage.

 Pull-up/Pull-down network: When the driving select signals S0, S1, and S2 are biased at 0V and the I/O PAD is floating, the configurable I/O cell operates in tri-state. In this situation, the mechanism of pull-up and pull-down can be turned on or off by the pull up signal PU and the pull down signal PD.

 Slew-rate control: When the output stage operates with slew-rate control circuit, the simultaneous switching noise (SSN) can be reduced significantly.

Table 2.1, Table 2.2, and Table 2.3 list the pins usage and functions of configurable I/O cell. Besides, the design flow, specific circuit, operation principle, and simulation results of configurable I/O cell are discussed in following sections.

2.2 BASIC SPECIFICATION

In this configurable I/O cell library, the typical core power supply voltage (VDD) and I/O output driver power supply voltage (VDDIO) are 1.0V and 2.5V. However, the library is also compatible with 1.8-V ~ 3.3-V design window of VDDIO. Therefore, the information of this library will be provided not only with 2.5-V VDDIO, but also with 1.8-V and 3.3-V VDDIO supply voltage in following introduction. Table 2.4, Table 2.5, and Table 2.6 list the DC specification of configurable I/O cell under 2.5-V, 1.8-V, and 3.3-V VDDIO supply voltage, respectively.

2.3.1 Driving Capability

In order to design an output cell with variable driving capability, the transistors of output driver are distributed into three groups, MP0/MN0, MP1/MN1, and MP2/MN2 as shown in Fig. 2.1. The specification on dc driving currents of the configurable I/O cell are defined as 2mA, 8mA, 10mA, 14mA, 16mA, 22mA, and 24mA with different output MOS fingers.

When the output driving current is 2mA, the finger number of the output driver is one.

Similarly, when the output driving current is 24mA, the finger numbers of the output driver are 12 fingers.

The driving select signals, S2, S1, and S0, are used not only to control the operating mode, but also to choose the output driving capability in transmitting mode. In order to distribute the output driving current equally, 12 fingers of output drive are divided into three groups in parallel. The transistor MP0/MN0 is designed with only one finger, and MP1/MN1 and MP2/MN2 are composed of 4 fingers and 7 fingers, respectively. The relation between the driving capability and the driving select signals (S0, S1, and S2) has been mentioned in Table 2.2. Moreover, the design flow of output driver will be introduced in next paragraph. However, several parameters should be defined firstly in this section as follows:

 I_OL: The sink current at I/O PAD of configurable I/O cell when the voltage at I/O PAD of configurable I/O cell is biased at VOL (= 0.4V), as shown in Fig. 2.2.

 I_OH: The source current at I/O PAD of configurable I/O cell when the voltage at I/O PAD of configurable I/O cell is biased at VOH (= VDDIOmin – 0.4V = 0.9 x VDDIO – 0.4V), as shown in Fig. 2.3.

expressed as following equation:

= Duty Cycle

T

 (1)

where  is the duration that the function is non-zero; T is the period of the function.

First of all, the size of output NMOS with single finger (MN0) in Fig. 2.1 has to be determined in output driver design. The simulation setup for measuring size of MN0 is shown as Fig. 2.2(a). It has been simulated by SPICE in a 90-nm CMOS process with a simulated environment of 2.25-V (0.9 x 2.5V) VDDIO and the worst case (temperature of 125 ^oC and SS corner) which can result in the experience results to meet the design specification certainly.

Table 2.7 lists the definition of simulated environment. As shown in Fig. 2.4, the MN0 size can be determined with the low level output current I_OL equaled to 2.32mA. While the simulated and measured values of IOH/IOL are larger than the definition value (2mA, 8mA, 10mA… 24mA), it can be described as design specification conformability in driving capability. Table 2.8 depicts the simulation results of the level output current IOL in different simulation environments. The dimension of the NMOS is determined with 2.25-V VDDIO and the worst case simulation environment. After determining the size of MN0, a single-finger output PMOS, MP0, is combined with this output NMOS as an inverter to design output PMOS. In this thesis, there are two methods to design the output PMOS. The first method determines the size of output PMOS MP0 by the high level output current I_OH ≈ IOL where I_OL was the simulated driving current under the worst case and 2.25-V VDDIO for output NMOS, as shown in Fig. 2.5. Fig. 2.6 shows the simulated result of output PMOS MP0 with the channel width of 45.4m and the simulation environment is set in the worst case and 2.25-V VDDIO. As shown in Fig. 2.7, the second method to determine the size of output PMOS MP0 is to make that duty cycle of output signal near to 50% when a square wave with duty cycle of

The duty cycle of output signal could be more (less) than 50% due to too big (small) PMOS size, as shown in Fig. 2.8. Thus, the channel width of MP0 by second method is determined on 42m and the simulated duty cycle is 50.7% as shown in Fig. 2.9. According to these two PMOS sizes from these two methods, the corresponding IOH and duty cycle are compared in Table 2.9 with the same simulation environment. Since the output PMOS size in the second method is smaller than the first method, the output PMOS size is decided on 42m.

The simulation results of pull high driving current (I_OH) and duty cycle with different simulation environments are listed in Table 2.10 and Table 2.11, respectively. In Table 2.11, the input signal V_in is set in 0 ~ VDDIO, T_r = T_f = 0.1ns, pulse width = 1.875ns, period = 3.75ns, frequency = 266MHz and the additional loading capacitance (Cload) is 10pF.

Furthermore, Table 2.12, Table 2.13, and Table 2.14 list the simulation results of duty cycle with different output MOS fingers and operating frequencies under 2.5-V, 1.8-V, and 3.3-V VDDIO voltage supplies. Similarly, the input signal V_in is set in 0 ~ VDDIO, T_r = T_f = 0.1ns, pulse width = 1.875ns, period = 3.75ns, frequency = 266MHz, and Cload is 10pF but the simulation environment is set with pseudo worst case for close to actual condition.

2.3.2 Short-circuit Current Reduction

The circuit consumes unnecessary power due to short-circuit current. In order to reduce the short-circuit current at the output stage, the output NMOS/PMOS should be turned on slowly and turned off quickly to avoid DC paths flowed from VDDIO to VSSIO. Thus, the gate-controlled signals of output PMOS (NMOS) should be designed with a short (long) rise time and long (short) fall time. Fig. 2.10 shows the implementation of inverter with short-circuit current reduction. MP2/MN2 and MP3/MN3 are transmission gates as resistive

output driver as shown in Fig. 2.11. Fig. 2.12 shows the simulation results under different VDDIO supply voltage. When the gate-controlled signals (P_out and N_out) are pulled up to VDDIO, the signal of N_out is transmitted more slowly than P_out. On the contrary, the signal of P_out is transmitted more slowly than N_out when P_out/ N_out are pulled down to VSSIO. The inverter with short-circuit current reduction can be used to produce a delay of signal.

The inverters with short-circuit current reduction shown in Fig. 2.10 are added to the inverter chains to form the tapper buffers in front of the output driver (MN1~2/MP1~2) as shown in Fig. 2.1. Besides, since single-finger output drivers (MN0/MP0) have small amount of driving currents, the tapper buffers in front of it (MN0/MP0) can be composed of general inverters (without short-circuit reduction) to save layout area. In addition, each gate terminal of MP2-MP3 and MN2-MN3 shown in Fig. 2.10 has to be connected to power line (VDDIO or VSSIO) through a resistance individually to avoid the gate-oxide breakdown under ESD stress condition. However, in order to show the circuit clearly, the resistances are all omitted in this figure.

2.4 PRE-DRIVER

The pre-driver circuit uses thin-oxide (1.0-V) devices since the input data comes from internal core circuit with VSS-to-VDD (0V-to-1.0V) voltage level. Furthermore, the pre-driver circuit generates control signals of output drivers. Table 2.15 lists the truth table of pre-driver circuit, where the control signals (S2-S0), input signal (I), and gate-controlled signals (P2-P0 and N2-N0) correspond to that in Fig. 2.1. According to the table, the relation

 

Therefore, the logic diagram of pre-driver composed of a NAND gate and NOR gate is shown in Fig. 2.13. However, since parts of transistors can be used commonly to save layout area, the circuit is implemented as shown in Fig. 2.14. Fig. 2.15 shows the simulation waveforms under different frequencies of input signals. It depicts the pre-driver can be operated correctly under different input frequency.

2.5 LEVEL SHIFTER

Since the output stage receives VSS-to-VDD (low voltage level) input signals at control/input signal pin (I, S0, S1, and S2) and transmits VSS-to-VDDIO (high voltage level) output signals at I/O PAD, the I/O cell needs a level shifter circuit to shift the voltage level from VDD to VDDIO. Fig. 2.16 shows circuit implementation of level shifter. Two inverters connected to gate terminals of transistors MN1 and MN2 separately are comprised of 1.0-V devices, other transistors are 2.5-V devices. When the input (In) receives a DC signal of VDD (1.0V), the node Inb and node In_buff are biased at VSS and VDD. Thus, the transistor MN2 (2.5V device) is turned on weakly due to the VGS, MN2 = 1.0V and MN1 is turned off. However, when the node I_invb is pulled down to logic low, the node I_inv will start to be pulled up to logic high through the transistor MP1. Therefore, the transistor MP2 will be switched off, and then the output (Out) will be biased at VDDIO due to the node I_invb is biased at 0V. On the contrary, when the input (In) receives a DC signal of VSS (0V), the level shifter will transmit

conditions as listed in Table 2.16. A small amount of load capacitance (C_load) is added to simulate the parasitic capacitance while the output is connected to the input of inverter chain.

2.6 INPUT STAGE

The circuit diagram of schmit-trigger with an enable signal, SCH, is shown in Fig. 2.19, where the transistors MN4/ MP4 are 1.0-V devices, and the others are 2.5-V devices. While SCH receives logic high (1.0V) to trigger the function of schmitt-trigger, the node 1 and 2 are biased at VSS (0V) and VDD (1.0V) and then the noise margin will be enhanced. On the contrary, while SCH receives logic low to turn off the function of schmitt-trigger, the node 1 and 2 are floating points and then the circuit will become a inverter to form normal input transform the voltage level from VSSIO-to-VDDIO (high voltage level) to VSS-to-VDD (low voltage level). In order to overcome gate-oxide reliability [1] and hot-carrier degradation [2], this inverter is composed of thick-oxide devices. However, the inverter with thick-oxide devices causes a small Vgs of the transistor MP when MP is turned on. Thus, in order to make a close 50-persentage duty cycle of output signal, MP has been designed in a big size to enhance the driving capability.

V_T-, and V_TH). The waveforms of output signal, C, is simulated while the I/O PAD is swept from logic low to high and then return to its initial voltage level. The VT+/- is defined as the voltage level of I/O PAD while the voltage level of C is VDD/2 with the function of schmitt-trigger (SCH = 1). The VT+ is I/O PAD transmitted from low to high, and the VT- is that from high to low. The V_TH is defined as the voltage level of I/O PAD while the voltage level of C is VDD/2 without the function of schmitt-trigger (SCHa = 0). Fig. 2.22-24 show the simulation waveforms of input stage when the I/O PAD is inputted a signal with 266-MHz frequency under different VDDIO supply voltage, and Table 2.18-19 list the duty cycle under different simulation conditions. Since the Vgs of the transistor MN shown in Fig. 2.20 vary from 1.62V to 3.6V, the range of duty cycle in Table 2.18 and 3.19 are 45.72% ~ 56.65% and 44.85% ~ 61.79%, respectively.

2.7 PULL-UP/PULL-DOWN NETWORK

In this thesis, the pull-up and pull-down resistances are formed with a PMOS and NMOS operating in linear region, respectively. Besides, in order to prevent ESD stress, two 36k-Ω resistances are placed individually between the I/O PAD and the drain terminal of PMOS/NMOS as shown in Fig. 2.25. To avoid an undesired leakage current, the control signal PU (VSS-to-VDD) is shifted to high voltage level (VSSIO-toVDDIO) by level shifter mentioned in section 2.4 to turn the PMOS (MP1) off completely.

Since the equivalent resistance of the PMOS/NMOS (MP1/MN1) operating in linear region is nonlinear resistance, the rise/fall time of pull-up/pull-down network is near to that

terminals of MP1 and MN1 are biased at 0V to turn on the MP1 and turn off the MN1, respectively. Under the same additional load capacitance (Cload) of 12pF, MP1 and the 36k-Ω series resistance are replaced by an ideal resistance (R_PU) of 37kΩ. In order to make that these two simulated circuit have similar rise time, the device size of MP1 can be optimized with the typical simulation case and 2.5-V VDDIO. Therefore, the device size of MP1 can be determined and the corresponding ideal resistance can be defined as the equivalent pull-up resistance (R_PU) in simulated circuit, simultaneously. Similarly, the dimension of pull-down MOS (MN1) is determined as shown in Fig. 2.27. Hence, the size of MN1 can be determined and the corresponding ideal resistance is defined as the equivalent pull-down resistance (R_PD) in simulated circuit, simultaneously.

After determination of the MP1/MN1 size, Fig. 2.28 shows the simulation setup of the equivalent pull-up/pull-down resistances (RPU/RPD) in simulated circuits with different simulated conditions and load capacitance of 12pF. The R_PU/R_PD is modified to obtain the same rise/fall time of the pull-up/pull-down network. The simulation results are listed in Table 2.23 and Table 2.24. The variation of pull-up/pull-down resistance is listed in Table 2.25.

2.8 SLEW-RATE CONTROL

2.8.1 Introduction

Signal and power integrity are crucial issues in VLSI systems. Modern trends in deep sub-micron circuit designs, such as high operating frequencies, short rise/fall times, and lower supply voltage, exacerbate this problem. Output buffers provide an interface for driving mainly capacitive and inductive external loads. The capacitive load typically consists of the

gates. The inductive load usually comprises the package parasitic series inductances of the power and ground lines supplying the output buffer, connected to the external power and ground rails on the PCB. A major component of the circuit noise is the inductive noise.

Ground bounce, also known as simultaneous switching noise (SSN) or delta-I noise, is a voltage glitch induced at power/ground (P/G) distribution connections due to switching currents passing through either wire/substrate inductance or package lead inductance associated with power or ground rails. When the current flows through the inductance L, the voltage drop can be expressed as

V Ldi

 dt (3)

In the output buffer design, the transistors sizing is imposed by DC interfacing constraints. This leads to several problems [11]:

 Unacceptable high current peaks which occur with the simultaneous switching of many output buffers;

 Inductive power supply noise which results in large voltage drops;

 Electromagnetic interference (EMI) due to high output edge switching rates.

The results noise voltage can potentially cause spurious transitions at inputs of devices sharing the same power and ground rails. Therefore, controlling the output voltage variations is generally required to limit the crosstalk and reduce the inductive power supply noise to an acceptable value. Besides, the effect of ground bounce in output buffer can be simply modeled as an inductor shown in Fig. 2.29 [12].

To solve these problems, a reduction of the slew rate in the output edges is preferred as far as the speed specification is satisfied [13]. A simple approach is to slow down the turn-on time of the output switching transistor through an access resistor to the transistor gate.

Furthermore, the output driver can be divided into several parallel output drivers for ground bounce reduction and slew-rate control. An output buffer with slew-rate control, which is a three-step slew-rate control circuit, is shown in Fig. 2.30 [14]. The parallel output transistors of slew-rate controlled output buffer turn on progressive through delay elements implemented by resistors or transmission gates. This helps reduce the slew rate of output buffer and the ground/power bounce. However, the output transistors turn off step by step as output transistors turn on.

2.8.3 Design of Slew-rate Control

Fig. 2.31 shows the output driver of configurable I/O cell with slew-rate control to reduce ground/power bounce. The delay elements are implemented by transmission gate (MDN/MDP). The original MN1/MP1 (multiple=4) shown in Fig. 2.1 are divided into

Fig. 2.31 shows the output driver of configurable I/O cell with slew-rate control to reduce ground/power bounce. The delay elements are implemented by transmission gate (MDN/MDP). The original MN1/MP1 (multiple=4) shown in Fig. 2.1 are divided into