Chapter 3 The Transmitter Architecture
3.3 S UMMARY
In this chapter, the architecture of the proposed transmitter is described. The pre-emphasis concept is introduced. In the next chapter, we will describe the detail circuit. The algorithm of calibration is proposed and proven that it is convergent. We will realize this algorithm by circuit in the next chapter.
Chapter 4
Transmitter Circuit Design
4.1 Introduction
This chapter will describe the detail circuit of the proposed architecture. The circuit includes the pre-emphasis transition detector, the output swing calibration controller, and the driver circuit. At the end of this chapter, the simulation results are given. We use the channel in SPICE to test and verify the proposed architecture. The frequency response of channel is shown in Figure 2.2.
Figure 4.1 Frequency response of using HSPICE channel model
Figure 4.1 shows the frequency response using the HSPICE model. The characteristic impedance of the channel is 50Ω.
4.2 Circuit Design
4.2.1 Transition Detector
Chapter3 has described the function of the 2 taps pre-emphasis. Tap1 operates when there are data transitions. The tap1 detection block is as shown in Figure 4.2.
We use latch to produce a data delay of half symbol space. Then this circuit provides opposite pulses by using NAND gate and NOR gate. Pout1-0 and Poutb1-0 send pulses when data transit from high to low and Pout0-1 and Poutb0-1 send pulses when data from low to high.
Figure 4.2 Tap1 detection circuit
Figure 4.3 Tap2 detection circuit inb
latch in
latch latch
latch
clk clkb
Pout1-0
Poutb1-0
Poutb0-1
Pout0-1
in
inb latch latch
latch latch
latch latch clkb
clk clk
Pout_O1-0
Poutb_O1-0
Poutb_O0-1
Pout_O0-1
The tap2 detection block is shown in Figure 4.3. Tap2 operates when there are data transitions and it maintains the voltage level of the output after tap1 is over. We also use latch to make delay and use logic gate to generate pulses. Pout_O1-0 and Poutb_O1-0 send pulses when data is from high to low and Pout_O0-1 and Poutb_O0-1
send pulses when data is from low to high. Note that the clock rate of the transition detector is the same as the data rate. For example, data rate is 3Gbps and the clock rate is 3GHz.
4.2.2 Swing Calibration Controller
Swing calibration controller is used to compensate voltage of the output due to process variation. This block includes FSM, a shift register, and comparators as shown in Figure 4.4.
1020mV
Shift registers0u s11u
Shift registers0u s11u
Figure 4.4 The architecture of the swing calibration controller
The source information of FSM is from the comparators. We use a simple two-stage operational amplifier to compare the output voltage and reference voltages as shown in Figure 4.5. Inverters are added to obtain digital outputs.
Figure 4.5 The comparator circuit (a) for higher output voltage (b) for lower output voltage
After the comparison with output voltage level and reference voltage, we have two digital outputs (U and D). WhenVout is higher thanVrefh, U is 1, otherwise U is 0. WhenVoutb is lower thanVrefl, D is 1, otherwise D is 0. According to results of the comparators and Figure 3.14, we can find the truth table and equations of FSM as shown in Table 4-1.
Vrefl
Voutb
Vbias
D VDD
(b) Vout
VDD
Vrefh
Vbias
U
(a)
Table 4-1 Truth table of FSM
This calibration begins when there is a reset signal.Vout that is a higher DC voltage level is calibrated first, when calibration function operates.Vout is calibrated until u is one. It means Vout is higher thanVrefh. When FSM calibratesVout, we use
qu to control the multiplexer to transmit clock to shift register. It makes shift register work. When qu is one, it means Vout is less than Vrefh and we need to increase resistors to raise Vout. Increasing one resistor means the shift register shifts one to next. When qu is zero, it means Vout has been greater thanVrefh and the shift register stops working and holds the value in the shifter register. When Vout is calibrates over, FSM begins to calibrateVoutb and it is the same process we describe the above-mentioned. But we use clkb to achieve. This way can reduce calibration cycle time. Two calibration functions will operate in rotation until qu and qd are all zero and calibration is over. It means Vout is greater than Vrefh and Voutb is less than Vrefl. Figure 4.6 shows the show the shift register. We can see that the shift registers always shift right. So the shift registers increase the number of one and do not reduce. The flip-flop of shift registers is the static type. We can not use the dynamic flip-flop, because after the self-calibration the output value of the D flip-flop must hold on itself forever.
s0u s1u s2u
s0d s1d s2d
D Q D Q D Q
s8u s9u s10u s11u
s8d s9d s10d s11d D Q D Q D Q
D Q D Q D Q
. . .
s0u s1u s2u
s0d s1d s2d D Q
s8u s9u s10u s11u
s8d s9d s10d s11d D Q D Q D Q
D Q D Q D Q
. . .
Figure 4.6 The shift registers
When calibration function operates, the reflection will happen. The reflection makes calibration function error and unlock as shown in Figure 4.7.
Figure 4.7 Reflection effect when calibration function operates
In order to solve this problem, we reduce the clock rate to wait for the reflection effect to disappear and sample the stable output as shown in Figure 4.8.
Figure 4.8 Solution of reflection effect
This solution has successfully solved the reflection effect. The simulation results as shown in Figure 4.9. When output voltage is stable, we send a pulse to EnableP (EnableN).
Shift register working time
Waiting time Waiting time Clk
No reflection effect Reflection effect Vout
Voutb
Figure 4.9 Simulation result of calibration which overcomes reflection effect
4.2.3 Counter
The counter is a simple block. The counter operates at low as kHz. So we choose the simple architecture shown in Figure 4.10. There are six D Flip-Flops and a NOR gate. D and Qb are connected to together so that D Flip-Flops become T-Flip-Flops.
When the clock trigger, S1~S6 are triggered in sequence. After 16 clocks, Tx goes high, the calibration process ended and the driver starts sending data.
D Q
Figure 4.10 The architecture of the counter
Figure 4.11 shows the function verification of the counter above. After the reset, S0~S4 begin to count until S5 changes. Tx signal rise from LOW to HIGH and hold on until the next reset. We use this counter to decide when the transmitter to transmit or do self-calibration. Tx signal presents the operation mode of our transmitter.
EnableP EnableN Voutb Vout
Clk
S0 S1 S2 S3 S4
Tx S5 reset
clk
stable S0
S1 S2 S3 S4
Tx S5 reset
clk
stable
Figure 4.11 The function verification of the counter
4.2.4 Driver
The driver is studied in this section. The power supply and ground of an IC is not ideal. It is combined with the equivalent inductance and capacitance of power distribution networks as shown in Figure 4.12. The load capacitor will be charged and discharged when signal transient. The switching noise increases as the frequency increases.
VDD
CVdd
CVss
LVdd
LVss
Cpad CL
Lpin VDD
VDD
CVdd
CVss
LVdd
LVss
Cpad CL
Lpin
Figure 4.12 Simplified electrical model of chip-package interface
Conventionally, two current sources are connecting to power and ground respectively to minimize the current change hence reduce noise as shown in Figure 4.13 (a). Unfortunately, these two current sources will create a large voltage drop and limit the output voltage swing. In order to meet LVDS standard, the size of the four switching transistors need to be increased. So, the sizes of the pre-drivers must also be increased. This will increase the area and power of the pre-driver. It is a trade-off between the performance and the cost. Due to the device size scaled-down, the power supply voltage decreases. This problem becomes a challenge for designers. So, we proposed the following architecture. It has no current source in power supply and ground as shown in Figure 4.13 (b).
Figure 4.13 LVDS driver (a) traditional (b) proposed driver
This methodology has some advantages. First, the driver needs no current source so output signal swing is enlarged. It also reduces the sizes of switch transistor greatly.
Hence, the sizes of the pre-driver are reduce as well. It reduces the overall chip area substantially. Furthermore, the whole driver architecture looks like the two inverter connected back to back, it makes the control and layout easier. Notice that, the common-mode voltage is lowered from 1.25V to 0.9V to be used in a 1.8V supply environment. According to the proposed driver, we add logic gates to the driver. The completive version for the design is shown in Figure 4.14.
Figure 4.14 (a) shows the circuit of the main driver and the calibration driver.
(a) (b)
For the main driver, A and B pins are connected to Vdd. For calibration driver, then we can control A and B pins according to the swing calibration controller. In total, there are twelve calibration drivers. Figure 4.14 (b) shows the circuit of the pre-emphasis driver. We can control A and B pins respectively to connect HIGH or LOW to determent how many PMOS and NMOS being turned on according to the channel loss. The transition detector controls Pout0-1, Poutb0-1, Pout1-0 and Poutb1-0. When data has transitions, the transition detector generates pulses to control these pins to shape output signal. Note that Tap1 and Tap2 are the same and the only difference is that the transition detector sends different widths of pulses to the drivers.
Figure 4.14 Complete version of our driver (a) main and calibration driver (b) pre-emphasis driver
In chapter3, we stated that our driver is like a voltage divider with resistors.
These resistors are PMOSs and NMOSs as shown in Figure 4.14. And we will discuss the reflection problem. When the driver is operating in the pre-emphasis state, we can not guarantee that equivalent resistor is 50Ω. But we hope it is 50Ω to cancel the reflection effect in steady statue at least. We can determent the termination resistor value of near end and the equivalent resistors of four switches to make these resistors
in inb
A
B A
B
(a)
Pout0-1
A
B A
B
Poutb0-1
Poutb1-0
Pout1-0
(b)
be equal to 50Ω when the reflection happens as shown in Figure 4.15. When we determent termination resistor value of near end, we just control the output voltage at desired level, then the resistor will be equal to the needed 50Ω. If the output voltage is wrong, the swing calibration controller will calibrate it.
Figure 4.15 Equivalent resistors change
According to simulation results, we can get relationship between the turn-on MOSs and the output voltage in Figure 4.16. We can change tune-on MOS to change the output voltage to reach desired level. At the same method, the SF and FS cases also are considered in our driver design.
Figure 4.16 The output voltage of the TT, SS and FF cases 1U.I.
out
outb
50Ω Not 50Ω
4.2.5 Delay Buffer
The delay buffer is the simple circuit. In order to obtain the same delay for the main driver, the calibration driver, and the pre-emphasis driver, we use inverter chains to obtain the same delay as shown in Figure 4.17.
Figure 4.17 Delay buffer circuit
4.3 Simulation Result
4.3.1 Output Swing Calibration Simulation
To verify the design of the swing calibration controller circuit, the post-simulation results of the transmitter circuit are shown in this section. Figure 4.18 and Table 4-2 show the simulation results of the calibration function. We set the reference voltages to 1020mV (Vrefh) and 780mV (Vrefl) for a swing of 250mV and a common mode of 900mV. Vhigh is 1025mV and Vlow is 775mV. The calibration needs at most twelve clock cycles to complete, our counter will count sixteen clock cycles and switch to transmission mode. We can see the mode change in Figure 4.18.
The calibration function of FF case does not operate because R andu R are less d thanRstable initially. Rru and Rrd can be calculated according to the simulation data and their values are about 50Ωin steady state. This can reduce the reflection effect.
latch
latch in
inb
Main/calibration Driver
Calibration mode Transmission mode (a)
(b)
(c)
(d) Vout
Voutb
Vout Voutb
Vout
Voutb
Vout
Voutb
Figure 4.18 Post-Simulation results of calibration functions (a) TT case (b) SS case (c) SF case (d) FS case (e) FF case.
Table 4-2 Parameter summary after calibration Corner
case Vhigh Vlow
After Calibration
R u
After Calibration
R d
Reflection resistor
Rru
Reflection resistor
Rrd
TT 1.022V 0.768V 178.2 Ω 176.01 Ω 49.7 Ω 49.9 Ω FF 1.025V 0.768V 175.8 Ω 174.3 Ω 49.5 Ω 49.7 Ω SS 1.023V 0.760V 171.5 Ω 167.7 Ω 49.0 Ω 49.3 Ω FS 1.036V 0.777V 171.2 Ω 173.3 Ω 49.6 Ω 49.2 Ω SF 1.034V 0.773V 170.6 Ω 172.2 Ω 49.4 Ω 49.3 Ω
4.3.2 Output Eye Diagram Simulation
After checking the calibration functions, we simulate the output eye diagram of our driver in this section. We use C language to generate 3.125Gbps random data. In Figure 4.19, the driver without the pre-emphasis has a jitter of 26ps in post-layout simulation. The height of the eye diagram is about ±250mV. Receiver eye diagram is not good due to channel loss. So we add pre-emphasis function to the driver and the output jitter is about 36ps as shown in Figure 4.20. Although the transmitter output jitter is increased, the eye diagram of the receiver is a better than in Figure 4.19. The height of the eye diagram of the receiver is about ±200mV.
(e) Vout
Voutb
Figure 4.19 Eye diagram of propose transmitter without pre-emphasis
Figure 4.20 Eye diagram of propose transmitter with pre-emphasis
Figure 4.21 is the overlap of the eye diagrams with and without pre-emphasis.
We can see clearly that pre-emphasis compensates the channel loss effectively.
~26ps Tx output
Rx input
Tx output
Rx input
~36ps
Figure 4.21 Overlap eye diagrams to comparison
4.4 Implementations
The proposed transmitter is implemented using TSMC 1P6M 0.18um. The total chip area is 0.95mm*0.84mm and the core area is 0.47mm*0.44mm as shown in Figure 4.22. The driver is in the middle of the chip and the transition detector (TD) and the swing calibration controller (SCC) are on both sides. We use pre-emphasis control pins to control pre-emphasis according to the channel response. Some pins are reserved for debugging. The summaries of post-layout simulation are shown in Table 4-3.
Rx input (with pre-emphasis) Rx input (without Pre-emphasis)
vdd gnd out
outb clk clks vin
Pre-emp control p in s
Pre-emp control p in s
Debug control pin
Dr iv er SCC
outb clk clks vin
Pre-emp control p in s
Pre-emp control p in s
Debug control pin
Dr iv er SCC
SC C
TD TDvdd gnd
out
outb clk clks vin
Pre-emp control p in s
Pre-emp control p in s
Debug control pin
Dr iv er SCC
SC C
TD TD840um
950um
Figure 4.22 Layout of proposed transmitter Table 4-3 Chip summary of the transmitter
26p @3.125Gbps(no pre-emp) 36p @3.125Gbps(with pre-emp) Jitter (pk-pk)
38.7 mW (without pre-emp) 50.6 mW (with pre-emp) Power
Power Supply 1.8V
0.18um 1P6M CMOS Technology
Tx with pre-emphasis Function
26p @3.125Gbps(no pre-emp) 36p @3.125Gbps(with pre-emp) Jitter (pk-pk)
38.7 mW (without pre-emp) 50.6 mW (with pre-emp) Power
Power Supply 1.8V
0.18um 1P6M CMOS Technology
Tx with pre-emphasis Function
4.5 Summary
In this chapter, we have described the proposed transmitter circuit. The driver has an additional circuit that can calibrate the output voltage by itself. The chip can detect the output level and start the calibration by reset. After 16 clocks, the calibration ends and the driver start sending data. The pre-emphasis is also added to this driver to compensate channel loss. According to the channel response, we can adjust pre-emphasis. We can control the rising/falling time and no over compensation in steady state. The overall simulation results of transmitter and receiver eyes diagrams and calibration are shown in this section.
Chapter 5 Conclusion
5.1 Conclusion
High-speed link becomes more and more important. In this thesis, we proposed a 3.125 Gbps transmitter architecture that uses novel scheme with self-calibration and pre-emphasis. We have described Tap1 and Tap2 of the pre-emphasis. It improves the signal quality at far end. The self-calibration that compensates the process variation is also proposed and its algorithm is proved. We have described overall transmitter circuit and simulation. According to post-layout simulation, we know that the self-calibration and pre-emphasis are working correctly. Our pre-emphasis is better than others, because we can control the rising (falling) time and no overshot in steady state. The proposed transmitter is composed of the digital logic gates, so a self-calibration, all-digital 3Gbps driver with pre-emphasis is implemented in this thesis. The proposed driver can be used in SATA Ⅱ [8]. This transmitter is implemented in TSMC 1P6M 0.18um CMOS technology.
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