F UNCTIONAL B LOCKS - The Transmitter Architecture

Chapter 3 The Transmitter Architecture

3.2 F UNCTIONAL B LOCKS

Figure 3.1 The overall transmitter architecture

The swing calibration controller is the finite state machine (FSM). The FSM control the compensated driver by another digital circuit (shift register). When output voltage is detected, the FSM calculates and controls the shift-register to decide compensation current. The self-calibration feedback does not always work all the time.

When the transmitter is in the calibration mode, the input is always connected to Vdd.

When the transmitter is in the data transmission mode, the multiplexer will switch the input to the data. We use a slow counter to change mode when the counter counts a pre determined period of time.

3.2 Functional Blocks

We will discuss the important functional blocks in this section.

3.2.1 Pre-Emphasis Module

As described in chapter 2, the transmission line is a low pass function.

Pre-emphasis circuit plays a role of high pass function so that the frequency response is flatten within the bandwidth of our desired frequency range in the receiver. This

frequency response can be written as

, f f t tan cons )

f ( H ) f (

H_c ⋅ _pre = ≥ _op (3.1)

where H_c( f )is the channel frequency response, H_pre( f )is the pre-emphasis frequency response and f_op is the maximal operation frequency.

The pre-emphasis either amplify the high frequency component or attenuate the low frequency component as shown in Figure 3.2 [8]. In the diagram, the dotted line means the overall frequency response.

Figure 3.2 Frequency response, (a) the high frequency is amplified and (b) the low frequency is attenuated.

We use the scheme of Figure 3.2(a). The primary reason is that the low frequency component is attenuated and the voltage swing may not be large enough to recover data correctly at far end. This method increases the power of high frequency components. In order to increase the high frequency part, we can shape the transition of the signaling.

Gain

Freq.

Channel frequency response

Pre-emphasis

Freq.

Gain

Channel frequency response

Pre-emphasis (a)

(b)

Traditionally, a tap of the pre-emphasis is a symbol space as shown in Figure 3.3 (a). The dashed line is the waveform of the receiver. There are some problems.

We can not compensate the rising (falling) time and the steady state voltage level simultaneously. In many specifications, the rising (falling) time is requested. The first tap of the pre-emphasis decides the rising (falling) time. In order to reduce rising time in the receiver, the first tap has to increase more current to enhance the output voltage of the transmitter as shown in Figure 3.3 (b).

Figure 3.3 (a) The pre-shaped signal in the transmitter, (b) increasing current of the first tap

We can also see that there is an overshot waveform at far end. In the receiver eye diagram, the overshot waveform is the over compensation for steady state voltage level as shown in Figure 3.4(a). If we only compensate for steady state voltage level and no overshot waveform in the receiver, the rising time may not short enough to match the specifications as shown in Figure 3.4(b).

So we propose a new method to implement the pre-emphasis function as shown in Figure 3.5. A tap of the pre-emphasis which is only half symbol space is a feasible method to compensate for rising (falling) time and steady state voltage level simultaneously. If the first tap that controls the rising time is a symbol space, it may cause overshot waveform in the receiver. If we reduce it to half symbol space, the

1U.I.

(a)

(b)

overshot waveform is diminished and the rising (falling) time can be also compensate to match the specification.

In Figure 3.6, we can see that the overshot waveform is diminished in the receiver and the rising (falling) time can be easily controlled with increasing current by the first tap. Therefore, our new method of the pre-emphasis function is better than traditional one in overcoming the channel loss effect.

Figure 3.4 Eye diagram of the receiver, (a) over compensation for steady state with 1-tap of a symbol space (b) rising time is increased with non over compensation (c)

comparison between (a) and (b)

Figure 3.5 Proposed pre-emphasis function 1U.I.

Rising time 90ps

Rising time 126ps

(b)

Figure 3.6 Eye diagram of the proposed pre-emphasis function

3.2.2 Pre-emphasis and Main Drivers

The architectures of pre-emphasis, main driver and calibration driver are almost the same. There is an advantage to implement by similar architecture. Because of the similar architecture, the pre-emphasis driver, main driver and calibration driver have the same delay time.

Figure 3.7 Driver architecture : main, calibration driver and pre-emphasis D+

Ph+

Po+

Main driver

Pre-emphasis tap1

D-

Ph-

Po- Pre-emphasis tap2

Calibration driver

D+ D-

out

outb a

c Transmitter

Output

Receiver Input

The driver includes the circuit blocks of the main driver, calibration driver and pre-emphasis as shown in Figure 3.7. The strength of each tap is decided by channel length and channel loss. The relationship between current (I) and differential amplitude of the output of the transmitter (∆ ) is V

I V = ⋅

∆ _(3.2)

whereR is the equivalent resistance. _e

From Equation (3-2). We know that the amplitude increases with current orR . _e In out system, R is constant because of the termination resistance. The main driver _e represents the circuit of the original driver, the calibration driver represents the calibration circuit to calibrate output voltage level (∆ ) and pre-emphasis represents V the pre-shaping circuit to emphasize the high frequency components. The function of tap1 is shown in Figure 3.8. The circuit of tap1 operates when a data transition is detected and it suppliesI₁ to enlarge∆ . V

Figure 3.8 Signal waveform when Tap1 is operated

Tap1 is used to any transition and it only controls slew rate. So we need another tap to deal with the steady voltage level. Tap2 is essential in our design. Tap3 is required or not is determined by the receiver sensitivity, the area, and the loading overhead. In out system, if we have three tap, every tap is one third symbol space. It is a challenge to out design. So we only have two taps in our system. The function of the tap2 is shown in Figure 3.9.

Tap1 in operation 1U.I.

out

outb

Figure 3.9 Tap2 function

Figure 3.10(a) is the simulation that only tap1 operates. We can see that the data is attenuated after transition. The tap2 circuit supplies enough current to compensate for attenuation as shown in figure 3.10(b).

Figure 3.10 The simulation result in receiver end (a) only tap1 (b) tap1 and tap2 1U.I.

out

outb

Tap2 in operation

(a)

(b)

The calibration driver provides current in initial state to compensation the output amplitude according to FSM that we will discuss later.

3.2.3 Transition Detector

The transition detector detects data transition. When data has a transition, it sends a pulse to the pre-emphasis driver to make the pre-emphasis increases current to compensate attenuation as shown in Figure 3.11.

Figure 3.11 Transition detector function

Figure 3.12 Simulation result of the transition detector

When data is from high to low or low to high, the transition detector produces two types of pulses for pre-emphasis and calibration as shown in Figure 3.12.

in inb

Tap1

Tap2

1U.I.

Tap1

Tap2

3.2.4 Swing Calibration Controller

In out system, the driver is like a voltage divider with resistors as shown in Figure 3.13.

Figure 3.13 The driver equivalent model In (3.2), the current (I) is equal to

and (3.2) can be rewritten to

R vdd by parallel resistors. The FSM is needed here. This FSM can control how many resistors are parallel connected to guarantee the output swing. The state diagram of

FSM is shown in Figure 3.14.

Figure 3.14 State diagram

In Figure 3.14, V_refh and V_refl are the reference voltages.V_refh is lower than Vout, and V_refl is higher than V_outb. So we can control the output amplitude by changing V_refh and V_refl. According to state diagram, we can plot our calibration curve as shown in Figure 3.15.

Figure 3.15 Calibration curve according to state diagram

How can we guarantee the algorithm to be convergent and calibrates the output voltages to the wanted levels by control the parallel resistors? If we can prove following equations (3.6), (3.7), and (3.8), we can say this algorithm is convergent because V_out and V_outb are monotonic increasing and monotonic decreasing.

Vout > Vrefh Vout > Vrefh Voutb < Vrefl

Yes No

Voutb < Vrefl

Stop

)

whereR and_a R are the parallel resistors and n is the number of the parallel _b resistors. We can easily prove Equation (3.6) is correct.

Afterward we will show that Equation (3.7) is correct. In Figure 3.15, V_Ln and

) to m, soR_Hnis equal toR_Lm. This supposition makes calculation easily. We can get the Equation (3.12) after reduction

And in the same way, we also show thatV_H₍_n₋₁₎ is greater thanV_Hn. So we prove Equation (3.7) is correct.

Then we will discuss Equation (3.8).∆V_Hn and ∆V_H₍_n₋₁₎ in Figure 3.15 are the differences between high level and low level of V_out. They are given by

DD long and complex calculation, the reader can try to calculate and we do not show the process here. After reduction, we know that Equation (3.14) is greater than zero so

)

∆ is greater than∆V_Ln. Above the demonstration, we know that Equation (3.6), (3.7), and (3.8) are all correctly. So this algorithm is stable and convergent and Vout and V_outb are monotonic increasing and monotonic decreasing.

There are calculations by hand to demonstrate that this algorithm feasible. We get the values ofR_u, R_d , R_a and R_b in spice simulation under all corner cases and plot calibration curves after calculation as shown in Figure 3.16. The reader may find FF case is mission. Because it matches the output voltage in initial state, the FSM will not operate calibration function.

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