Second Stage

After first stage of the fine tuning process, the candidate already met error constraint. The second stage will reduce the fraction bit width under error constraint in order to minimize the hardware cost.

First, the every variable is set to half of sum of the lower bound and the bit width of the candidate, each bit width set is one combinations. We simulate the combinations.

Second, if any combination meets the error constraint, the combination which has the biggest ratio ( | △cost | / | △BER | ) are chosen. It means that the variable of the combination has the biggest hardware cost in the same bit error rate. For the combinations which do not meet the error constraint, the lower bounds of these combinations are updated to half of sum of the original lower bound and the bit width of the variables in the combinations. We repeat the procedure until the lower bound could not update anymore.

Finally, if the bit width set of the candidate is equal to lower bound, it means that the bit width could not be further reduced. We terminate the second stage of the fine tuning process and obtain the final result.

Figure 3.6 Flow of the second stage of fine tuning process

The total flow of the second stage of fine tuning process is showed in Figure

Figure 3.7 Simulated combinations for second stage of fine tuning process

Subsequently, we simulate |W| combinations. If there is more than one combination meeting the error constraint, we choose the combination k having largest ratio ( | △cost | / | △BER | ) and set wk to (wk + wk_LB) / 2. The variables in the combinations which meet the error constraint but have smaller ratio than combination k remain the same bit width in WFS. If combinations do not meet the error constraint, we set the lower bound of the changed variable in the combinations to half of sum of bit width of variable and its lower bound. We will check if there is variable equal to its lower bound. If it is, we remove the variable from |W| and put it into WLB.

Finally we will check if W is an empty set. If the W is an empty set, it means that W can not reduce anymore and we terminate the process. Otherwise, we repeat the procedure until the W is equal to lower bound.

Figure 3.8 Example of the first step of fine tuning first stage

The first stage of fine tuning process is showed in Figure 3.8. The figure indicates that there is no combination which meets the error constraint. Since there is no combination meeting the error constraint, the combination which has the smaller ratio ( | △cost | / | △BER | ) will be picked to be the new candidate. The procedure repeats because the bit error rate of new candidate does not meet the

Figure 3.9 Example of the second step of fine tuning first stage

The combination meets the error constraint in the first stage of the fine tuning process showing in Figure 3.9. After first choice of the combination, there are only two combination and the combinations are individually simulated. In these two combinations, only the first combination meets the error constraint. Even if the second combination has the smaller ratio ( | △cost | / | △BER | ), it does not meet the error constraint, so the first combination is chosen to be the new candidate and go to the second stage of fine tuning process.

Figure 3.10 Example of the first step of fine tuning second stege

The second stage of fine tuning process is showed in Figure 3.10. Lower bounds of three variables are 3, 4 and 2, so the bit width of first variable in the first combination is

(3 + 6) / 2 = 4.5

The bit width of first variable in the first combination is 4 because the bit

The first combination is chosen to be the new candidate and the process repeats because it is the only combination which meets the error constrain. The second combination does not the error constraint so the lower bound of the second variable is updated to 5.

Figure 3.11 Example of the second sep of fine tuning second stage

The end of the fine tuning process is showed in Figure 3.11. The bit width in the combinations is calculated in the same way. For two combinations, these combinations are simulated and both of they do not meet the error constraint.

The combinations do not meet the error constraint, and then we update the lower bound. Since the new lower bound is equal to the candidate, it means bit width can not reduce anymore, so we terminate the procedure. Final result is {4, 6, 2}.

Chapter 4

Experimental Results

4.1 Experimental Information

We use the OFDM system model which is provided in [15] and the systemC data type is used for our fixed point data format [18]. The main blocks in the receiver for finite bit width determination are the Fast Fourier transform (FFT), channel estimator and fine signal detection. For the bit width variables, we choose the most significant effect on the hardware complexity and bit error rate. Figure 4.1 shows the receiver architecture of OFDM system. Figure 4.2 shows fine signal detection function block. Figure 4.3 shows the channel estimator function block.

Figure 4.2 Fine signal detection of receiver

Figure 4.3 Channel estimator of the receiver

Either N-point FFT or IFFT needs ^Nlog N₂

2 multiplications, where N is the number of point. According to Figure 4.2, the pilot signal cancellation unit and the combiner unit need 8N multiplications for every two OFDM symbols. In Figure 4.3, the data interference cancellation unit and the pilot matching unit also need 8N multiplications for every two symbols. Furthermore, the coarse signal detection unit requires the same number of multiplications as the fine signal detection functional block, i.e. 8N multiplications per two OFDM symbols. The complexity is showed in the Table 4.1 and we assume that the complexity increases linearly as bit width increase to simplify demonstration.

Table 4.1 Complexity of the receiver

Variables w0 w1 w2 w3 w4 w5

Hardware Complexity(multiplication) 1024 2048 1024 1024 1024 1024

4.2 Experimental Results

In this section, we demonstrate three cases of the proposed algorithm for the OFDM system with error constraint of 0.0007, 0.001 and 0.001 and show how the proposed algorithm works.

Table 4.2 Upper bound and lower bound of the all variables Variables Upper Bound Lower Bound

The upper bound and the lower bound of the simulation with error constraint of 0.01 and SNR of 18 are showed in Table 4.2. We start the algorithm from the lower bound with {5, 8, 8, 6, 12, 6}. This candidate does not meet the error constraint, and then we start the fine tuning process.

The first stage of fine tuning process makes the candidate meet the error constraint in few simulation times. We set the w0, w3 and w5 to the upper bound and the candidate meets the error constraint. Then, we start the second stage of fine

Table 4.3 Result of the proposed algorithm

Table 4.4 Upper bound and lower bound of all variables Variables Upper Bound Lower Bound

The upper bound and the lower bound of the simulation with error constraint of 0.001 and SNR of 18 are showed in Table 4.4. We start the algorithm from lower bound with {8, 8, 8, 7, 13, 8}. This candidate does not meet the error constraint, and then we start fine tuning process.

The first stage of fine tuning process makes the candidate meet the error constraint in few simulation times. We set the w0, w3 and w5 to the upper bound and the candidate meets the error constraint. Then, we start the second stage of fine tuning process to reduce the total hardware complexity. After the 17^th simulation, we update lower bound and the candidate is already equal to the lower bound, so we terminate the fine tuning process and obtain the final results. The simulation result is showed in Table 4.5 below.

Table 4.5 Simulation result of the proposed algorithm

Table 4.6 Upper bound and lower bound of the all variables Variables Upper Bound Lower Bound

The upper bound and the lower bound of the simulation with error constraint of 0.0007 and SNR of 18 are showed in Table 4.6. We start the algorithm from the lower bound with {9, 8, 8, 8, 14, 9}. This candidate does not meet the error constraint, and then we start the fine tuning process.

The first stage of fine tuning process makes the candidate meet the error constraint in few simulation times. We set the w0, w2, w3 and w5 to the upper bound and the candidate meets the error constraint. Then, we start the second stage

Table 4.7 Result of the proposed algorithm

4.3 Comparison Results

In this section, we compare the simulation results with the algorithm proposed by S. Roy et al. [12], sequential search proposed by K. Han et al. [17] and the distortion and complexity measured by K. Han et al. [16] .

First, we compare the simulation results between proposed algorithm and the Roy’s algorithm. The comparison results of simulation times are showed in Table 4.8 below. The comparison results of hardware complexity are showed in Table 4.9 below.

Table 4.8 Simulation times of two algorithms Algorithms Roy's Algorithm Proposed Algorithm BER = 0.01 203(100%) 20(9.6%)

BER = 0.001 196(100%) 17(8.7%) BER = 0.0007 189(100%) 29(15.3%)

Average 196(100%) 22(11.2%)

Table 4.9 Hardware complexity of two algorithms Algorithms Roy's Algorithm Proposed Algorithm BER = 0.01 65536(100%) 60416(92.2%) BER = 0.001 71680(100%) 71680(100%) BER = 0.0007 84992(100%) 74752(88%) Average 74069(100%) 68949(93.1%)

Because we search the bit width between the upper bound, which is the start point of the algorithm proposed by S. Roy et al., and the lower bound. The proposed algorithm is almost ten times faster than Roy’s algorithm. Our algorithm also considers the hardware complexity as objective function, the hardware complexity results is better or equal to the algorithm S. Roy et al. proposed.

Second, we compare the simulation results between proposed algorithm, the sequential search in term of the complexity and distortion measurement (CDM).

The comparison results of simulation times are showed in Table 4.10. The comparison results of hardware complexity are showed in Table 4.11.

Table 4.10 Simulation times of three algorithms

Algorithms Sequential Search CDM Proposed Algorithm

BER = 0.01 30(100%) 30(100%) 20(66.7%)

BER = 0.001 30(100%) 30(100%) 17(56.7%)

BER = 0.0007 30(100%) 30(100%) 29(96.7%)

Average 30(100%) 30(100%) 22(73.3%)

Table 4.11 Hardware complexity of two algorithms

Algorithms Sequential Search CDM Proposed Algorithm BER = 0.01 59392(100%) 59392(100%) 60416(101.7%) BER = 0.001 66560(100%) 66560(100%) 71680(107.7%) BER = 0.0007 70656(100%) 70656(100%) 74752(105.8%) Average 65536(100%) 65536(100%) 68949(105.2%)

Because he proposed algorithm set four variables to the upper bound (w0, w2, w3 and w5) in BER = 0.0007, it will take more simulation times to reduce the hardware complexity.

It shows that the hardware complexity of the proposed algorithm is 5% more than CDM and sequential search averagely in Table 4.11. Because the proposed algorithm only set three variables to the upper bound in BER = 0.01 and 0.001 and four variables to the upper bound in BER = 0.0007, the bit widths of these variables have to be longer to meet the error constraint.

20 40 60 80 100 120 140 160 180 200 220

Figure 4.4 Comparison result of BER = 0.01

6.9

20 40 60 80 100 120 140 160 180 200

Figure 4.6 Comparison result of BER = 0.0001

The total comparison results are showed in Figure 4.4, Figure 4.5 and Figure 4.6. If the simulation result of the algorithm locates closer to the origin of the coordinates, it means the algorithm has fewer simulation times or less hardware complexity.

The comparison results of BER = 0.01, 0.001 and 0.0007 are showed in Figure 4.4, Figure 4.5 and Figure 4.6. The results of proposed algorithm are closer to the origin than other algorithms in the simulation times. It means proposed algorithm can obtain the result without increasing too much hardware complexity.

Chapter 5

Conclusion and Future Work

In this work, we proposed an algorithm that uses the lower bound and the upper bound to find the optimized bit width for the OFDM system. Proposed algorithm can reduce the simulation times than sequential search and CDM.

According to the simulation results, proposed algorithm can reduce almost 30% simulation times than CDM and sequential search. The proposed algorithm is almost ten times faster than the one proposed by S. Roy et al.

We only consider the variables of the OFDM system for the case study. We will conduct experiments on other systems in the future.

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