Comparison Results

In this section, we compare the simulation results with the algorithm proposed by S. Roy et al. [12], sequential search proposed by K. Han et al. [17] and the distortion and complexity measured by K. Han et al. [16] .

First, we compare the simulation results between proposed algorithm and the Roy’s algorithm. The comparison results of simulation times are showed in Table 4.8 below. The comparison results of hardware complexity are showed in Table 4.9 below.

Table 4.8 Simulation times of two algorithms Algorithms Roy's Algorithm Proposed Algorithm BER = 0.01 203(100%) 20(9.6%)

BER = 0.001 196(100%) 17(8.7%) BER = 0.0007 189(100%) 29(15.3%)

Average 196(100%) 22(11.2%)

Table 4.9 Hardware complexity of two algorithms Algorithms Roy's Algorithm Proposed Algorithm BER = 0.01 65536(100%) 60416(92.2%) BER = 0.001 71680(100%) 71680(100%) BER = 0.0007 84992(100%) 74752(88%) Average 74069(100%) 68949(93.1%)

Because we search the bit width between the upper bound, which is the start point of the algorithm proposed by S. Roy et al., and the lower bound. The proposed algorithm is almost ten times faster than Roy’s algorithm. Our algorithm also considers the hardware complexity as objective function, the hardware complexity results is better or equal to the algorithm S. Roy et al. proposed.

Second, we compare the simulation results between proposed algorithm, the sequential search in term of the complexity and distortion measurement (CDM).

The comparison results of simulation times are showed in Table 4.10. The comparison results of hardware complexity are showed in Table 4.11.

Table 4.10 Simulation times of three algorithms

Algorithms Sequential Search CDM Proposed Algorithm

BER = 0.01 30(100%) 30(100%) 20(66.7%)

BER = 0.001 30(100%) 30(100%) 17(56.7%)

BER = 0.0007 30(100%) 30(100%) 29(96.7%)

Average 30(100%) 30(100%) 22(73.3%)

Table 4.11 Hardware complexity of two algorithms

Algorithms Sequential Search CDM Proposed Algorithm BER = 0.01 59392(100%) 59392(100%) 60416(101.7%) BER = 0.001 66560(100%) 66560(100%) 71680(107.7%) BER = 0.0007 70656(100%) 70656(100%) 74752(105.8%) Average 65536(100%) 65536(100%) 68949(105.2%)

Because he proposed algorithm set four variables to the upper bound (w0, w2, w3 and w5) in BER = 0.0007, it will take more simulation times to reduce the hardware complexity.

It shows that the hardware complexity of the proposed algorithm is 5% more than CDM and sequential search averagely in Table 4.11. Because the proposed algorithm only set three variables to the upper bound in BER = 0.01 and 0.001 and four variables to the upper bound in BER = 0.0007, the bit widths of these variables have to be longer to meet the error constraint.

20 40 60 80 100 120 140 160 180 200 220

Figure 4.4 Comparison result of BER = 0.01

6.9

20 40 60 80 100 120 140 160 180 200

Figure 4.6 Comparison result of BER = 0.0001

The total comparison results are showed in Figure 4.4, Figure 4.5 and Figure 4.6. If the simulation result of the algorithm locates closer to the origin of the coordinates, it means the algorithm has fewer simulation times or less hardware complexity.

The comparison results of BER = 0.01, 0.001 and 0.0007 are showed in Figure 4.4, Figure 4.5 and Figure 4.6. The results of proposed algorithm are closer to the origin than other algorithms in the simulation times. It means proposed algorithm can obtain the result without increasing too much hardware complexity.

Chapter 5

Conclusion and Future Work

In this work, we proposed an algorithm that uses the lower bound and the upper bound to find the optimized bit width for the OFDM system. Proposed algorithm can reduce the simulation times than sequential search and CDM.

According to the simulation results, proposed algorithm can reduce almost 30% simulation times than CDM and sequential search. The proposed algorithm is almost ten times faster than the one proposed by S. Roy et al.

We only consider the variables of the OFDM system for the case study. We will conduct experiments on other systems in the future.

Reference

[1] H. Keding, M. Willems, M. Coors, and H. Meyr, “FRIDGE: A fixed-point design and simulation environment,” in Proceedings of IEEE Design, Automation and Test in Europe (DATE ’98), pp. 429–435, Paris, France, February 1998.

[2] G. A. Constantinides, G. J. Woeginger, “The complexity of multiple wordlength assignment,” Applied Mathematics Letter, 15(2): 137-140 (2002)

[3] Synopsys Inc. (2001). CoCentric SystemC Compiler Behavioral Modeling Guide.[online]. Avaible:www.synopsys.com

[4] Synopsys Inc. (2000). Synopsys CoCentric Fixed-Point Designer Datasheet [online]. Avaible:www.synopsys.com

[5] C.Fang, R. Rutenbar, T. Chen, “Fast, accurate static analysis for fixed-point finite-precision effects in DSP designs,” 2003 International Conference on Computer-Aided Design, ICCAD-2003., vol., no., pp. 275-282, 9-13 Nov. 2003

[6] D. Lee, A. Abdul Gaffar, R. Cheung, O. Mencer, W. Luk, and G. Constantinides,

“Accuracy-guaranteed bit-width optimization,” IEEE Trans. Computer-Aided Design Integrated Circuits and Systems, vol. 25, no. 10, pp. 1990-2000, Oct.

2006.

[7] W. Osborne, R.C.C. Cheung, J. Coutinho, and W. Luk, “Automatic accuracy guaranteed bit-width optimization for fixed and floating-point systems,” in IEEE International Conference on Field-Programmable Logic and Applications (FPL), Netherlands, Aug, 2007.

[8] C.Fang, R. Rutenbar, Puschel M. and T. Chen, “Toward efficient static analysis of finite-precision effects in DSP applications via affine arithmetic modeling,”

Design Automation Conference, 2003. Proceedings , vol., no., pp. 496-501, 2-6 June 2003

[9] H. Choi and W. P. Burleson, “Search-based wordlength optimization for VLSI/DSP synthesis,” in Proceedings of IEEE Workshop on VLSI Signal Processing, VII, pp. 198–207, La Jolla, Calif, USA, October 1994.

[10] W. Sung and K. I. Kum, “Simulation-based word-length optimization method for fixed-point digital signal processing systems,” IEEE Transactions on Signal Processing, vol. 43, no. 12, pp. 3087–3090, 1995.

[11] J. Babb, M. Rinard, C.A. Moritz, W. Lee, M. Frank, R. Barua, S. Amarasinghe,

“Parallelizing applications into silicon,”Field-Programmable Custom Computing Machines, 1999. FCCM '99. Proceedings. Seventh Annual IEEE Symposium on , vol., no., pp.70-80, 1999

[12] S. Roy and P. Banerjee, “An algorithm for trading off quantization error with hardware resources for MATLAB based FPGA design,” IEEE Transactions on Computers, Vol. 54, Issue 7, July 2005.

[13] A. Mallik, D. Sinha, H. Zhou, and P. Banerjee, “Low power optimization by smart bit-width allocation in a SystemC based ASIC design environment,”IEEE Transactions on Computer Aided Design of Integrated Circuits, to appear, 2006.

[14] C.Y. Wang, C.B. Kuo, and J.Y. Jou, “Hybrid wordlength optimization methods of pipelined FFT processors,” IEEE Transactions on Computers, Vol. 56, No. 8, pp.

1105-1118, August 2007. (SCI,EI)

[15] M.L. Ku and C.C. Huang “A complementary codes pilot-based transmitter diversity technique for OFDM systems,” IEEE Transactions on Wireless Communication 5(3): 504-508 (2006)