In this thesis, for the first time, we have developed a new DC-IV measurement, called βDC-IV measurement. The main idea of this measurement is to boost the DC-IV current level to exceed the gate-leakage current, and then we use shift and subtract method to extract the pure DC-IV current. This approach has been demonstrated for the devices with the thickness of gate-oxide down to 13A0.
Based onβDC-IV measurement, a new interface-traps lateral profiling technique has been built for the first time. The main concept of this technique is to find where the recombination and generation processes happen in the maximal probability, which can be described by the positions in which the intrinsic energy level is equal to the average of the sum of the p and n quasi Fermi levels.
In this thesis, each kind of schemes to design highly reliable CMOS devices by introducing various strain technologies has been proposed. Based on the results given by the experiments of HC stress and FN stress in application of IFCP and interface-traps lateral profiling technique, two main conclusions on the HC for strained nMOSFETs and NBTI for strained pMOSFETs have been provided: (1) For strained nMOSFETs, CSEL capping layer devices are much better in terms of reliability and performance than others devices. SSOI devices have good hot-carrier immunity and performance, but its channel interface quality has to be improved. The performance for SiC devices is good, but its defects of interface and junction are its disadvantage. SiGe on substrate devices own appreciated performance, but the Ge-out
diffusion effect is so serious that this kind of devices will be un-reliable. (2) For strained pMOSFETs, SiGe on S/D devices will be much better in terms of performance, HC, and NBTI reliability, but SiGe on channel devices have worse NBTI property and are complex to be made, which makes this kind of devices un-valuable. All of the descriptions above are summarized in Table 6-2. As a result, keeping with the progress of strain technology, it is necessary to make a trade-off and find the best strategy to improve the performance and keep reliable in the same time, which is a challenging task. All these results in this thesis will be valuable to design manufacturable CMOS devices in terms of performance and reliability down to 45 nm technology node and beyond.
Table 6-1 The summary of strained CMOS devices in terms of performance and reliability in this thesis.
Ge-out
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