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A New Direct-Current Current-Voltage (DC-IV) Method- Boosted DC-IV (βDC-IV)

3.3 The Theory of Gated-Diode (GD) Measurements

The theory of Gated-Diode measurement is based on the SRH recombination and generation process of p-n Junction, but the gate terminal is added to control the form and position of the surface depletion region of p-n junction. Fig. 3-3 shows the schematic diagram of this concept. When drain-to-bulk (p-n) junction is formed, the space charge region (SCR) is set. With a junction bias (a reverse or forward bias), the recombination current contributed by the defects in SCR will flow. We can monitor the SCR quality of the junction by the amount of the recombination current. The higher the recombination current is, the worse the junction quality becomes. If we assume that a board and uniform energy distribution of the defects around the intrinsic

level –Φi, and the defect capture cross section for electrons is the same as that for holes (i.e., σnp=σ), the distribution of defects will be set as a Gaussian distribution from Φh toΦe, and the maximal value will exist atΦi. Thus, we can simply assume the main place where the recombination-generation process happens in the maximal probability is at the intrinsic level, which is the narrow region- △X in Fig. 3-3.

As the gate bias is applied on the surface of the junction, the position of SCR near this surface will be modulated by the gate bias. When the channel under the Si/SiO2 is accumulated with a suitable gate bias, the SCR of p-n junction near the surface will be bended into the drain region due to the distribution of the electric field from gate to drain, as shown in Fig. 3-4(a). Thus, we can monitor the recombination current caused by defects in SCR of the drain side. When the channel under the Si/SiO2 is depleted with a suitable gate bias, the SCR of p-n junction near the surface will be extended to the bulk region, as shown in Fig. 3-4(b), and then we can monitor the recombination current conduced by the defects around the intrinsic level in SCR of the channel region. If the gate bias is further increased so that the channel is inversed, SCR under the interface of Si/SiO2 will be drowned by the minority carriers in bulk, and the recombination and generation process beneath surface will stop.

Therefore, the recombination current can not be observed. As a result, we can control where the recombination-generation process happens through the modulation of the form and position of SCR with the sweep of the gate bias.

The excess recombination current can be expressed as, [29]

1 ( ) ( ) exp( )

2 2

pn

R G G i

I qW s x x V n qV

= kT (3-1)

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Fig. 3-3 The schematic diagram of gate voltage modulating the depletion region of drain to bulk diode.

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Fig 3-4(a) The SCR form of the junction with channel accumulation under suitable gate bias. Note the SCR near the surface is bended into the drain region.

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Fig 3-4(b) The SCR form of the junction with channel depleted under suitable gate bias. Note the SCR near the surface is extended to the bulk region.

where W is the device channel width, and q is the unit charge, and △s(x) is the surface recombination rate, and x is the position where the electron and hole concentrations are equal, and ni represents the intrinsic concentration of the material.

Note △s(x) is proportional to the interface Nit around mid-gap which acts as the recombination centers, e.g.,

( )

th it

( )

s x = σ v N x

(3-2)

where vth is the thermal velocity. The values of σ and vth used here are 1×10-15 cm2 and 1×10-17 cm/sec, respectively. From equations (3-1) and (3-2), we can relate the Nit

to the gated-diode recombination current in terms of where recombination and generation process occurs. By comparing the gated-diode current after stress with that before stress, we can understand the stress degradation mechanism of the interface for the tested device.

In the last part of this section, we make a comparison of DC-IV measurement and GD measurement, as shown in Table 3-2. The same idea of both is to use the recombination-generation process in SCR by sweeping the gate bias to sense the interface defects under Si/SiO2 from channel to drain. The difference is that DC-IV performs the BJT operation to achieve this goal, but GD only performs diode to achieve this goal. Thus, DC-IV has to use four-terminals (gate, drain, well, and substrate) measurement to realize this idea, but GD only uses three-terminal (gate, drain, and well) measurement. Next, we compare the operation schemes of both methods. DC-IV uses a small forward junction bias to enforce the forward current from the emitter to the collector, but GD can not only be employed in a forward junction bias but also in a reverse junction bias. However, until now both these approaches have been only implemented in the junction voltage smaller than turn-on voltage, which is because it is hard to separate the recombination current from the forward diffusion current when the junction turns on. Moreover from historical

reasons, the recombination current of DC-IV is measured from the well terminal, but that of GD is measured from the drain terminal. In fact, it is okay once can measure the DC-IV or GD either from the well terminal or the drain terminal.

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Table 3-2 The comparison of DC-IV and GD measurements.

3.4 The Theory of Boosted DC-IV( βDC-IV )

The challenge of GD measurement for the ultra-thin gate oxide devices is the gate-leakage during the measurement. When the thickness of the gate oxide is thinner than 20A0, the current level of gate leakage current is comparable to or even higher than the gated-diode current. Many researches have put much effort on how to suppress the gate leakage current so that the gated-diode current can be observed. In 2002, Chung and Lo developed a smart technique, “Low leakage Gated-Diode, [20]”

which has been applied in the gate oxide reliability study whose gate thickness of the tested devices is thinner than 20A0. Furthermore, in 2005, Chung and Lee[30] also reported another bright measurement, “Twin Gated-Diode,” which has been implemented in the gate-oxide reliability study whose gate thickness of the tested device is thinner than 16A0. In this section another measurement technique is

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