In this chapter, excellent basic properties of CDO film including low dielectric constant (lower than 2.3) after annealing at 600°C, good thermal stability (no FTIR spectrum change after annealing at 650°C), very little thickness shrinkage (less than 3% after annealing at 650°C), and low leakage current (lower than 1nA/cm2 at 30°C and 2.5MV/cm) are confirmed in this work.
Our investigation discovered that the lacking formation of Al2O3 interfacial layer caused Al ions to migrate into CDO film and CDO porous structure would enhance metal ions movement in it. Although both Al and Cu ions can be driven into CDO under electrical stress, no metal ions are observed in CDO with TaN gate.
properties reported previously, CDO is still a very promising material for next generation Cu-interconnect technology. Besides, an electrical instability model considering metal ions diffusion, dielectric polarization, and carrier injection, was proposed to explain the observed electrical instability phenomenon of the CDO film under electrical stress. And this model would be applied to study on all other low-k dielectrics’ electrical instability behaviors.
It is concluded that Al and Cu are not suitable metal to contact with CDO film directly because Al ions and Cu ions can be driven into CDO film easily. Fortunately, TaN, a barrier metal for Cu-interconnect system, shows no mobile ions issues when direct contact with CDO film. Electron transport mechanism is identified to be Schottky emission at low electric field and low temperature. As metal ions are injected into CDO film, for example Al and Cu, electron transport mechanism changes to Frenkel-Pool emission at high temperature and high electric field. The injection of metal ions into CDO film also degrades the TDDB lifetime of the film.
Fortunately, the commonly used Cu diffusion barrier TaN is an excellent contact metal with CDO film. The 10 years TDDB lifetime allows an electric field stronger than 2 MV/cm and the TDDB lifetime at 0.5MV/cm becomes longer than 10 years by several orders of magnitude. It is thus concluded that the nano-porous ultra low dielectric constant CDO film is a very promising inter-metal dielectric material for
next generation interconnect system.
References
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Table 3-1 Flat band voltage shift of MIS structures with various metal gate materials after BTS test at 0.6MV/cm for 30 minutes
Temperature Al-CDO-1 Cu-CDO-1 TaN-CDO-1 Pt-CDO-1 Al-CDO-2 (V)
30°C -7.48 V -3.2 V -2.74 V -1.59 V -0.07
150°C ＜-40 V ∼-40 V -9.6 V -6.23 V -5.12
Table 3-2 Results of pull-stud adhesion test of different metal/CDO interface and Al/SiO2 interface
Al/CDO Cu/CDO TaN/CDO Al/SiO2
Average (MPa) 16.82 19.1 51.92 47.02
Standard Deviation (MPa) 5.62 9.53 11.46 7.37
Table 3-3 Flat band voltage shift of Al-CDO-1 sample after annealing at 400℃ for various time periods
CDO 0 hour 2 hours 8 hours
Average (V) -1.59 -2.73 -3.52
Standard deviation (V) 0.24 0.31 0.33
N-Si Metal
CDO
SiO2
N-Si Al CDO
N + -Si Al CDO Al-CDO-MIM
PECVD SiO2
Metal-CDO-1 (Al,Cu,TaN,Pt)
Al-CDO-2
SiO2
Fig. 3.1 Schematic drawings of the MIS structures used in this work. Metal-CDO-1 : Metal/ CDO (200 nm)/ SiO2 (10 nm)/n-Si. Al-CDO-2 : Al(500 nm)/ PECVD SiO2 (30 nm)/ CDO (200 nm)/ SiO2 (10 nm)/n-Si. Al-CDO-MIM : Al (500 nm)/ CDO (200 nm)/n+-Si.
4000 3500 3000 2500 2000 1500 1000 500
Fig. 3.2 (a) FTIR spectra and (b) thickness shrinkage and dielectric constant variation of CDO film after thermal annealing at different temperatures.
0.0 0.5 1.0 1.5 2.0 2.5
Fig. 3.3 (a) Current density-electric field characteristic of Al-COD-MIM sample measured at different temperatures. (b) The breakdown characteristics of
-40 -20 0 20 40 10
20 30 40 50 60 70
Original RVS
FVS
Capacitanc e (pF)
Voltage (V)
Fig. 3.4 Capacitance-voltage curves of Al-CDO-1 sample measured from inversion mode to accumulation mode (FVS) and from accumulation mode to inversion mode (RVS)
-20 -15 -10 -5 0 5 10
20 30 40 50 60 70
Capacitance(pF)
Voltage (V)
Origin -2MV/cm +2MV/cm
Fig. 3.5 Capacitance-voltage curves of Al-CDO-1 sample after electrical stress at -2MV/cm and +2MV/cm fro 4 minutes.
0 500 1000 1500 2000 2500 3000
0 500 1000 1500 2000
100
Fig. 3.6 SIMS depth profiles of (a) Al-CDO-1 sample and (b) Cu-CDO-1 sample
0 500 1000 1500 2000 2500 10
010
110
210
310
410
5SiO
2Si
Ta before BTS
CDO substrate
Ta after BTS
Counts (arb. units)
Depth (A)
Fig. 3.7 SIMS depth profiles of TaN-CDO-1 sample before and after BTS test at +1 MV/cm and 200℃ for 60 min.
0 500 1000 1500 2000 10
010
110
210
310
410
510
6Ohr
2Hr 8Hr
Si SiO
2CDO Si Substrate
Counts (arb. units)
depth (A)
Fig. 3.8 SIMS depth profiles of Al-CDO-1 samples after annealing at 400℃ for various time periods
-40 -30 -20 -10 0 10 20 30 40 20
25 30 35 40 45 50 55
FVS RVS
Original
Capcitrance(pF)
Voltage (V)
Fig. 3.9 Capacitance-voltage curves of Al-CDO-2 sample with different voltage ranges and different sweep directions.
-16 -12 -8 -4
Fig. 3.10 Capacitance-voltage curves result of Al-CDO-2 sample after BTS at (a) room temperature and (b) 150°C. The electric field is 0.6MV/cm
2.2 2.4 2.6 2.8 3.0 3.2 3.4 -3
-2 -1 0 1 2
Ea=0.39eV Linear Fitting
ln|V fb shif t|
1000/T (
oK
-1)
Fig. 3.11 Arrhenious plot of the dielectric polarization of CDO film.
250 500 750 1000 1250 1500
250 500 750 1000 1250 1500 -38
Fig. 3.12 The J-E characteristic of Al-CDO-MIM sample can be well fitted by (a) Schottky emission model at low temperature and low electric field and (b) Frenkel-Poole model at high temperature and high electric field.
250 500 750 1000 1250 1500 -38
-36 -34 -32 -30 -28 -26
Schottky Emission
LN(J/T 2 )
E
1/2(V/cm)
1/230C 100C 150C 200C
Fig. 3.13 The J-E characteristic of Al-CDO-2 sample at negative gate voltage can be well fitted by Schottky emission model from room temperature to 200°C.
Metal Metal
N-Si SiO
2N-Si SiO
2CDO + CDO
-+ ions - electrons+
Fig. 3.14 Proposed model to explain the observed electrical instability of Metal-CDO-1 capacitors.
10 100 1000 10000 100000
Fig. 3.15 The cumulative TDDB failure of Al-CDO-1, Cu-CDO-1 and TaN-CDO-1 samples stressed at 1MV/cm, 1MV/cm, and 3.5MV/cm, respectively. The temperature is 200°C.
0 1 2 3 4 5 10
-110
010
110
210
310
410
510
610
710
810
910
10TDDB lifetime of TaN-MIS 10 years
200
oC
M eantime to Fail @ 50% (sec)
Electrical Field (MV/cm)
Fig. 3.16 Extrapolation of TDDB lifetime of TaN-CDO-1 sample at 200°C according to E-model.
Chapter 4
Low Dielectric Constant Diffusion Barrier Film Silicon Carbide For Copper Interconnect
4.1 Introductions
Copper (Cu) has been recognized as the most suitable alternative for aluminum as wiring material because of its low electrical resistivity and excellent electromigration resistance [1,2]. Dual damascene process is the well-accepted patterning technology because Cu film is hard to be patterned by plasma etches. It is also known that Cu is a serious contamination source for both silicon and silicon dioxide. To prevent Cu from diffusion into IMD, Cu must be sealed using diffusion barriers. Fig. 4.1 shows the typical Cu interconnect structure. The main IMD is some kind of low dielectric constant (low-k) materials. A dielectric diffusion barrier layer must be deposited on Cu wires to seal Cu and serve as etch stop layer during via hole etch of the next metal layer. The same material is usually used as etch stop layer during trench etch if necessary. Silicon nitride (SiN) is the currently used material because it has been used as a masking and passivating layer for a long time to against diffusion of metal ions and moisture [3-5]. Unfortunately, the relative high dielectric
constant IMD [6]. The impact of SiN on interconnection capacitance increases with the decrease of dielectric constant of main IMD. Therefore, a newly developed dielectric barrier material amorphous SiC (a-SiC, simplified as SiC herein after) attracts more attentions recently [7]. It is also regarded as the only one candidate to replace SiN as dielectric diffusion barrier and etch stop layer [6-7].
The SiC film can be deposited in chemical vapor deposition (CVD) system using Trimethylsilane (3MS) as a precursor. Film with good material properties of low dielectric constant (<5), low film stress, high thermal stability, high breakdown field (>2MV/cm), and low leakage current at room temperature had been reported [12].
However, almost no study has been performed to electrically emphasize the stability and reliability issues of SiC film.
In this chapter, we evaluate the dielectric barrier effectiveness for Cu penetration with regard to SiC film with different deposition conditions. The electrical reliability and electrical instabilities of SiC film were reported for the first time. The film was stressed at various electric field and temperature. The instabilities were evaluated by the capacitance-voltage (C-V) characteristic of the metal/insulator/Si (MIS) capacitor.
The effects of electric field, polarity, and temperature were studied. Two mechanisms were proposed to explain the observed electrical instabilities at high and low electric field. The carrier transport mechanism through SiC film was also identified.
4.2 Experimental Details
Simple MIS capacitor structure was used to study the electrical stability of SiC film. The starting material is boron-doped (100)-oriented 8-inches Si wafer. The resistivity is 2-4 ohm-cm. To minimize the influence of interface instability, a 10 nm thick SiO2 was thermally grown before the deposition of SiC film. The MIS structures can be divided into three categories. The film structure of Al-SiC-1 sample is Al(500 nm)/SiC(90 nm)/ SiO2 (10 nm)/Si. Most samples are in this structure and they were used to study the electrical stability of SiC film. MIS structure using Cu gate and heavily doped n-type Si substrate was fabricated (Cu-SiC-MIM) to study the SiC barrier properties. The sandwiched structure is Cu(500 nm)/SiC(90 nm)/n+-Si. The film structure of Cu-SiC-1 sample is Cu(500 nm)/SiC(90 nm)/Fluorinated Silicate Glass (FSG)(450 nm)/ SiO2 (10 nm)/Si. It is used to evaluate the barrier ability of SiC against Cu diffusion. The structure of reference sample is Cu(500 nm)/FSG(750 nm)/
SiO2 (10 nm)/Si and is denoted as Cu-FSG-1. Because of the existence of thermal oxide and the work function difference between gate and substrate, the above structures are asymmetric. Almost symmetric MIS structure using Al gate and heavily doped n-type Si substrate was fabricated (Al-SiC-MIM) to study the carrier transport mechanism. The sandwiched structure is Al(500 nm)/SiC(90 nm)/n+-Si The simplest Al(500 nm)/ SiO (10 nm)/Si structure (Al-SiO2-1) was also fabricated to make sure
the quality of the 10 nm thick SiO2 and the SiO2/Si interface. Fig.4.2 shows the schematic drawings of the six sample structures.
FSG film was deposited in a high-density-plasma chemical vapor deposition system (HDPCVD) and SiC films were deposited plasma-enhanced chemical vapor deposition system (PECVD). The SiC films were deposited at 400 ℃ using 3MS organosilicon gas as a precursor with N2 and/or N2O as carrier gas. Table 4-1 lists the deposition conditions of three different SiC films denoted as SiC(1), SiC(2), and SiC(3). The metal gate is wet etched to 800umx800um in square shape. For those samples will receive high temperature measurement, a 30 nm thick SiN layer was deposited on sample surface to prevent samples from oxidation.
The thickness of the deposited SiC film was measured by ellipsometry method with multi-angle and multi-wavelength. The dielectric constant of the SiC film was calculated from the capacitance of MIS-2 structure at zero voltage or MIS-1 structure at accumulation mode. The effect of 10 nm thick thermal oxide was corrected using the MIS-3 structure. Moisture uptake was evaluated by thermal desorption spectroscopy (TDS). The atomic composition was determined by Rutherford Backscattering Spectrometry (RBS) analysis and the major chemical bonds were identified using Electron Spectroscopy for Chemical Analysis (ESCA).
Capacitance-voltage (C-V) measurement was performed to evaluate the SiC film
stability using an impedance meter of model Agilent 4284A. Bias temperature stress (BTS) tests under various temperatures and electric fields were performed. Flat-band voltages before and after BTS were extracted from high frequency (100 KHz) C-V characteristic with voltage swept either from accumulation mode to inversion mode (forward voltage sweep, FVS) or from inversion mode to accumulation mode (reverse voltage sweep, RVS).
4.3 Study on Silicon Carbide Films
4.3.1 Fundamental Properties of Silicon Carbide Films
Fundamental properties of the deposited SiC film were characterized at first. The dielectric constant of the SiC films calculated from Al-SiC-1 structure is listed in Table 4-2 and is apparently lower than the dielectric constant of silicon nitride. TDS analysis shows the moisture out-gassing of three different SiC films after storage in cleanroom environment for 2 weeks. SiC(1) film exhibits a little more moisture out-gassing then the others two SiC films (Fig. 4.3). Because the deposited SiC(2) and SiC(3) films are very inert to moisture, the Al-SiC-1 samples with SiC(2) film stored in non-cleanroom environment show identical high frequency C-V characteristics to the as-fabricated samples.
In order to evaluate the barrier property of SiC films again Cu diffusion, continuous BTS were performed on Cu-SiC-MIM structure at +2MV/cm and 200℃
for 500 minutes. Fig. 4.4 shows the BTS results of the three SiC films. SiC(2) shows the best Cu barrier property then SiC(3) and SiC(1) shows the worst barrier property.
Besides, continuous BTS tests of SiC(2) at +1 MV/cm and 200 ℃ were performed on the Cu-SiC-1 and Cu-FSG-1 samples. Fig. 4.5(a) compares the flat-band voltage (Vfb) shift of the two samples. It is obvious that Cu was driven into FSG film during BTS and cause flat-band voltage shift on the samples without diffusion barrier layer (Cu-FSG-1). On the contrary, very small Vfb shift was observed on the samples with SiC barrier layer after BTS for two hours. Fig. 4.5(b) shows the C-V characteristics of the Cu-SiC-1 sample after BTS for various lengths of time. Only slightly C-V shift was observed after BTS. Although the small flat-band voltage shift might be attributed to slightly Cu ions drift into SiC film, we will show that the instability of SiC film also plays role on the small flat-band voltage shift later at next section.
Fig. 4.6(a) and (b) show the leakage current versus time of the Cu-SiC-MIM capacitors biased at 2 MV/cm and 150℃ and 3 MV/cm and 200℃, respectively. It is observed that by increasing the nitrogrn content, the leakage current can be suppressed effectively. But moderate nitrogen content (SiC(2)) results in the longest TDDB lifetime. It is possible that the gas ratio and composition during SiC deposition affect the micro-structure of the film which in turn affect the dielectric constant, leakage current, and TDDB lifetime. Table 4-2 listed the summarized basic
characteristics of three different SiC films.
4.3.2 Electrical Instability of SiC Films
In previous section, SiC films deposited at different deposition conditions were compared. SiC(2) film was chosen for further study. All of the above results indicated that the SiC(2) film is similar to or better than that reported in [6]. However, the hysteresis phenomenon was coincidentally found. During the measurement of C-V characteristics of the Al-SIC-1 samples, we found it unexpectedly that there was serious Vfb shift after wide range voltage sweep.
Fig. 4.7 shows the high frequency C-V characteristics measured in both of the FVS and RVS modes for two cycles. The original curve was measured in the FVS mode with voltage swept from –10 V to +10 V. Because the total dielectric thickness including SiC film and thermal oxide is 100 nm, the maximum electric field is about 1MV/cm. The original C-V curve looks like a normal C-V curve of a typical MIS capacitor. However, as the voltage range is expanded to ±40 V, the C-V curve shifted apparently. In the FVS mode, the C-V curve shifted toward the positive voltage axis, while in the RVS mode, the C-V curve shifted toward the negative voltage axis. The magnitudes of Vfb shift in both directions are almost identical and the C-V curves are almost overlapped in continuous FVS and RVS measurement cycles. Table 4-3 lists
the flat band voltages measured by FVS and RVS sweep modes with various voltage ranges. It is found that there is a threshold voltage of about 18 V (~1.8 MV/cm). With electric field lower than 1.8 MV/cm, no hysteresis phenomenon would occur.
Although the C-V characteristic is stable under room temperature and low field measurement, low electric field stress at high temperature still results in instability of the Al-SiC-1 capacitor. Fig.4.8(a), (b), and (c) show the C-V curves measured at room temperature after BTS at 200 ℃ and ±0.4, ±0.5, and ±0.6 MV/cm, respectively, for 3 hours. It is obvious that the C-V curves distorted and shifted after BTS. Except serious increase of interface state density, the magnitudes of Vfb shift after positive and negative electrical field stress are asymmetric. It is quite different with that shown in Fig.4.7. Fig.4.9(a) and (b) show the C-V curves measured at room temperature after BTS at 150 and 175 ℃, respectively, for 3 hours. The electric field was fixed at ±0.5 MV/cm. The shift and distortion of C-V curves were also observed but the magnitude decreased with the decrease of the BTS temperature. These results indicate that a much lower electric field at high temperature can cause asymmetric instability.
Furthermore, the mechanism of asymmetric instability should be temperature dependent.
4.3.3 Dielectric Polarization
Preliminary C-V measurements of the SiC film (Al-SiC-1 structure) demonstrated certain instabilities that are not typical of MIS structures incorporating clean thermal oxides. The instabilities are prevalent, even at room temperature, to such a degree that reliable C-V characteristic is difficult to be measured. There are four possible mechanisms may cause dielectric instability : (a) the 10 nm thick thermal oxide is unstable; (b) the SiC film is contaminated by mobile ions such as Na, K, Cu, etc.; (c) the SiC film is polarized under electric field; (d) charges are injected into SiC film under electric field. In the following subsections, these mechanisms are examined by further experiments.
The quality of the 10 nm thick thermal oxide was examined firstly. A simple Al/
The quality of the 10 nm thick thermal oxide was examined firstly. A simple Al/