Summary

LTPS technology has many advantages such as high resolution, large size, low-cost, higher mobility than a-Si process. This technology is thus suitable for SOP-LCD applications. With SOP-LCD, it may be possible to integrate the keyboard, CPU, memory, and display into a single “sheet computer”. However, power issue is an important issue in SOP-LCD applications. Therefore, power reduction in SOP driver circuit has become one of the major challenges and research topics.

~ 9 ~

1.2 Background Knowledge of Thin-Film Transistors Liquid Crystal Displays

1.2.1 Brief Introduction of Liquid Crystal Displays [8], [9]

There are many kinds of liquid crystal. The twist of liquid crystals can be controlled by the electric field that is applied across it, liquid crystals are used as a switch that passes or blocks the light. The polarizer can block or pass the specific light by changing the phase of the polarizer. There are two polarizers including the first polarizer called polarizer and the second polarizer called analyzer. If the couple of polarizers have 90° phase error, the light can be blocked which is shown in Figure 1.

(a). But if we twist the liquid crystal molecule by applying the specific electric field across it, the light still can pass the polarizer. This is because the direction of liquid crystal molecules varies with electric field and it can guide the light along the long axis, shown in Figure 1. (b).

Figure 1.9 (a) A couple of polarizers with 90° phase error. (b) A couple of polarizers with liquid crystals.

(a)

(b)

~ 10 ~

Figure 1.10 The structure of a TN-LCD (a) while light is passing, and (b) while light is blocked. a: polarizer; b: glass substrate; c: transparent electrode; g: orientation layer; e:

liquid crystal; f: illumination.

In Figure 1.1 (a), it shows a pixel of a transmissive twisted nematic LC-cell without voltage applied. The white backlight f passes the polarizer a. The light leaves it linearly polarized in the direction of the lines in the polarizer. In this case, the analyzer is crossed with polarizer. The light can pass the analyzer without applied voltage and the pixel appears white. This operation is called the normally white (NW) mode.

If a voltage V_LC of the order of 10 V is applied across the cell, as shown in Figure 1.1 (b), all molecules aligned parallel to the electric field. In this situation, the wave is polarized in the same direction as at the input. Therefore, the analyzer blocks the light and the pixel appears black. This is called the normally black (NB) mode.

1.2.2 Liquid Crystal Display Module Structure

The cross section structure of TFT-LCD panel is shown in Figure 1.11. There are two parts of liquid crystal filled in the center of LCD panel including TFT array substrate and color filter substrate. A backlight module contains an illuminator and a light guilder because liquid crystal molecule cannot light by itself. Usually this part

~ 11 ~

consumes the most power of the system. There are a polarizer, a glass substrate, a transparent electrode and an orientation layer in TFT array substrate. In color filter substrate, it is composed of an orientation layer, a transparent electrode, color filters, a glass substrate and a polarizer. Transparent electrodes can control the directions of liquid crystal molecules in each pixel by voltage supplied from TFT on the glass substrate. Color filters contain three original colors, red, green, and blue (RGB). The degree of light called “gray level” can be well controlled in each pixel covered by color filer to get more than million kinds of colors.

Figure 1.11 The cross section structure of TFT-LCD panel.

1.2.3 Driving Method [10]

Liquid crystal molecules need to do inversion because the DC blocking effect and the DC residue (stick image) will be appeared under a fixed voltage in the long period.

Therefore, the electric field polarity should be inversed every period to avoid the destruction of liquid crystals. The torque caused by electric filed is related to the magnitude of electric filed instead of the polarity of electric filed. Therefore, the polarity of electric filed would not affect the twisting of the liquid crystal molecules. If

~ 12 ~

the electric field across liquid crystals is changed into two polarities (positive and negative) with the same magnitude alternately, the frame picture can still be kept on the same gray level. If electric field is higher than common mode voltage the polarity is called positive polarity, otherwise it is called negative polarity. By this way, the liquid crystal molecules can avoid defection under the applied voltage with same magnitude. From the description above, the polarity inversions of LCD panel can be divided into four general types: frame inversion, row inversion, column inversion, and dot inversion which are shown in Figure 1.4 [10]. Dot inversion is the major driving method of LCD panel because by this method, we can achieve to higher quality image due to the reduction in both horizontal and vertical cross-talk. The flicker of image also can be reduced due to the spatial averaging of pixels. But the price of this method is an increase of the power consumption due to the line inversion component. This method is also incompatible with common voltage modulation.

Based on the operational type of common mode voltage, the driving method can also be classified into DC modulation driving and AC modulation driving which are shown in Figure 1.13. DC modulation driving method would keep its common voltage on a constant level. However, the common mode voltage of AC modulation driving method is not a constant level, is a period voltage. DC modulation driving method can eliminate the crosstalk and flicker; however, this driving method will cause more power consumption. AC modulation driving method can lower the power dissipation in data driver, but only frame and row inversion are available for this driving method.

~ 13 ~

Figure 1.4 The polarity inversions of TFT-LCD panel.

~ 14 ~

(a)

(b)

Figure 1.5 (a) The operation waveform of DC modulation driving method and (b) the operation waveform of AC modulation driving method.

1.3 Thesis Organization

The fundamentals and realization of the time-modulation pixel memory are discussed in chapter 2. Then, the concept and simulation results of the two-direction cyclic DAC are discussed in chapter 3. In the last chapter, the conclusions of this thesis and the future work are stated.

~ 15 ~

Chapter 2

Fundamentals and Realization of Time-modulation Pixel Memory

2.1 Introduction

2.1.1 Embedded Pixel Memory

The LCD frame can be separated into normal mode and still mode. The normal mode is that the frame of LCD is changing continuously. The still mode means that the frame of the LCD is static. However, conventional LCD driver produces data and sends it into pixel through data line even these data are all the same because it is a static frame. The concept of the embedded pixel memory is that the LCD is driven by only the pixel circuit when displaying a still image. This means that no charging current to the data line, which has a large load capacitance, is required. And only a small charging current to the pixel capacitor is necessary. This results in an ultra-low-power operation. Figure 2.1 shows the basic concept of pixel memory technology [3].

Figure 2.6 Basic concept of pixel memory technology.

~ 16 ~

Figure 2.2 shows the power consumption trend of an LCD driver with various resolutions [3]. With this pixel memory technology with reflective color LCD technology, a very attractive display having an ultra-low-power characteristic as well as high image quality can be realized. Also, it has low-cost property because the frame memory is integrated in the display. The total power consumption of an LCD module is actually dominated by the lighting system such as a frontlight and a backlight. Therefore this pixel memory technology should be applied to a reflective LCD or a transflective LCD. In a reflective LCD, the pixel memory circuit can be effectively integrated under the reflective pixel electrode without any optical loss. The power consumption remains very low in most case. However, the LCD requires a frontlight system when it is used in a very low ambient light environment, which results not only in a high consumption of power but also degrades the image quality even in a normal environment. In a transflective LCD, the above problem relating to the image quality can be solved. A backlight system can be used instead of a frontlight for very low ambient light conditions. Also, it can have two different operating modes in normal ambient light conditions; an ultra low power mode which is operated by the pixel memory circuit without a backlight, and a high picture quality mode which is operated by the pixel memory or conventional driver circuit with the backlight turned on. The drawback is that the transmissive aperture area is limited to some level, according to the display specifications and the process technology.

~ 17 ~

Figure 2.2 Power consumption trend of an LCD driver.

2.1.2 Fundamentals of the 1-bit Digital Pixel Memory [11], [12], [13]

Recently, several researches were introduced to reduce the power consumption of the low-temperature polycrystalline silicon (LTPS) TFT LCDs for small size and portable electronic equipments. These are focused on the reducing the driving frequency of LCD panel for low power consumption in the still image. Since the embedded memory circuits using LTPS TFTs in the pixel can display the still image without driving the data line from the data driver. There are two memory types to memorize the video data for display the still image in the pixel. One is using a dynamic memory. And the other is using a static memory circuit as shown in Figure 2.3, its pixel consist of pixel switch, one latch contain the digital data to express still image, and two switched to select binary data of latch. Since each pixel have either black or white, this panel was able to display 1-bit RGB(8 color) image in still mode.

Figure 2.4 shows the operation of this pixel from normal mode to still mode. At normal mode, Cont1 and Cont2 are low to cut the electrical path between pixel electrode and latch (SRAM1) and this pixel is driven as conventional pixel. In pre-still

~ 18 ~

mode, all latches in the panel ate programmed and memorized their own data. Then, in still mode, data driver and gate driver are turned off and pixel is driven by contained data in latch. Cont1, Cont2 and common electrode signals are alternated to reverse the voltage polarity applied at LC in every frame time. Therefore, driver circuits on the glass substrate and the controller IC consume almost nothing and its panel only consumes little power to drive control signals (Cont1 and Cont2) and power caused by leakage current in the latch in the still mode.

Figure 2.3 Schematic diagram of static memory embedded pixel.

Figure 2.4 Timing chart from normal mode to still mode.

2.1.3 Fundamentals of the Digital Area-modulation Pixel Memory [14], [15]

The basic concept of the area-modulation is that dividing one pixel into binary

~ 19 ~

weighted area and controlling each divided area to be black or white. With dividing the pixel into six parts, this panel was able to display 6-bit RGB(64 color) image in still mode. Figure 2.5 shows the schematic diagram of this 6-bit area-modulation pixel memory [15]. This pixel memory circuit contains one latch, a 6-bit DRAM and two TFTs as controlling transistors.

Figure 2.6 shows the time diagram of the control signals. At normal mode, POLA and POLB are low to cut the electrical path between pixel electrode and latch (SRAM1) and this pixel is driven as conventional pixel. In pre-still mode, all latch in the panel ate programmed and memorized their own data. S0~S5 turns on in turns to store the corresponding digital data into the DRAM. Then, in still mode, data driver and gate driver are turned off and pixel is driven by contained data in latch. S0~S5, POLA, POLB and common electrode signals are alternated to reverse the voltage polarity applied at LC in every frame time. Therefore, driver circuits on the glass substrate and the controller IC consume almost nothing and its panel only consumes little power in the still mode.

~ 20 ~

Figure 2.5 Schematic diagram of area-modulation pixel memory.

~ 21 ~

Figure 2.6 Time diagram of the control signals.

2.2 Circuits Implementation on Glass Substrate

2.2.1 Concept of Time-modulation [16]

This section explains basic concept of the time-modulation way for the embedded digital pixel memory. Figure 2.7 illustrates the main idea that how the time-modulation is used to build up the memory circuit. Except for the area-modulation that mentioned on 2.1.3 can produce different gray levels by dividing one pixel into several areas which is binary weighted and control each area to brighten or not, the time-modulation is another way to produce gray levels. When the high voltage is given to the pixel electrode for different time width in a constant time interval, it can be observed that different time width that the pixel electrode is given to high voltage, the different gray level that the pixel will show.

~ 22 ~

Figure 2.7 Concept of time-modulation.

Based on this concept, the gate time width that is opened for one pixel to read the data for data line is designed to be divided into binary weighted, 8:4:2:1, for 4-bit. By controlling each time interval voltage high or not, the different gray levels can be mixed. In this work, we design the pixel memory based on 2.8” QVGA TN LCD. The frame time of this LCD is 16.7ms, so the gate line time width is 16.7ms/320 = 52µs.

2.2.2 Design of 4-bit Digital Time-modulation Pixel Memory

This section presents the design of the 4-bit time-modulation pixel memory circuit which is embedded for each pixel. Figure 2.8 shows the schematic diagram of the pixel memory which contains a latch, a 4-bit DRAM and two switches, M2, M3, deciding whether to do inversion or not. This design is similar to the area-modulation design; however, this design does not have to divide the pixel into several parts which can decrease the aperture for the LCD panel. Figure 2.9 shows the control signal with time-modulation for this design. In pre-still mode, the control signals (i.e. S0~S3) turn on the switches of DRAM (i.e. M8~M11) in turns to store the corresponding digital value for each time interval into the 4-bit DRAM with M2 on and M3 off. Then, at the next cycle, the pixel goes into the still mode which means M1 is off and the pixel memory circuit has to produce the time-modulation digital signal for the Lc node

~ 23 ~

without providing data from driving circuit.

In still mode, when inversion is needed, M3 will turn off and M2 will turn on. In that case, the digital data stored in DRAM will produce an inverting digital data through one inverter (i.e. M4 and M5) at node Lc. And because control signals (S0~S3) can turn on the switches of DRAM for corresponding time width (i.e. 8:4:2:1) due to the concept of time-modulation technique, the inverting data will be produced at Lc node for corresponding time width. The latch can lock up the digital value in case the value stored in DRAM might be changed when the switch of DRAM is turned on. This design is based on AC modulation driving method. When doing the inversion, Vcom will be 5V; otherwise, it will be 0V.

With M2, M3 turns on alternatively, the pixel memory circuit can do normal operation and inversion without reading the data from driving circuit. The size of these switches is shown in Table 2.1. For a smaller area, it’s better to design the size of switch as small as possible, but in this design, the switch size of DRAM (i.e.

M8~M11) is designed larger (m=5) to make sure the switch has smaller resistance while reading or writing digital data from DRAM.

Name Type Size Fin (m)

Table 2.1: Transistor dimensions of the switches used in the pixel memory circuit.

The capacitance value of DRAM is also important in this design. When there is a

~ 24 ~

digital value change, there might be the charge redistribution between Cm and Clc.

For example, there is a digital value “1” at node Lc and the value should be changed to “0” in the next cycle because the second capacitance of DRAM stores the digital value “0” as shown in Figure 2.10. The charge on the Cm and Clc will redistribute and if the value of Cm is too small, the latch might lock up with wrong digital value and the digital value stored in DRAM might be changed. In addition, lager capacitance can diminish the effect from clock feed-through. When the control signals (S0~S3) swing, there might be some voltage coupling on capacitance of DRAM. If the capacitance value of DRAM is large enough, the voltage coupling from clock can be ignored. For the reasons above, the larger capacitance of DRAM can prevent data changed from charge redistribution and clock feed-through; however, larger capacitance also brings smaller aperture for the pixel and that will be a trade off whiling designing the value of capacitance. From simulation, it can be found that the value of DRAM capacitance must be larger than 0.5pF, or this pixel memory circuit will not work in still mode. To take Cm=0.3pF as an example, it can be observed that the digital value is wrong in still mode as shown in Figure 2.11. That is because the digital data stored in DRAM are changed due to the charge redistribution with too small Cm. So in this design, Cm is designed to be 0.6 pF to make sure there is no effect from charge redistribution and make the area of the pixel memory circuit as small as possible.

A test pattern and its simulation timing chart are shown in Figure 2.12. The test pattern is given as “l010” for 4 bits. The Lc node is shown as “0101” when M3 is on which means the inversion has been done successfully. By such simulation, this circuit is successfully verified. In the pixel memory design, the data stored by digital memory is more reliable than analog memory. And proposed time-modulation memory has a smaller area than area-modulation pixel memory.

~ 25 ~

Figure 2.8 Schematic diagram of time-modulation pixel memory.

Figure 2.9 Time diagram of the control signals.

~ 26 ~

(a)

(b)

Figure 2.10 (a)S0 turns on with the digital data “1” for the first cycle in still mode and (b) S1 turns on with the digital data “0” for the second cycle in still mode and there is a charge redistribution.

~ 27 ~

Figure 2.11 Time diagram of the simulation with Cm=0.3pF.

Figure 2.12 Time diagram of the simulation with Cm=0.6pF.

2.2.3 Discussions

According to simulated results, the power consumption of the proposed circuit in still mode is 0.24 µW per pixel. The scan driver and data driver are not included in the proposed circuit for power consumption simulation due to the limited resource, such

~ 28 ~

as chip area. However, by storing the frame data and generating its corresponding inversion data to refresh the static image without activating the data driver circuit, the power consumption of the proposed circuit can be reduced.

Also, the aperture for the LCD panel in the proposed circuit is higher because the occupied area from complicate routing for each binary-weighted pixel can be further

Also, the aperture for the LCD panel in the proposed circuit is higher because the occupied area from complicate routing for each binary-weighted pixel can be further