Simulation and Verification

According to previous sections in this chapter, we can get whole architecture of this 8-bit two-direction cyclic DAC (as shown in Figure 3.9). This two-direction cyclic DAC has four voltage sources: VDD = 10 V, VSS = 0 V, V = 5 V, and _m V_m⁺ = 7 V. That

means V_REF= V_m⁺ - V = 2 V. This two-direction cyclic DAC has been successfully _m simulated in 3-µm LTPS technology. The simulation result of this DAC, assigned a series of digital input codes 11111111 (255) at 250-kHz operation frequency. Except for the first cycle, which is called ‘reset cycle’, there are still eight cycles needed to obtain the target analog conversion data. In Figure 3.13, it shows the simulation when the sign bit bn is ‘0’. The cyclic DAC with codes 011111111 can convert the digital codes to analog data in up direction. However, in Figure 3.14, it shows the simulation when the sign bit bn is ‘1’. The cyclic DAC with codes 111111111 can convert the digital codes to analog data in down direction. The average power consumption of the

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cyclic DAC is 95.63801 µW and the average drive current per channel is 4.7657 µA.

Figure 3.13 The simulation result of this 8-bit cyclic DAC with input codes 011111111 in 3-µm LTPS technology.

Figure 3.14 The simulation result of this 8-bit cyclic DAC with input codes 111111111 in 3-µm LTPS technology.

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The linearity is an important specification of the data converter circuits except offset error and gain error. The linearity of the DAC depends on the deviation of the transfer curve from the ideal straight-line transfer curve. There are two factors to evaluate this kind of non-linearity, including differential nonlinearity (DNL) and integral nonlinearity (INL). The step size for the ideal DAC “∆” is defined as least significant bit (1 LSB) in the data converter. The definitions of DNL and INL are shown in Figure 3.15.

(a)

(b)

Figure 3.15 (a)The definition of the differential non-linearity (DNL) and (b)the definition of the integral non-linearity (INL).

From the definition of the linearity above, the DNL and INL of cyclic DAC with codes 011111111 are shown in Figure 3.16. The maximum DNL is 0.35 LSB and the maximum INL is 0.55 LSB. However, when it comes to the cyclic DAC with codes 111111111, the DNL and INL are shown in Figure 3.17. From this figure, the

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maximum DNL is 0.35 LSB and the maximum INL is 0.4 LSB.

Figure 3.16 Simulated DNL and INL with input codes 011111111.

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Figure 3.17 Simulated DNL and INL with input codes 111111111.

3.2.5 Summary

In this chapter, a speed and power efficient two-direction 8-bit cyclic DAC with 4 µs conversion time per bit has been has been successfully simulated in 3-µm LTPS technology for column drivers. The simulation results are shown above. The performance summary is shown in Table 3.1. This simple structure cyclic DAC shows

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the capability of low power driver ICs for 2.8” QVGA TN LCD.

Parameter Performance

# of bits 8

Accuracy (DNL/INL) 0.35 LSB/0.55 LSB @ 250 kHz

Speed 4 µµµµs/bit~2 µµµµs/bit

Power 95.63801 µµµµW

Technology 3-µµµµm LTPS

Table 3.3 Performance summary for cyclic DAC.

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Chapter 4

Conclusions and Future Works

4.1 Conclusions

In chapter 2, a novel 4-bit time-modulation pixel memory is designed, simulated and verified in 3-µm LTPS technology. This pixel memory circuit allows the pixel display 4-bit digital data without the LCD driver circuit. That means the pixel memory circuit can display 4-bit digital data and its inversion data when gate driver and data driver of LCD are off. This pixel memory is suitable to be further integrated with display panel to reduce the power consumption.

In chapter 3, an 8-bit two-direction cyclic DAC for on-panel data driver has been simulated. This cyclic DAC has been successfully simulated in 3-µm LTPS technology.

This cyclic DAC can be implemented with one opamp and two capacitors with clock controlling circuit. By using serial type charge-redistribution technique, the power efficiency of DAC can be achieved while using in a LCD driver circuit. Also, two-direction technique allows one cyclic DAC per one channel. The circuit configuration does not change with the input data. That makes the DAC more robust and has the smaller area.

4.2 Future Works

For the function verification, the size of the pixel memory circuit is overdesigned, so the size should be scaled down to be suitable for high resolution application. By scaling down the size, the power of the pixel memory circuit can be reduced.

And the two-direction cyclic DAC could be combined with digital gamma

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control to perform DAC with gamma correction as shown in Figure 4.1 and integrated on the glass substrate.

Figure 4.1. DAC block with gamma correction.

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REFERENCES

[1] S. Uchikoga, “Low-temperature polycrystalline silicon thin-film transistor technologies for system-on-glass displays,” in MRS Bulletin, pp. 881−886, Nov.

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SID, Dig. Tech. Papers, 2004, pp. 864−867.

[5] T. Matsuo and T. Muramatsu, “CG silicon technology and development of system on panel,” SID, Dig. Tech. Papers, 2004, pp. 856–859.

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Ishikawa, T. Ikeda, Y. Kurokawa, T. Ozaki, K. Mutaguch and S. Yamazaki, “A CPU on a glass substrate using CG-silicon TFTs,” ISSCC, 2003, vol. 9, No. 4, Feb. 2003.

[7] H. Asada, “Low-Power System-on-Glass LCD Technologies”, SID 05 Digest, pp. 1434-1437 (2005).

[8] E. Lueder, Liquid Crystal Displays Addressing Schemes and Electro-Optical Effects, John Wiley and Sons, Inc., Sep. 2004.

[9] T. Tsukada, TFT/LCD Liquid-Crystal Displays Addressed by Thin-Film Transistors, Gordon and Breach Publishers, 1996.

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[11] H. Kimura, T. Maeda, T. Tsunashima, T. Morita, H. Murata, S. Hirota, and H.

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280−283.

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Tech., 2010, pp. 1363−1366.

[14] K. Harada, H. Kimura, M. Miyatake, S. Kataoka, T. Tsunashima, T. Motai, and T. Kawamura, “A novel low-power-consumption all-digital system-on-glass display with serial interface,” SID Dig. Tech., 2009, pp. 383−386.

[15] T. Nakamura and H. Hayashi, “Display apparatus, display system and method of driving apparatus,” US patent, US 6943766 B2, Sep. 13, 2005.

[16] Y. Wakai, S. Yazawa, H. Ikejiri, Y. Uchikawa, and M. Isuda, “Liquid crystal video display device having pulse-width modulated on signal for gradation display,” US patent, US 4743096, May 10, 1988.

[17] Y.-H. Tai, Design and Operation of TFT-LCD Panels, Wu-Nan Book, Inc., Apr.

2006.

[18] P. R. Gray, P. J. Hurst, Stephen H. Lewis, and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, John Wiley & Sons, Inc., 2001.

[19] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill Companies, Inc., 2001.

[20] M.J. Bell, “An LCD column driver using a switch capacitor DAC”, IEEE J.

Solid-State Circuits, Vol. 40, No. 12, pp 2756- 2765, Dec. 2005.

[21] H.-N. Nguyen, Y.-S. Jang, J.-Y. Bae, H.-B. Le, and S.-G. Lee, “Differential Multi-bit/Conversion Cyclic DAC for TFT-LCD Column Drivers,” SID Dig.

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Tech., 2010, pp. 1458−1461.

[22] C.-W. Lu and L.-C. Huang, “A 10-bit LCD column driver with piecewise linear digital-to-analog converters,” IEEE J. Solid-State Circuits, vol. 43, no. 2, pp.

371–378, Feb. 2008.

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VITA

姓 名：陳思翰 學 歷：

市立建國高級中學 (90 年 9 月~93 年 6 月) 國立交通大學電子工程學系 (93 年 9 月~97 年 6 月) 國立交通大學電子研究所碩士班 (97 年 6 月~100 年 9 月)

研究所修習課程：

類比積體電路 吳介琮教授

數位積體電路 周世傑教授

積體電路之靜電放電防護設計特論 柯明道教授

計算機結構 劉志尉教授

類比濾波器設計 蔡嘉明教授

半導體物理與元件（一） 汪大暉教授

資料轉換積體電路 吳介琮教授

鎖相迴路設計與應用 陳巍仁教授

永久地址：台北市信義區永吉路 187 巷 17 號 10F Email：[email protected]

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PUBLICATION LIST

[1] S.-H. Chen, M.-D. Ker, and T.-M. Wang, “Digital time-modulation pixel memory circuit in LTPS technology,” in Journal of Society for Information Display, vol. 19, no. 8, pp. 539-546, Aug. 2011.

[2] S.-H. Chen, M.-D. Ker, and T.-M. Wang, “Design of digital time-modulation pixel memory circuit on glass substrate for low power application,” SID Symposium Digest 42, 1281-1284 (2011).