Thesis Organization

The fundamentals and realization of the time-modulation pixel memory are discussed in chapter 2. Then, the concept and simulation results of the two-direction cyclic DAC are discussed in chapter 3. In the last chapter, the conclusions of this thesis and the future work are stated.

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Chapter 2

Fundamentals and Realization of Time-modulation Pixel Memory

2.1 Introduction

2.1.1 Embedded Pixel Memory

The LCD frame can be separated into normal mode and still mode. The normal mode is that the frame of LCD is changing continuously. The still mode means that the frame of the LCD is static. However, conventional LCD driver produces data and sends it into pixel through data line even these data are all the same because it is a static frame. The concept of the embedded pixel memory is that the LCD is driven by only the pixel circuit when displaying a still image. This means that no charging current to the data line, which has a large load capacitance, is required. And only a small charging current to the pixel capacitor is necessary. This results in an ultra-low-power operation. Figure 2.1 shows the basic concept of pixel memory technology [3].

Figure 2.6 Basic concept of pixel memory technology.

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Figure 2.2 shows the power consumption trend of an LCD driver with various resolutions [3]. With this pixel memory technology with reflective color LCD technology, a very attractive display having an ultra-low-power characteristic as well as high image quality can be realized. Also, it has low-cost property because the frame memory is integrated in the display. The total power consumption of an LCD module is actually dominated by the lighting system such as a frontlight and a backlight. Therefore this pixel memory technology should be applied to a reflective LCD or a transflective LCD. In a reflective LCD, the pixel memory circuit can be effectively integrated under the reflective pixel electrode without any optical loss. The power consumption remains very low in most case. However, the LCD requires a frontlight system when it is used in a very low ambient light environment, which results not only in a high consumption of power but also degrades the image quality even in a normal environment. In a transflective LCD, the above problem relating to the image quality can be solved. A backlight system can be used instead of a frontlight for very low ambient light conditions. Also, it can have two different operating modes in normal ambient light conditions; an ultra low power mode which is operated by the pixel memory circuit without a backlight, and a high picture quality mode which is operated by the pixel memory or conventional driver circuit with the backlight turned on. The drawback is that the transmissive aperture area is limited to some level, according to the display specifications and the process technology.

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Figure 2.2 Power consumption trend of an LCD driver.

2.1.2 Fundamentals of the 1-bit Digital Pixel Memory [11], [12], [13]

Recently, several researches were introduced to reduce the power consumption of the low-temperature polycrystalline silicon (LTPS) TFT LCDs for small size and portable electronic equipments. These are focused on the reducing the driving frequency of LCD panel for low power consumption in the still image. Since the embedded memory circuits using LTPS TFTs in the pixel can display the still image without driving the data line from the data driver. There are two memory types to memorize the video data for display the still image in the pixel. One is using a dynamic memory. And the other is using a static memory circuit as shown in Figure 2.3, its pixel consist of pixel switch, one latch contain the digital data to express still image, and two switched to select binary data of latch. Since each pixel have either black or white, this panel was able to display 1-bit RGB(8 color) image in still mode.

Figure 2.4 shows the operation of this pixel from normal mode to still mode. At normal mode, Cont1 and Cont2 are low to cut the electrical path between pixel electrode and latch (SRAM1) and this pixel is driven as conventional pixel. In pre-still

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mode, all latches in the panel ate programmed and memorized their own data. Then, in still mode, data driver and gate driver are turned off and pixel is driven by contained data in latch. Cont1, Cont2 and common electrode signals are alternated to reverse the voltage polarity applied at LC in every frame time. Therefore, driver circuits on the glass substrate and the controller IC consume almost nothing and its panel only consumes little power to drive control signals (Cont1 and Cont2) and power caused by leakage current in the latch in the still mode.

Figure 2.3 Schematic diagram of static memory embedded pixel.

Figure 2.4 Timing chart from normal mode to still mode.

2.1.3 Fundamentals of the Digital Area-modulation Pixel Memory [14], [15]

The basic concept of the area-modulation is that dividing one pixel into binary

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weighted area and controlling each divided area to be black or white. With dividing the pixel into six parts, this panel was able to display 6-bit RGB(64 color) image in still mode. Figure 2.5 shows the schematic diagram of this 6-bit area-modulation pixel memory [15]. This pixel memory circuit contains one latch, a 6-bit DRAM and two TFTs as controlling transistors.

Figure 2.6 shows the time diagram of the control signals. At normal mode, POLA and POLB are low to cut the electrical path between pixel electrode and latch (SRAM1) and this pixel is driven as conventional pixel. In pre-still mode, all latch in the panel ate programmed and memorized their own data. S0~S5 turns on in turns to store the corresponding digital data into the DRAM. Then, in still mode, data driver and gate driver are turned off and pixel is driven by contained data in latch. S0~S5, POLA, POLB and common electrode signals are alternated to reverse the voltage polarity applied at LC in every frame time. Therefore, driver circuits on the glass substrate and the controller IC consume almost nothing and its panel only consumes little power in the still mode.

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Figure 2.5 Schematic diagram of area-modulation pixel memory.

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Figure 2.6 Time diagram of the control signals.

2.2 Circuits Implementation on Glass Substrate

2.2.1 Concept of Time-modulation [16]

This section explains basic concept of the time-modulation way for the embedded digital pixel memory. Figure 2.7 illustrates the main idea that how the time-modulation is used to build up the memory circuit. Except for the area-modulation that mentioned on 2.1.3 can produce different gray levels by dividing one pixel into several areas which is binary weighted and control each area to brighten or not, the time-modulation is another way to produce gray levels. When the high voltage is given to the pixel electrode for different time width in a constant time interval, it can be observed that different time width that the pixel electrode is given to high voltage, the different gray level that the pixel will show.

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Figure 2.7 Concept of time-modulation.

Based on this concept, the gate time width that is opened for one pixel to read the data for data line is designed to be divided into binary weighted, 8:4:2:1, for 4-bit. By controlling each time interval voltage high or not, the different gray levels can be mixed. In this work, we design the pixel memory based on 2.8” QVGA TN LCD. The frame time of this LCD is 16.7ms, so the gate line time width is 16.7ms/320 = 52µs.

2.2.2 Design of 4-bit Digital Time-modulation Pixel Memory

This section presents the design of the 4-bit time-modulation pixel memory circuit which is embedded for each pixel. Figure 2.8 shows the schematic diagram of the pixel memory which contains a latch, a 4-bit DRAM and two switches, M2, M3, deciding whether to do inversion or not. This design is similar to the area-modulation design; however, this design does not have to divide the pixel into several parts which can decrease the aperture for the LCD panel. Figure 2.9 shows the control signal with time-modulation for this design. In pre-still mode, the control signals (i.e. S0~S3) turn on the switches of DRAM (i.e. M8~M11) in turns to store the corresponding digital value for each time interval into the 4-bit DRAM with M2 on and M3 off. Then, at the next cycle, the pixel goes into the still mode which means M1 is off and the pixel memory circuit has to produce the time-modulation digital signal for the Lc node

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without providing data from driving circuit.

In still mode, when inversion is needed, M3 will turn off and M2 will turn on. In that case, the digital data stored in DRAM will produce an inverting digital data through one inverter (i.e. M4 and M5) at node Lc. And because control signals (S0~S3) can turn on the switches of DRAM for corresponding time width (i.e. 8:4:2:1) due to the concept of time-modulation technique, the inverting data will be produced at Lc node for corresponding time width. The latch can lock up the digital value in case the value stored in DRAM might be changed when the switch of DRAM is turned on. This design is based on AC modulation driving method. When doing the inversion, Vcom will be 5V; otherwise, it will be 0V.

With M2, M3 turns on alternatively, the pixel memory circuit can do normal operation and inversion without reading the data from driving circuit. The size of these switches is shown in Table 2.1. For a smaller area, it’s better to design the size of switch as small as possible, but in this design, the switch size of DRAM (i.e.

M8~M11) is designed larger (m=5) to make sure the switch has smaller resistance while reading or writing digital data from DRAM.

Name Type Size Fin (m)

Table 2.1: Transistor dimensions of the switches used in the pixel memory circuit.

The capacitance value of DRAM is also important in this design. When there is a

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digital value change, there might be the charge redistribution between Cm and Clc.

For example, there is a digital value “1” at node Lc and the value should be changed to “0” in the next cycle because the second capacitance of DRAM stores the digital value “0” as shown in Figure 2.10. The charge on the Cm and Clc will redistribute and if the value of Cm is too small, the latch might lock up with wrong digital value and the digital value stored in DRAM might be changed. In addition, lager capacitance can diminish the effect from clock feed-through. When the control signals (S0~S3) swing, there might be some voltage coupling on capacitance of DRAM. If the capacitance value of DRAM is large enough, the voltage coupling from clock can be ignored. For the reasons above, the larger capacitance of DRAM can prevent data changed from charge redistribution and clock feed-through; however, larger capacitance also brings smaller aperture for the pixel and that will be a trade off whiling designing the value of capacitance. From simulation, it can be found that the value of DRAM capacitance must be larger than 0.5pF, or this pixel memory circuit will not work in still mode. To take Cm=0.3pF as an example, it can be observed that the digital value is wrong in still mode as shown in Figure 2.11. That is because the digital data stored in DRAM are changed due to the charge redistribution with too small Cm. So in this design, Cm is designed to be 0.6 pF to make sure there is no effect from charge redistribution and make the area of the pixel memory circuit as small as possible.

A test pattern and its simulation timing chart are shown in Figure 2.12. The test pattern is given as “l010” for 4 bits. The Lc node is shown as “0101” when M3 is on which means the inversion has been done successfully. By such simulation, this circuit is successfully verified. In the pixel memory design, the data stored by digital memory is more reliable than analog memory. And proposed time-modulation memory has a smaller area than area-modulation pixel memory.

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Figure 2.8 Schematic diagram of time-modulation pixel memory.

Figure 2.9 Time diagram of the control signals.

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(a)

(b)

Figure 2.10 (a)S0 turns on with the digital data “1” for the first cycle in still mode and (b) S1 turns on with the digital data “0” for the second cycle in still mode and there is a charge redistribution.

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Figure 2.11 Time diagram of the simulation with Cm=0.3pF.

Figure 2.12 Time diagram of the simulation with Cm=0.6pF.

2.2.3 Discussions

According to simulated results, the power consumption of the proposed circuit in still mode is 0.24 µW per pixel. The scan driver and data driver are not included in the proposed circuit for power consumption simulation due to the limited resource, such

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as chip area. However, by storing the frame data and generating its corresponding inversion data to refresh the static image without activating the data driver circuit, the power consumption of the proposed circuit can be reduced.

Also, the aperture for the LCD panel in the proposed circuit is higher because the occupied area from complicate routing for each binary-weighted pixel can be further decreased. The area impact is one of the most important issues in the proposed circuit.

Since the time-modulation technique is utilized in the proposed circuit, the desired gray levels can be displayed by applying high or low logical voltage on the pixel in different time widths in a fixed time period. Therefore, the pixel is not needed to be divided in a binary weighted way as mentioned in area-modulation, which means the occupied area from complicate routing for each binary-weighted pixel can be further decreased, and the aperture for the LCD panel can be increased in the proposed circuit.

2.2.4 Summary

In this section, the concept of pixel memory circuit has been described. A 4-bit time-modulation pixel memory is designed and simulated in 3-µm LTPS technology.

A 4-bit test pattern is given and the inversion can be done with the pixel memory circuit without the LCD driving circuit.

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2.3 Experimental Results

2.3.1 Layout Considerations

The chip performance is often affected by the layout. At first, in order to reduce the sensitivity to process variation on capacitances of DRAM, the layout of these capacitances is aligned closely For the same reason, the switches layout is also put together to diminish the distortion or other errors caused by the process variation.

Figure 2.13 shows the photo of the fabricated 4-bit time-modulation digital pixel memory in a 3-µm LTPS. To prevent the parasitic capacitance of measurement equipment, about 10p, this layout adds a buffer for the output LC node.

The test chip size is 306µm x 465µm. It contains DRAM, switches, Clc and buffer. Then, the measured results will be discussed detailed in the next section.

Figure 2.13 Photo of the fabricated 4-bit time-modulation digital pixel memory in a 3-µm LTPS.

2.3.2 Measurement Setup

The measurement setup is shown in Figure 2.14. Keithley4200 Dual Pulse Generator can produce clock signal waveform, which is high to 9V and low to -5V. It can also edit the waveform when to rise or fall down so that it can produce both

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periodic and non-periodic waveform. Gn, data signal, S0~S3 are produced by it.

GPS 4303 DC Power Supply is a DC power supply which can provide separated pairs of power supply and ground where the supply voltage Vdd is 5 V and ground Vss is 0 V.

Agilent 81110A is pulse/pattern generator which can provide a pair of non-overlapping clock signals which is square waveform. It needs 81110A to generate POLA and POLB. To synchronize these two 81110A and Keithley4200, Agilent 33220A Function/arbitrary waveform generator is needed to be a reference clock. By connecting these three machines with one reference clock signal, these three machines can produce synchronized signal waveform.

SDO603A Oscilloscope shown in Figure 2.14 is a digital phosphor oscilloscope using to detect and display the signal waveforms.

The pixel memory circuit is designed on glass substrate and all of its input/output signals are bounded to the flexible printed circuit (FPC) pads and then connected to the PCB (printed circuit board) at the right hand side of Figure 2.14.

Figure 2.14 The measurement setup illustration for Pixel Memory Circuit.

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2.3.3 Measured Results of the 4-bit Time-modulation Pixel Memory Circuit

Figure 2.15 (a) shows S0 and S1 and Figure 2.15 (b) shows S2 and S3. In order to follow the concept of time-modulation, the duty cycle of S0 is twice of S1, and duty cycle of S2 is twice of S3. During Gn is on, data line produces the test pattern

“1010”. Because large parasitic capacitance of measurement equipment will affect node LC, a buffer is added to LC node for measurement. As a result, output of buffer, buffer_out represents the waveform of LC node. Figure 2.15 (c) shows Gn, data line and buffer_out. LC node can do inversion by itself as Gn is off to show the pattern

“1010”, “0101” alternatively.

(a)

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(b)

Figure 2.15 Measured result of the 4-bit time-modulation pixel memory (a) S0, S1, S2 and S3 (b) data line, Gn and buffer_out.

2.4 Summary

A 4-bit time-modulation pixel memory is designed, simulated and verified in 3-µm LTPS technology. A 4-bit test pattern is given and the inversion can be done with the pixel memory circuit without the LCD driving circuit. The power consumption of the proposed circuit in still mode is 0.24 µW per pixel. The measurement results show the pixel memory circuit can display 4-bit digital data and its inversion data on LC node alternatively when Gn is closed.

Thus, the proposed time-modulation pixel memory circuit has been successfully designed and realized in a 3-µm LTPS technology, and that is suitable to be further integrated with display panel to reduce the power consumption.

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Chapter 3

Fundamentals and Realization of Two-direction Cyclic Digital-to-Analog Converter

For the first time, the cyclic digital-to-analog converter (DAC) is simulated in 3-µm LTPS process as a part of the LCD driving circuit. The concept of the cyclic DAC used in LCD driving circuit is described in the following section. Also, the design for each block of cyclic DAC is discussed in this chapter. Finally, the performance of the cyclic DAC designed in 3-µm LTPS process can be discussed from simulation. In this work, the DAC is designed for the driver of the 2.8” QVGA TN LCD mentioned in chapter 2. That means the DAC should convert the digital codes into analog value in 52µs. To take the time for buffer into account, the DAC needs to convert one bit per 4 µs.

3.1 Introduction

3.1.1 LCD Panel Data Driving Circuit [17]

In Figure 3.1, there are several blocks which consists the data driver including shifter register, data latch, level shifter, digital-to-analog converter (DAC) and analog output buffer [16]. For the first three parts, they can process the digital data from video signal so that they are classified as digital architectures. Shifter register (S/R) and data latch manage to transit and store the RGB signals. The level shifter (L/S) is applied to translate the RGB signal to a higher level voltage.

For the other two parts, the DAC can convert the digital data into analog signal

For the other two parts, the DAC can convert the digital data into analog signal