Chapter 5 Novel Single Poly EEPROM with Metal Control Gate Structure
5.4 Conclusi on
The EEPROM cell with W damascene control gate is presented for the first time. The device fabrication is very compatible to standard CMOS process because the extra masking step can be only 2 (DNW and CG) over the CMOS process. Actually, DNW is a common layer for mixed-signal design, if it is counted as a default mask layer, the extra masking requirement for this new cell could be only one layer. Moreover, the extra process step (high K film deposition and W CMP for CG) for memory cell is done at the back-end metallization step, so there is no concerns of cross contamination nor the device impact by the extra thermal cycle from the conventional double poly process. Since the CG is formed directly on FG like the way on ETOX cell, we can layout the very competitive cell size for 2T and 1T cell with 26 F2 and 18 F2 respectively, which is much smaller than the other single poly EEPROM technologies with N-well coupling. In addition, the good single cell performance with 6.5V program/erase is demonstrated in this paper, it could allow 3.3V IO device to replace typical HV device. Chip area could be saved in addition to the masking layer saving mentioned earlier. Owing to the significant advantages like Logic compatible process, compact cell size and low voltage program/erase operation, this new cell is suitable for mid-density embedded Multi-Time-Program (MTP) application.
(a) (b)
(c)
Fig. 5.1 (a) Logic OTP using oxide rupture mechanism [2]. The capacitor shown in the figure is a poly gate with junction overlap structure, it can be breakdown during programming, (b) schematic diagram of device and array structure for a single PMOS logic OTP memory [3], (c) The top and cross section view of eFuse [4].
(Ref. U.S. Patent #’s 6,667,902 & 6,671,040)
Fig. 5.2 Schematic diagram and cross-sectional view of a logic MTP memory cell [6]
p–substrate
electron tunneling oxidegate electron
injection
n– STI or LOCOS
oxidegate n–
p+ p+
floating gate
V
tunV
injV
sfloating gate
V
tunV
injV
sIc
Fig.5.3 (a) Cross-sectional view of a single cell, (b) Top view cell layout. The ideal 2T and 1T cell size is 26F2and 18F2, respectively.
(b)
Fig.5.4 TEM picture of final cell. A proper oxidation treatment (~1 nm) before ALD and a post ALD anneal were done to ensure a good inter-gate dielectric quality. The physical thickness and the equivalent oxide thickness (EOT) of Al2O3is about 20 nm and 9 nm, respectively.
W CG
FG
Al 2 O 3
W CG
FG
Al 2 O 3
Fig.5.5 (a) Schematic diagram of memory array, (b) bias condition
BL0 BL1 BL2 BL3
Vss
BL0 BL1 BL2 BL3
A
BL0 BL1 BL2 BL3
Vss
BL0 BL1 BL2 BL3
A
BL0 BL1 BL2 BL3
Vss
BL0 BL1 BL2 BL3
A
Fig.5.6 (a) Program characteristics under different source (Vss) voltage, (b) Erasing characteristics with different control gate (CG) voltage.
(a) (b)
1.0E-06 1.0E-05 1.0E-04 1.0E-03 Tim e (sec)
1.0E-04 1.0E-03 1.0E-02 1.0E-01 Tim e (sec)
1.0E-06 1.0E-05 1.0E-04 1.0E-03 Tim e (sec)
1.0E-04 1.0E-03 1.0E-02 1.0E-01 Tim e (sec)
ReadCurrent(A)
CG=-5.0V, PW=4V CG=-4.5V, PW=4V CG=-4.0V, PW=4V
Fig. 5.7 (a) Disturb cell location in the array. A,B,C &D cells are in the same page, which will have same high VSSduring programming, (c) the cell current of C, B,D cells after
Vss
BL0 BL1 BL2 BL3
Vss
BL0 BL1 BL2 BL3
A
ReadCurrent(A) D: Row-Disturb-2 100ms/shot B: Col-Disturb 10ms/shot
BL0 BL1 BL2 BL3
Vss
BL0 BL1 BL2 BL3
A
BL0 BL1 BL2 BL3
Vss
BL0 BL1 BL2 BL3
A
ReadCurrent(A) D: Row-Disturb-2 100ms/shot B: Col-Disturb 10ms/shot C: Row-Disturb-1 10ms/shot
(a)
(b)
Fig.5.8 (a) Endurance Cycling characteristics with channel-hot-electron (CHE)
programming and FN erasing. Only 10% current drop is observed after 100K cycling, (b) Data retention characteristics under various pre-cycling stress at 150C baking.
000E+0
1.0E+00 1.0E+01 1.0E+02 1.0E+03 1.0E+04 1.0E+05
Cycling Times
R e a d C u rr e n t (A )
ERS (SG=0V, WL=-4V, BL=0V, VSS=0V, PW=5V)
PGM (SG=2.5V, WL=6.5V, BL=0V, VSS=6.2V, PW=0V)
0.00%
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05
Baking Time @150C ( hr )
Ir0 10K cycle
10 yrs
50%
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05
Baking Time @150C ( hr )
Ir0 10K cycle
10 yrs
50%
reference
Reference
[1] J. Harding, “ Smaller, fater, Cheaper, Better: The Relentless Pressure on Consumer Electronics,”LogicNVM Symp,2007
[2] US patent 6,667,902 & 6,671,040
[3] C.Kothandaraman,S.K.Iyerand S.S.Iyer,“Electrically Programmable Fuse(eFUSE) Using Electromigration in Silicides,”IEEE Electron Device Lett., vol. 23, no. 9, Sep.
2002, pp. 523-525
[4] L. Chang, C. Kuo, Chenming. Hu, A. Kalnitsky, A. Bergemont and P. Francis,
“Non-volatilememory devicewith true CMOS compatibility,”Electronics Letter, vol.35, no.17, 19thAug. 1999, pp. 1443-1444
[5] A. Pesavento, T. Gilliland, C. lindhorst, S. Srinivas, F. Bernard, S. Salazar, C. Diorio, S.
King, C. Bockorick, B. Wang, Y. Ma, C.H. Wang, T. Humes, J. Caywood, “Embedded nonvolatile Memory in Logic CMOS,”in IEEE NVSMW, 2004, pp. 49-50.
[6] K. Ohsaki, N. Asamoto, A. Takagaki, “A single poly EEPROM Cell Structure for Use in Standard CMOS Processes,”IEEE J. Solid-State Circuits, vol. 29, no. 3, Mar. 1994, pp.
311-316.
[7] Y.L. Tu, H.L. Lin, L.L. Chao, Danny Wu, C.S. Tsai, C. Wang, C.F. Huang, C.H. Lin, Jack Sun, “Characterization and Comparison of High-k Metal-Insulator-Metal (MiM) Capacitors in 0.13 m Cu BEOL for Mixed-Mode and RF Applications,”in Symp. VLSI Technol. Dig., 2003, pp. 79-80.
[8] B. Govoreanu, P. Blomme, M. Rosemeulen, J. Van Houdt, K. DeMeyer, “VARIOT: A Novel Multilayer Tunnel Barrier Concept for Low-Voltage Nonvolatile Memory Devices,”IEEE Electron Device lett., vol. 24, no. 2, Feb. 2003, pp. 99-101.
Process”IEEE Trans. Electron Devices, vol. 48, no.8, August 2001, pp. 1751–1755.
[10] Y.H. Song, J.I. Han, J.W. Kim, J.H. Park, S.Y. Kim, D.W. kwon, Y.M. Park, J.S. Lee, W.K. Lee, D.Y. Lee, J.W. Kim, M.S. Kang, J. Kim, and K.D. Sub, “A High Density and Low-cost Self-aligned Shallow Trench Isolation NOR Flash Technology with 0.14 m2 cell size”inIEDM Tech. Dig., 2001. pp. 2.4.1-2.4.4.
[11] A. Chimenton, P. Pellati, P. Olivo, “Overerase Phenomena: An Insight Into Flash Memory Reliability,”in Proceedings of the IEEE, vol. 91, no. 4, April 2003, pp. 617-626.
[12] T. Sugizaki, M. Kobayashi, M. Ishidao, H. Minakata, M. Yamaguchi, Y. Tamura, Y.
Sugiyama, T. Nakahishi, H. Tanaka, “Novel Multi-bit SONOS Type Flash Memory Using a High-K Charge Trapping Layer”in Symp. VLSI Technol. Dig., 2004, pp. 27-28.
[13] J.W. Liou, C.J. Huang, H.H. Chen, G. Hong, “Characterization of Process-Induced Mobile Ions on the Data Retention in Flash Memory”IEEE Trans. Electron Devices, vol.
50, no.4, April 2003, pp. 995–1000.
[14] M. Janai, B. Eitan, A. Shappir, E. Lusky, I. Bloom, G. Cohen, “Data retention Reliability Model of NROM Nonvolatile Memory Products”IEEE Trans. On Device and Materials Reliability, vol. 4, no.3, September 2004, pp. 404–415.
Chapter 6
Conclusions and Further Recommendations
6.1 Conclusions
In this thesis, a new methodology for program vs. disturb window characterization on split gate flash cell is presented in Chapter 3. The window can be graphically illustrated in VWL(word-line)-VSS(source) domain under a given program current. This method can help us to understand quantitatively how the window shifts vs bias conditions, and lead us to find the optimal program condition. The condition obtained by this method can have the largest operation window. This methodology was successfully implemented in 0.18um triple self-aligned (SA3) split-gate cell development.
Then, in the chapter 4, a new triple self-aligned (SA3) split-gate flash cell with a T-shaped source coupling approach is described. This novel structure can significantly enhance coupling capacitance between the source and floating gate without increasing cell size. The enhancement can be simply modulated by an oxide-etching step. This new structure can be applied to program voltage reduction and cell size scaling. For program voltage reduction, the maximum program voltage of the new cell can be reduced from 7.4 to 6.4 V, which is characterized by the newly developed characterization methodology presented in Chapter 3. For cell size scaling, comparable wafer sort yield was demonstrated using the new cell with a shorter floating length and a shallower source junction. To understand the relationship
discussion on the program and erase mechanisms for our split–gate flash cell is described in Chapter 2.
In this chapter 5, a novel single poly EEPROM using metal control gate is presented in this paper. The control gate is tungsten (W) line made by a damascene process, and inter-gate dielectric is Al2O3grown by Atomic Layer Deposition (ALD).
The program and erase mechanism is the same as the one for traditional stacked-gate cell, which uses the channel hot electron injection for programming and Fowler-Nordheim (F-N) tunneling for channel erasing. With the high dielectric constant (K) property of Al2O3, we can perform the program and erase function with a voltage less than 6.5 V, which could be handled by 3.3 V devices instead of traditional high voltage devices. In the process compatibility aspect, this new cell needs only two extra masking steps over the standard CMOS process, and the high-K material is deposited in the back-end metallization steps without the concern for cross-contamination nor the device impact from the extra thermal cycle. Therefore, this new technology is suitable for embedded application. In this paper, the good cell performance is demonstrated; such as, fast programming/erasing, good endurance and data retention.
6.2 Further Recommendations
There are some interesting topics for further study. For window characterization, the choosing of program and disturb spec needs further investigation because the operation window would have strong dependence on how we define the spec. For split gate technology evolution, the direction to scale down the cell is to continuously improve the CG/FG coupling. The cell described in the reference [1] is a very good
candidate for the next generation of split –gate Flash. It uses an additional control gate on top of floating to fully utilize the FG area for coupling. By doing so, the high voltage in source voltage can be moved to additional CG, so the source junction can be shallower and the cell can be much smaller. Also, the addition of control gate can provide more flexibility to control the program disturb mechanism, so the operation window can be enlarged. In addition, the erase gate can be moved to the poly on top of source junction, so the select transistor can use low voltage oxide to increase driving capability. For the single poly EEPROM with metal control gate, the future work we would focus on the trapping mechanism study and the experiment on new high K material for the metal control gate cell.
Fig.6.1. Next generation of split-gate Flash cell. One extra CG gate is added to enhance the FG/VSScoupling [1].
Reference
[1] Y.S. Cho, M.J. Chen, “A novel Highly Reliable Flash Memory –characteristics, Reliability Evaluation, and application,” National Chiao-Tung University PHD Thesis, 2004.
學經歷
姓名: 宋弘政 性別: 男
出生: 民國 54 年 10 月 25 日 籍貫: 高雄市
住址: 高雄市楠梓區宏毅二路南五巷四十一號 學歷: 國立交通大學電物系 [72 年 9 月- 76 年 6 月]
國立交通大學光電研究所碩士班 [76 年 9 月- 78 年 7 月]
國立交通大學電子研究所博士班 [88 年 8 月- 97 年 6 月]
經歷: 臺灣積體電路記憶體 工程師~專案經理 [80 年 7 月- 94 年 8 月]
臺灣積體電路北美分公司 專案經理 [94 年 12 月至今]
博士論文題目:
分離式閘極非揮發性記憶體技術及新穎多晶矽電子抹除式唯讀記憶 體之研究
Study on Split-Gate Non-Volatile Memory Technology and A Novel
Single Poly EEPROM Memory Cell
Publication List
1. International Journal:
[1] Hung-Cheng Sung, Tan Fu Lei, Te-Hsun Hsu, Chen-Ming Huang, Ya-Chen Kao, Yung-Tao Lin, C.S.
Wang;“New Triple Self-aligned(SA3) Split-gate Flash Cell with T-shaped Source Coupling,”JJAP, Vol.
44, no. 10, 2005, pp. 7377-7383
[2] Wen-Ting Chu, Hao-Hsiung Lin, Chia-Ta Hsieh, Hung-Cheng Sung, Yu-Hsiung Wang, Yung-Tao Lin, Wang, C.S,; “Shrinkable triple self-aligned field-enhanced split-gate flash memory,”IEEE Trans.
Electron Devices, Vol. 51, Issue 10, Oct. 2004 pp. 1667 - 1671
2. International Letter:
[1] Hung-Cheng Sung, Tan Fu Lei, Te-Hsun Hsu, Ya-Chen Kao, Yung-Tao Lin,C.S.Wang “Novel program versus disturb window characterization for split-gate flash cell,”IEEE Electron Device Lett., Vol. 26, Issue 3, March 2005 pp. 194 - 196
[2] Hung-Cheng Sung, Tan Fu Lei, Te-Hsun Hsu, S.W. Wang, Ya-Chen Kao, Yung-Tao Lin, Wang, C.S,
“Novel Single Poly EEPROM with Damascene Control Gate Structure,”IEEE Electron Device Lett., vol. 26, no.10, 2005, pp. 770-772
[3] Wen-Ting Chu, Hao-Hsiung Lin, Yeur-Luen Tu, Yu-Hsiung Wang, Chia-Ta Hsieh, Hung-Cheng Sung, Yung-Tao Lin, Chia-Shiung Tsai, C.S. Wang “Using an ammonia treatment to improve the floating-gate spacing in split-gate flash memory,”IEEE Electron Device Letters, Vol. 25, Issue 9, Sept.
2004 pp. 616 - 618
[4] Wen-Ting Chu, Hao-Hsiung Lin, Yu-Hsiung Wang, Chia-Ta Hsieh, Hung-Cheng Sung, Yung-Tao Lin,C.S.Wang,“High SCR design forone-transistor split-gate full-featured EEPROM,”IEEE Electron Devices Lett., Vol. 25, Issue 7, July 2004 pp.498 - 500
[5] Kuo-Ching Huang, Yean-Kuen Fang, Dun-Nian Yang, Chii-Wen Chen, Hung-Cheng Sung, Di-Son Kuo, C.S.Wang, Mong-Song Liang ,“The impacts ofcontrolgate voltage on the cycling endurance of splitgate flash memory,”IEEE Electron Devices lett. Vol. 21, Issue 7, July 2000 pp. 359 - 361
[6] Kuo-Ching Huang, Yean-Kuen Fang, Dun-Nian Yaung, Chii-Wen Chen, Hung-Cheng Sung;
Di-Son Kuo, C.S. Wang, Mong-Song Liang,“Effectofsubstrate bias on the performance and reliability