Chapter 4 New Triple Self-aligned (SA3) Split-Gate Flash Cell with T-Shaped
4.4.1 Programming
From the discussion in Chap.2, we derive the EX and EOX as shown in the following equations. (eqs.7&8 in Chap.2)
G
From above equations, we can find that the the SCR ( ) has a linear effect on theS a large longitudinal electric field (Ex) and vertical oxide electric field (EOX).
On the basis of the lucky-electron model (LEM), the injection current equation is shown below. The linear effect of SCR on EX and EOXwill turn into exponential effect on injection current.
The simulation result shown in Fig.4.5, it indicates that SCR is the most important factor influencing electron injection probability; 10% increase on SCR can improve electron injection probability by 300%.
As shown in eqs (9)-(11) in Chap2, using a cylindrical approximation, the electric
where a is the radius of curvature of the smaller cylinder, and
G SG S SS
Simply stated, a higher (SCR) can result in a higher voltage drop across theS inter-poly oxide. Based on the Fowler-Nordheim tunneling equation, the (SCR)S will also have exponential effect on the injection efficiency.
From the above discussion, we can understand the improvement on (SCR) willS have significant advantage on the programming and erasing performance for split-gate Flash. The improvement is very important for lower voltage operation and cell size scaling.
4.5 Application to Voltage Reduction
As was revealed in section 4.2, we can modulate the SCR by varying the etching time for FG oxide spacer pull-back. The result in Fig. 4.6 shows that more pull-back etching can induce a higher source coupling. Next, by measuring the cells at different etching times, we can obtain the relationship between SCR and program/erase performance [16]-[19]. As shown in Fig. 4.7(a) and (b), a higher SCR can result in a more efficient program/erase performance as we predicted in the previous section.
The criteria for evaluating the program/erase performance is described in the following: (a) The programmability is characterized as Ir0/Ir1@Vs=6V, 10us with program current=3uA, where Ir0 and Ir1 is programmed and erased current, respectively. (b) The erasing performance is characterized by Verase, which is the voltage to reach 50% Ir1 after 10ms erasing.
Since programming and erasing can be improved by a higher SCR, we can perform the functions with a lower voltage, which is important for low-Vcc operation.
To determine the program condition for the T-shaped SA3 cell, we used the new
program-disturb window characterization methodology described in Chap.3 [20].
Comparing the program-disturb windows between conventional SA3 and new T-shaped coupling cell, shown in Figs. 4.8(a) and (b), we can find that the Vss voltage for programming can be reduced from 7.4 to 6.4 V in new cell. It is important to let the voltage lower than 6.5V because it can be handled by the 3.3V IO device, which is a requirred device in many application. The junction of IO devices typically can sustain up to 7V, so it can handle the 6.5V operation with proper cascade design.
Using IO device for high voltage circuit design has several benefits: (1) Masking steps saving. About 4 masking step for well and LDD implant for traditional HV devices can be eliminated, (2) Area saving. The 3.3V design rule can be much tighter than the rule for >10V. Despite the low Vs voltage advantage, there is a minor side effect caused by the reverse-tunneling-disturbance (RT). The boundary drops from 9 V to 8 V in the new cell. The RT disturbance is caused by the undesired electron tunneling from WL to FG when FG is coupled to a high voltage during programming.
The RT disturbance tends to occur under the conditions of a high Vss bias and a high SCR. In general, the degradation can be improved by FG profile optimization.
For the erase performance improvement by the new SA3 cell, we found that the Verase can be reduced by 0.5V as shown in Fig. 4.7(b). Basically, the erase voltage reduction is not as critical as the reduction in program voltage because of the two following reasons. First, the erase operation consumes much less power than the program operation; thus, the high-voltage design for erase is much easier. Second, the erase voltage can be greatly reduced by splitting the voltage into two polarities [8].
4.6 Application to Cell Size Reduction
For the traditional SA3 cell, a deep Vss junction is necessary to induce a sufficient coupling capacitance between Vss and FG. Thus, a large FG length is required to accommodate the large source junction and to prevent the punchthrough triggered by the high Vss voltage. With the help of T-shaped Vss coupling, the same SCR can be achieved with a shallower Vss junction. As a result, we can reduce FG length while keeping the same cell performance. As we can observe in Fig. 4.9, the yield of a 16 Mbit test vehicle with a shallower Vss junction and a T-shaped coupling structure remains stable when FG length is reduced, whereas the yield of the
Note that the nominal FG length is 0.18 µm. In addition, the data retention performance of the new cell remains as good as that in the case using the traditional approach. The data retention failure rate after 72 hrs baking at 250°C is less than 1%
out of 3000 good die.
4.7 Summary
A triple self-aligned (SA3) split-gate flash cell with a T-shaped source coupling approach is described in this paper. This novel structure can significantly enhance the coupling capacitance between the source and the floating gate (SCR) with no complex process steps. This new structure can be applied to program voltage reduction and cell size scaling. For the program voltage reduction, the maximum program voltage of the new cell can be reduced from 7.4 to 6.4 V, which is characterized by a newly developed methodology for program-disturb window characterization. For erasing, the voltage reduction is about 0.5 V. Regarding cell size scaling, comparable sort-1 and sort-2 yields are demonstrated using the new cell with a smaller floating gate length and a shallower source junction. In summary, the new T-shaped source coupling approach is a novel, well controlled, and inexpensive approach, which does not need additional masking step. Therefore, it is a very attractive solution for the next-generation SA3 split-gate cell.
Fig.4.1 The cell cross-sectional view of tradition non-self-aligned cell vs. triple self-aligned(SA3) cell.
Larger cell size but simpler process
Smaller cell size but more complex process
Source Drain
Drain
WL1 WL2
Source Drain
Drain
WL1 WL2
NSA(non self-aligned) SA3(triple self-aligned)
Smaller cell size but more complex process
Source Drain
Drain
WL1 WL2
Source Drain
Drain
WL1 WL2
Source Drain
Drain
WL1 WL2
Source Drain
Drain
WL1 WL2
NSA(non self-aligned) SA3(triple self-aligned)
Fig.4.2. Process flow of the T-shaped Triple Self-aligned (SA3) split-gate flash cell.
I. 1stself-align (FG to STI):
1. Coupling oxide oxide growth 2. FG poly deposition
3. SiN deposition 4. Standard STI process
SiN FG
II. 2ndself-align (SL to FG):
1. FG photo and etch 2. Poly slope etch
3. FG oxide spacer formation -- oxide deposition/etching 4. Poly (FG) etch
5*. Oxide spacer pull-back etching 6*. Source liner oxide deposition 7*. Source poly spacer formation
-- poly deposition/etch 8. Source implantation 9. Vss poly deposition and
etching back
Steps 5-7 are the new process other than conventional SA3 process10).
SiN
FG FG oxide spacer
III. 3rdself-align (WL to FG):
1. SiN removal 2. FG poly etching 3. Inter-poly(tunnel oxide)
deposition
4.WL poly spacer deposition/etch
Source liner oxide
1. Coupling oxide oxide growth 2. FG poly deposition
3. SiN deposition 4. Standard STI process
SiN FG
II. 2ndself-align (SL to FG):
1. FG photo and etch 2. Poly slope etch
3. FG oxide spacer formation -- oxide deposition/etching 4. Poly (FG) etch
5*. Oxide spacer pull-back etching 6*. Source liner oxide deposition 7*. Source poly spacer formation
-- poly deposition/etch 8. Source implantation 9. Vss poly deposition and
etching back
Steps 5-7 are the new process other than conventional SA3 process10).
III. 3rdself-align (WL to FG):
1. SiN removal 2. FG poly etching 3. Inter-poly(tunnel oxide)
deposition
4.WL poly spacer deposition/etch
Source liner oxide
(b)
Fig. 4.3 (a) Traditional SA3 vs. T-shaped Vss coupling SA3 cell. (b) TEM picture of the new
Conventional SA3 T-shaped Vss coupling SA3
Source Drain
Drain
WL WL
Source Drain
Drain
WL WL
(a)
Fig. 4.4 Cell array and bias voltage for program, erase, read-out and three disturb conditions, which are: A. Column punchthrough disturb(PTC), B. Row punchthrough disturb(PTR), C.
Reverse tunneling disturb(RT). Note that the cells outside the selected page are immune from disturb stress.
Erase and Read bias
BLn-1 BLn* BLn+1 BLn+2 WLm0(0V)
Vss(7.4V) WLm1(1.8V)
2.5V Vdp 2.5V 2.5V
B A B B
C S C C
BLn-1 BLn* BLn+1 BLn+2 WLm0(0V)
Vss(7.4V) WLm1(1.8V)
2.5V Vdp 2.5V 2.5V
B A B B
C S C C
Note: Vdp is the selected bit-line voltage at Idp=5 uA; the voltage is about 0.5 V.
Fig.4.5 (a) Pinch-off point of FG and SG is A and B, respectively. Electron injection point is C, where is located in floating gate edge on the poly space. (b) Electric field and electron injection probability distribution (c) Plot of factors effect on the electron injection
0
Vbl=0 Vbl=0.6 Vbl=1.2 SCR=60% SCR=70% SCR=80% Vss=6.5 Vss=7.5 Vss=8.5 Vsb=0 Vsb=-1 Vsb=-2
Peak P_electron-injection
Vbl=0 Vbl=0.6 Vbl=1.2 SCR=60% SCR=70% SCR=80% Vss=6.5 Vss=7.5 Vss=8.5 Vsb=0 Vsb=-1 Vsb=-2
Peak P_electron-injection Peak Ex
Peak Ey
LG
Floating gate
Fig.4.6 Source coupling ratio (SCR) vs. FG oxide spacer pull-back etching.
FG oxide spacer Pull-back (A)
S C R (% )
FG oxide spacer Pull-back (A)
S C R (% )
Fig.4.7 (a) Program improvement vs FG oxide spacer pull-back. The program performance is characterizaed by Ir0/Ir1@Vs=6V, 10us, program current=3uA, where Ir0 and Ir1 is
programmed and erased current, respectively. (b) Erasing improvement vs. FG oxide spacer etching. The erasing performance is characterized by Verase, which is the voltage to reach
PGM improvement
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00
0 200 400 600 800
FG oxide spacer Pull-back (A)
Ir 0 /I r1 @ V s = 6 V
ERS improvement
8.3 8.4 8.5 8.6 8.7 8.8 8.9
0 200 400 600 800
FG oxide spacer Pull-back (A)
V e ra s e (V )
(a)
(b)
Fig.4.8 (a) Program vs. disturb window of traditional SA3 cell. The source voltage for
programming is 7.4V, (b) Program vs. disturb window of T-shape Vss coupling SA3 cell. Vss voltage can be reduced to 6.4V in new cell.
0.9
Fig. 4.9 FG length reduction vs. yield. The yield of new SA3 cell remains stable when FG length is reduced, whereas the yield of old SA3 cell drops drastically with the shorter FG length. Note that the nominal FG length is around 180nm.
Project to even lower yield on–400A
FG length (A)
0 0.2 0.4 0.6 0.8 1 1.2 1.4
Norminal -200A -400A
Normalizedyield(%)
T-Shaped Vss Old SA3
Project to even lower yield on–400A
FG length (A)
0 0.2 0.4 0.6 0.8 1 1.2 1.4
Norminal -200A -400A
Normalizedyield(%)
T-Shaped Vss Old SA3
Reference
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Chap.5
Novel Single Poly EEPROM with Metal Control Gate Structure
5.1 Introduction
The consumer electronics is the most important market sector in IC industry, the household spending on consumer electronics doubles since 1994 [1]. The characteristics of consumer electronics are the short lifetime cycle and fast cost erosion. To be successful in this business, the time to market and the total cost is the main key factor. Recently, the Logic NVM (Non-Volatile Memory) technology has gained high attention because it can offer design flexibility to make chip meet the spec without going through design revision and can use pure logic process without extra masking for the non-volatile memory.
Currently, there are two categories in Logic NVM. One is Logic OTP and another is Logic MTP. The Logic OTP is the One Time Programming memory. There are several ways to perform the one time programming function using pure logic process. For example: (1) oxide rupture mechanism to cause gate to junction short[2], (2) electro-migration method to change the poly resistance [3], and (3) use single floating PMOS structure, which relies on the weak coupling between floating gate and junction to get electrons injected to the floating gate [4]. Since OTP memory can only be programmed once, the application is limited to code storage, calibration/trimming, feature selection, memory repair and ROM replacement. The summary of Logic OTP technology is shown in Fig. 5.1. The 2nd type of LogicNVM is the logic MTP. It can perform Multi-Time Programming up to 10,000 times like the typical Flash or EEPROM . It uses N-well as the coupling gate instead of traditional double poly, so it can be built on pure logic process [5,6]. As shown in Fig. 5.2, the cell size is very big because it needs to use a N-well region as the coupling gate. Due to the big cell size, the biggest density
usually can only be several K bits. As a result, the application is limited in the precision analog trimming code, digital right management (DRM), RFID and data storage.
In this chapter, a novel single poly EEPROM with small cell size and fewer extra masking steps is presented. The uniqueness of this cell is that the control gate structure is a tungsten line formed by damascene process and the inter-gate dielectric is the high-K material grown by Atomic Layer Deposition (ALD) [7]. Because of a stronger coupling between Control gate (CG) and Floating gate (FG) by using the high K material like Al2O3, the program and erase voltage can be lowered from ~10 V to 6.5 V. Therefore, the program/erase circuitry could be handled by 3.3 V IO devices instead of conventional high voltage devices [8]. Furthermore, the cell size can be very compact because the control gate is on top of the floating gate but not from the huge well diffusion. For CMOS process compatibility, this new approach can be built on pure logic process but adding two extra masking steps for Deep Nwell (DNW) and Control gate (CG). In addition, the high-K material is deposited during back-end metallization steps, so there is no high-K material contamination concerns because the material is deposited during back-end metallization steps. Therefore, the new cell presented in this paper is very suitable for mid-density embedded Multi-Time-Program (MTP) applications.
5.2 Device Fabrication
The cross-sectional and top view of a single cell is shown in Fig. 5.3 (a)&(b). The ideal 2T and 1T cell size for this new cell is 26 and 18 F2, respectively [10]. For feasibility study, a relaxed 2T cell, 1.5 m2, is used in this experiment. The 2T structure is chosen because it is immune from over-erase concern [11]. The channel width is 0.32 m, and the channel length for floating gate and select gate is 0.4 and 0.18 m, respectively. The floating gate overlap
resistance. The device fabrication begins with a deep N-well photo and implantation, then uses the standard 0.18 m CMOS process from Shallow-Trench-Isolation (STI) to contact plug formation. The gate oxide (~7 nm) and gate poly (150 ~ 200nm) for periphery devices are acted as the tunneling oxide and floating poly for this EEPROM device. After contact plug formation, the control gate is formed by a tungsten (W) damascene process, which includes Control gate photo & etching, Al2O3 deposition, barrier metal (TiN) deposition, W fill and CMP. A proper oxidation treatment (~1 nm) before ALD and a post ALD anneal were done to ensure a good inter-gate dielectric quality. The physical thickness and the equivalent oxide thickness (EOT) of Al2O3 is about 20 nm and 9 nm, respectively. After the control gate damascene process, the typical back-end metal process is followed. The TEM picture of final cell is shown in Fig. 5.4. Note that the high-K film, Al2O3,is deposited in the back-end metallization steps but not in the front-end process shown in the previous works [8], [12], so there is no cross-contamination issue caused by new material nor the device impact induced by the extra thermal cycle from conventional double poly process. To prevent data retention problems induced by salicidation, the cell area is blocked with protective oxide during the salicidation process [13].
5.3 Result and Discussion
Programming & Erasing Performance
The program and erase mechanism is the similar to the one for traditional stacked-gate cell, which uses channel-hot-electron injection for programming and Fowler-Nordheim (F-N) tunneling for channel erasing. The array schematic and bias condition is shown in Fig. 5.5 (a)
& (b). As shown in Fig. 5.6 (a) & (b), the programming and erasing can be accomplished in 500 s and 100 ms, respectively. The maximum voltage is 6.5 V and 5 V for programming and erasing, respectively. The voltage is less than the typical stacked-gate flash memory
because of the stronger FG-CG coupling contributed by the high-K film, Al2O3, whose dielectric constant is 9, which is 2.3 times and 28% higher than oxide and nitride, respectively.
The coupling ratio is around 70%, which is calculated from the cell layout and the equivalent oxide thickness. We use 0.18µm logic well and junction for this memory cell, so we can save the masking step for memory fabrication. However, since the drain and well is engineered for logic device, the programming performance is not as good as typical commodity flash cell.
With maximum 6.5V operation, the voltage could be handled by 3.3V IO device, which typically has breakdown voltage higher than ~7V. Using 3.3V IO device for the programming/erasing circuit can save the extra masking & process for high voltage device fabrication, also the chip area can be greatly reduced because of the tighter design rule for 3.3V devices.
Disturb Characteristics
No disturb behavior is found on the non-selected cells in bit-line and word-line directions during programming. The data is shown in the Fig. 5.7 (b). Similar to the split-gate Flash memory array reported in Chap.3, there are three types of disturb in the same page, which will have the high Vss disturb during program. The disturbed bits are labeled as B,C,D in the Fig.
No disturb behavior is found on the non-selected cells in bit-line and word-line directions during programming. The data is shown in the Fig. 5.7 (b). Similar to the split-gate Flash memory array reported in Chap.3, there are three types of disturb in the same page, which will have the high Vss disturb during program. The disturbed bits are labeled as B,C,D in the Fig.