Summary

The side-wall spacer Poly-Si/SiGe nanowires were successfully fabricated by the side-wall spacer technique on Si wafer. The SEM image is used to know the dimension of nanowire. In order to normalize the drive current of nanowires, we consider the nanowire as a resistor. The conductance is chosen for comparison between the nanowires. The higher drive achieved of SiGe nanowire instead of Poly-Si nanowire, and the higher current obtained for the SiGe nanowire with higher Ge concentration. The reason for less improvement of conductance after ion implantation may be that the implant dominates the current and decreases the influence of Ge element. However, the drive current of Si0.89Ge0.11 nanowire still has

50% improvement than Poly-Si nanowire after ion implantation. The test structure of serial contact pad with 5 um length micro wire was used to compare the contact resistance of SiGe and Poly-Si. The higher contact resistance and lower conductance are the properties of SiGe nanowire.

Chapter 3

Electrical Properties of SiGe Film with Various Oxidation Conditions

3.1 .1 An Overview of the Applications of High Mobility SiGe Alloy

As the channel length of metal-oxide-semiconductor field effect transistors (MOSFETs) is deeply scaled down to sub-100 nm, enhancement of the carrier mobility in the channel is desired for improving the performance of complementary MOS (CMOS) circuits²⁸. For this purpose, Ge is a promising channel material for MOSFETs because of high mobility of both the electrons and holes. Enhanced device performances have been demonstrated by using a strained Si channel grown upon a relaxed (SiGe) substrate²⁹, where the electron mobility is increased due to the reduced intervalley phonon scattering³⁰. However, at lower Ge content, only moderate increase in hole mobility could be achieved in strained Si compared to bulk Si³¹. On the other hand, with high Ge content (83%), SiGe channel high hole mobility enhancement in PMOSFETs can be realized³². To achieve the highest enhancement, pure Ge channel is attractive.

3.1.2 Ge Condensation Process in SiGe Film

Conventionally, relaxed Si1-xGex film with high Ge content has been obtained by growing compositionally graded Si1-xGex much thicker than the critical thickness in order to introduce dislocations to relax strain in Si1-xGex layer³³. Although the density of dislocations in the relaxed SiGe layer by this approach has been greatly reduced over time, the control of dislocations is still challenging and requires optimization for dislocation suppression. In addition, the thick Si1-xGex films need for strain relaxation through dislocations (on the order of a few microns, with a typical grading rate of

10% germanium increment per micron) poses a serious bottleneck for throughput³⁴. An approach to achieve high Ge content in relaxed Si1-xGex layer has been reported that takes the advantage of the selective removal of Si atoms from SiGe film by Si1-xGex thermal oxidation³⁵. When supply of Si atoms diffused from the SiGe to the oxidation interface meets the consumption of Si atoms during oxidation, only Si atoms would be oxidized because Si oxidation is preferred to Ge oxidation³⁶, which leads to an increased Ge content in the Si1-xGex layer as the film is thinned down.

3.1.3 Mechanism of SiGe Oxidation

The oxidation of SiGe thin films has been demonstrated at several laboratories^37-40. In these cases, enough Ge on the oxidation of Si had to be snow-plowed in order for oxidation enhancement to be observed. They proposed that breaking of the weaker Si-Ge bound as compared with Si-Si explain the rate enhancement. This may only be the last event, not necessarily controlling. For example, represents a steady-state situation in which Si-Si bonds must still be broken below the Ge-enriched layer to supply the needed Si flux to the interface to maintain the high oxidation rates. Attention should be focused on the growth interface and interactions there since the Ge effect is found only in the initial and linear regime of oxidation. In all cases reported so far, it is shown that Si is preferentially oxidized and only one Ge-rich layer is formed at the oxide/substrate interface for SiGe with a Ge concentration below 50%. On the other hand, there are two oxide layers formed after oxidation for SiGe with Ge concentration above 50%.

According to the theory binary alloy oxidation^41-42, the oxide growth will depend on the alloy composition. For the case of the SiGe alloy, Si is more reactive than Ge.

The reason is the large difference between the heat of formation of SiO2 (-204 kcal/mol) and GeO2 (-119 kcal/mol). For SiGe with low Ge concentration (< 50%),

only silicon is oxidized initially. Ge is completed rejected from the oxide and piles up at the oxide/substrate interface. On the other hand, oxygen concentration at the oxidation front decreases with the oxide thickness increases. Then, the decreasing oxygen concentration at the oxidation front counteracts the effect of increasing Ge concentration in the Ge-rich SiGe layer so that Ge is not oxidized during the entire oxidation process.

For SiGe with high Ge concentration (> 50%), Si and Ge will be oxidized during the oxidation process. In alloys containing 50 and 75 at.% Ge, the rate of diffusion of Si to the oxide/alloy interface is sufficiently slow with respect to the rate of oxidation that it rapidly becomes impossible to grow pure SiO2 . Thus, the initial oxide formed is a mixed (Si, Ge)O2 oxide. Eventually, the activity of oxygen at the interface decreases because of the thickness of the oxide, resulting in a slow down of the oxidation rate. This makes it possible for Si to diffuse to the interface as fast as is required to form pure SiO2.

Eventually, oxide thickness will reach a critical value, which is proportional to the Ge concentration in SiGe film, such that the oxygen and Ge concentration at the oxide/SiGe interface are too low for Ge to be oxidized. At this stage a steady-state condition has been reached at which selective oxidation of Si succeeds and Ge piles up at the oxide/SiGe interface again. So that it is shown that Ge at the oxide/SiGe is in elemental form, while Ge at the oxide surface is in an intermediate oxidized form.

3.1.3 Oxidation Behavior of SiGe

The oxidation behavior of SiGe films has been studied to a great extent^43-45. Ge is completed rejected from the oxide and piles up at the oxide/substrate interface after oxidation process. A Ge-on-insulator (GOI) was fabricated by Ge condensation

technique in previous literature⁴⁶. In addition, as the thickness of SiGe layer is smaller than diffusion length of the Ge atoms, the SiGe layer will become uniform, as show in Figure 3.1. The total amount of Ge atoms in the SGOI normalized by the value before oxidation is plotted as a function of oxidation time. It is found that the amount is kept constant during oxidation. This result enables an estimation of the final Ge fraction xf

based on the simple relationship xf = xi (Ti/Tf ). Here, xi, Ti and Tf are the initial Ge fraction, and the initial and final SGOI thicknesses, respectively shown in Figure 3.2.

The conservation of Ge atoms in the SGOI layers and the low Ge concentration in the oxide layer indicate that the SiGe oxide layer rejected the Ge atoms which remained in the SGOI layer.

Figure 3.1 Scanning TEM image and Ge profile across the layers Obtained by EDS measurement. (Ref. 43)

Figure 3.2 The Ge fractions after dry oxidation. (Ref. 43)

After the oxidation process, the dislocation density significantly decreases, as show in Figure 3.3. This decrease is attributed to the high temperature annealing, lead to the rearrangement of the lattice.

Figure 3.3 Plane-view TEM observations (a) before and (b) after oxidation at the temperature of 1200 °C. (Ref. 44)

3.1.5 Motivation

SiGe oxidation is widely used in either SiGe/Si hetro-junction devices, poly-SiGe gated MOSs, or SiGe channel devices. However, the optimal oxidation condition is not known yet. In this study, we adopt different oxidation temperature, oxidation time, oxygen flow, and oxidation rate and investigate the influence on the electrical characteristics of SiGe-based p-MOSFETs.

3.2 The Process Flow of SiGe-Based P-MOSFET

P-type (Boron doped) Si substrate (100)-oriented with 1-10Ω-cm resistivity was used in this study. After initial RCA cleaning, 3000Å oxide was thermally grown at 980℃ by a horizontal furnace through wet oxidation, served as an isolation layer.

After one more time RCA cleaning, a 150Å thick amorphous-Si was deposited by LPCVD at 550℃, as a buffer layer between SiO2 and SiGe film. SiGe (Ge content at 7% and 11%) film was then deposited onto amorphous-Si layer about 800 Å by UHV-CVD, shown in Figure 3.4 (a).

By means of photolithography, the active region could be defined after photo-resist was removed. After S-D and channel patterning, TCP poly etcher was employed for SiGe etching by Cl2 and HBr. Later, the main part of this study proceeds by oxidizing the remaining SiGe part through different temperatures and times (top view shown in Figure 3.4 (b)). Oxidation parameters like temperature, time, and oxygen flow were tried in order to find out the optimum oxidation condition of SiGe channel. Moreover, pre-deposited-oxide before oxidation, oxidation rate controlling, and annealing after oxidation were also performed trying to make better electrical characteristics performance of SiGe-based p-TFT possible. All experimental factors are listed in Table 3.1 to Table 3.6.

Next, devices were dipped in BOE solution to remove surface SiO2 formed during oxidation of SiGe film. After 1000Å SiO2 deposited by PECVD served as gate dielectic, 600℃ annealing with O2 was performed to cure the defects in gate oxide.

Then, 2000Å poly-Si was deposited by LPCVD to work as control gate, shown in Figure 3.4 (c). After gate region and channel length defined by lithography, poly-etcher and BOE solution were used for etching. Top view is shown in Figure 3.5 (d). Then, Boron was doped heavily with 5x1015 cm-2 at 10 keV. Activation annealing at 950℃ in N2 flow was then employed for 30 minutes after ion implantation.

Figure 3.4 (a) The stack of SiGe/SiO2/Si. (b) Top view of SiGe-S/D and channel pattern. (c) The PE gate oxide and Poly gate were deposited. (d) Poly gate pattern.

3000Å SiO2 by PECVD was deposited as passivation layer. Lithography comes next to form contact holes. SiO2 was then etched by BOE solution for about 55 seconds. Finally, a 500 nm Al film was deposited by evaporation and then contact pads were patterned. Al sintering was performed at 430℃ for 30minutes.The detailed fabrication process flow is as follows:

1. (100) P⁺ Si wafer

2. RCA cleaning

3. Wet oxidation at 980^oC for 3000Å 4. RCA cleaning

5. 150Å amorphous-Si by LPCVD 6. RCA cleaning

7. 800Å SiGe(Ge content at 7% and 11%) by UHVCVD 8. Mask #1:Define active region

9. Dry etching by TCP poly etcher 10. PR removing and RCA cleaning 11. SiGe dry oxidation

12. BOE dipped to remove SiO2

13. RCA cleaning

14. PECVD SiO2 1000Å deposition

15. Gate oxide annealing at 600^o with O2 for 1hr 16. LPCVD poly-Si 2000Å deposition

17. Mask #2:Define gate and channel length

18. Wet etching by poly-etcher solution for 90 seconds 19. Wet etching by BOE solution for 25 seconds 20. PR removing

21. Boron doping of 5x10¹⁵ cm^-2 at 10 keV 22. Activation at 950^oC for 30 minutes 23. STD cleaning

24. PECVD SiO2 3000 angstrom deposition 25. Mask #3:Define contact hole

26. Wet etching by BOE solution for 50 seconds 27. PR removing

28. Al coating for 5000Å 29. Mask #4:Define contact pad 30. Al etching

31. PR removing

32. Sintering of Al at 430^oC for 30 minutes

The cross-section view of p-type SiGe-thin-film-transistor is shown in Figure 3.5.

Figure 3.5 The cross-section view of p-type SiGe-thin-film-transistor.

Alloy concentration Oxidation condition Variable: Temperature 1000 ^oC

950 ^oC Si0.89Ge0.11

16 minutes 3750 sccm O2 flow

un-oxidized Table 3.1 Influence of Oxidation Temperature Experiment

Alloy concentration Oxidation condition Variable: Time Table 3.2 Influence of Oxidation Time Experiment

Alloy concentration Oxidation condition Variable: O2 Flow 3750 sccm Table 3.3 Influence of Oxygen Flow Experiment

Alloy concentration Oxidation condition Variable: Thickness 1000Å Table 3.4 Influence of Thickness of Pre-Oxide Experiment

Alloy concentration Oxidation condition Variable: Rate 950 ^oC 15 minutes 900 ^oC 30 minutes Si0.93Ge0.07 3750 sccm O2 flow

850 ^oC 75 minutes Table 3.5 Influence of Oxidation Rate Experiment

Alloy concentration Oxidation condition Variable: Annealling 6hrs anneal

Si0.93Ge0.07

950 ^oC 5 minutes

3750 sccm O2 flow no annealing Table 3.6 Influence of Annealing After Oxidation Experiment

3.3 Results and Discussions

Id-Vg and Id-Vd characteristics in these experiments were measured by HP4156A. In the following measurements of current, all devices were normalized to W/L = 1μ/1μ. In Id-Vg measurements, Vd was applied at (-5 V). While Id-Vd was measuring, |Vg-Vt| was set at 3V.

3.3.1 Influence of Oxidation Temperature on Electrical Properties

Figure 3.6 (a) shows Id-Vg characteristics of three different devices: un-oxidized, oxidation at 950 , and oxidation at 1000 . Si℃ ℃ 0.89Ge0.11 film was used in these experiments, and both of the oxidized devices were oxidized for 16 minutes with 3750 sccm O2 flow. It can be seen that both oxidized devices show superior electrical performance than the un-oxidized one by higher On/Off ratio. The device of 1000 ℃-oxidized shows even higher on current than the one of 950 ℃-oxidized one while both devices have roughly the same off state current.

Figure 3.6 (b) shows Id-Vd characteristics which are consistent with the prediction: the device oxidized at 1000 ℃ has highest Id of the three devices – 2.58µA at Vd = (-6)V. 950℃- oxidized device has 1.83 µA, and the un-oxidized one has 0.40µA. It was known that since SiGe got oxidized, concentration of Ge would be increased, and then mobility would also get enhanced which resulted in a higher on state current, On/Off ratio gets improved then. With higher oxidation temperature, the rate of oxidation would be higher, which made more Si in SiGe film oxidized. Then the mobility would be even higher, and better performance was achieved.

Figure 3.6 (a) Id-Vg characteristics of different oxidation temperatures. (b) Id-Vd characteristics.

3.3.2 Influence of Oxidation Time on Electrical Properties

Figure 3.7 (a) shows Id-Vg characteristics of four different devices: un-oxidized, oxidized for 4 minutes, oxidized for 16 minutes, and oxidized for 36 minutes, respectively. Si0.93Ge0.07 film was used in these experiments. All of the oxidized devices were oxidized at 1000^oC with 3750 sccm O2 flow. From the diagram, the trend of the curves indicates that longer oxidation time results in higher on state current. Besides, after calculation, the On/Off ratio of 36m-oxidized, 16m-oxidized, and 4m-oxidized is 3.3, 1.6, 1.5 times higher than that of the un-oxidized device, respectively. Due to the same reason as described previously, in the longer oxidation

time devices, more amount of Si was oxidized and then higher Ge concentration was achieved. Figure 3.7 (b) depicts Id-Vd characteristics for devices with different oxidation times. As predicted, 36m-oxidized device has highest on current, which is 5.08µA at Vd = (-8)V. For the other devices, they are 1.52µA, 0.75µA, and 0.61µA for 16m-oxidized, 4m-oxidized, and un-oxidized devices, respectively.

It is presumed that unless Si in the SiGe layer is fully oxidized, the performance of the SiGe-based p-MOSFET would always be improved with the increasing of oxidation time since the positive correlation between the amount of oxidized Si and the mobility of SiGe channel.

Figure 3.7 (a) Id-Vg characteristics after different oxidation times; the temperature is 1000℃ (b) Id-Vd characteristics.

3.3.3 Influence of Oxygen flow on Electrical Properties

Si0.89Ge0.11 film was used in this experiment. Devices were oxidized at 1000^oC for 16 minutes. Figure 3.8 (a) depicts Id-Vg characteristics of devices with different oxygen flows during oxidation: 3750 sccm, 2500 sccm, and un-oxidized. The device under larger oxygen flow shows larger on-state current and lower-off state current, which are undoubtedly better than the devices oxidized under 2500 sccm oxygen flow and the un-oxidized one. It is supposed to be contributed by more Si being oxidized, as discussed before. The On/Off ratios of 3750sccm-device and 2500sccm-device are 5.89 and 1.86 times higher than the un-oxidized one. As to Id-Vd characteristics, which is shown in Figure 3.8 (b), the device with 3750 sccm O2 flow has 2.56µA at Vd = (-6)V. The devices with 2500 sccm O2 flow and un-oxidized have 1.83µA and 0.43µA, respectively. From the experiments above, the amount of oxidized Si explains the improvement of electrical charateristic performance well. In the following study, several different oxidation conditions were applied, and some other results would be achieved.

Figure 3.8 (a) Id-Vg characteristics after different oxygen flow rates at 1000℃ (b) Id-Vd characteristics.

3.3.4 Influence of the Thickness of Pre-oxide on Electrical Properties

As it is known that the oxidation rate would decreases with increasing the oxidation time, a new experiment is designed to investigate the influence of the initial oxidation rate on electrical performance of SiGe-based TFT. SiO2 was deposited onto SiGe film first by PE-CVD just after UHV-CVD SiGe film deposited. The thicknesses of SiO2 were 300Å, 500Å, and 1000Å, respectively, and a non-pre-oxide device was also fabricated. Si0.93Ge0.07 was used in this experiment and oxidation was performed at 1000^oC for 36 minutes with 3750 sccm O2 flow. Figure 3.9 (a) depicts Id-Vg characteristics of devices with different thickness of pre-oxide. The On/Off ratio is

getting higher while the thicknesses of pre-oxide is getting larger, which is 2.6, 1.9, 1.7 times higher than that of non-pre-oxide device, respectively. But on the other hand, the on-state current decreases. It is presumed that less amount of Si in SiGe film would be oxidized owing to thicker pre-oxide existing that results in lower on current.

As shown in Figure 3.9 (b), Id at Vd = (-8 V) of non-pre-oxide, 300 Å, 500 Å, and 1000 Å are 5.46µA, 2.79µA, 1.07µA, and 0.95µA, respectively. But there is still benefit from depositing pre-oxide. Since the oxidation rate was lowered by pre-oxide, the segregation Ge atoms would distribute evenly in SiGe channel, which lowers the off-state current, and results in a higher On/Off ratio.

Figure 3.9 (a) Id-Vg characteristics with different thicknesses of pr-oxide deposited before oxidation ; the temperature is 1000℃ and the time is 36 min. (b) Id-Vd characteristics.

3.3.5 Influence of Oxidation Rate on Electrical Properties

In the previous study, it is concluded that under lower oxidation rate, SiGe-based p-TFT would achieve better On/Off ratio performance. However, the amount of oxidized Si in last experiment was still a variable. The factor of the amount of oxidized Si was removed by a new designed method. Several oxidation conditions were performed first and the thickness of SiO2 was measured. Three oxidation conditions of roughly the same thickness of SiO2 were selected. They are 950^oC 15 minutes, 900^oC 30 minutes, and 850^oC 75 minutes, respectively, which indicate the same amount of Si oxidized. Si0.93Ge0.07 was used in this experiment and oxidation was performed with 3750 sccm O2 flow. Figure 3.10 (a) depicts Id-Vg characteristics at Vd = -5 V. On-state current of the three devices almost equals, but the device with lower oxidation rate has lower off-state current, which supports our conclusion from the previous study. In Figure 3.10 (b), it is shown that the on-state current of the three devices are also almost the same at about 2.1 ~ 2.3 µA. As predicted, same amount of oxidized Si results in same Id. Slow oxidation rate makes Ge atoms distribute evenly and then makes lower off-state current which achieves a higher On/Off ratio.

Figure 3.10 (a) Id-Vg characteristics of different oxidation rates. (b) Id-Vd characteristics.

3.3.6 Influence of Annealing after Oxidation on Electrical Properties

In the final section, annealing was performed after SiGe film oxidation.

Si0.93Ge0.07 was used in this experiment and oxidation was performed at 950^oC for 5

Si0.93Ge0.07 was used in this experiment and oxidation was performed at 950^oC for 5