Influence of Oxidation Rate on Electrical

In the previous study, it is concluded that under lower oxidation rate, SiGe-based p-TFT would achieve better On/Off ratio performance. However, the amount of oxidized Si in last experiment was still a variable. The factor of the amount of oxidized Si was removed by a new designed method. Several oxidation conditions were performed first and the thickness of SiO2 was measured. Three oxidation conditions of roughly the same thickness of SiO2 were selected. They are 950^oC 15 minutes, 900^oC 30 minutes, and 850^oC 75 minutes, respectively, which indicate the same amount of Si oxidized. Si0.93Ge0.07 was used in this experiment and oxidation was performed with 3750 sccm O2 flow. Figure 3.10 (a) depicts Id-Vg characteristics at Vd = -5 V. On-state current of the three devices almost equals, but the device with lower oxidation rate has lower off-state current, which supports our conclusion from the previous study. In Figure 3.10 (b), it is shown that the on-state current of the three devices are also almost the same at about 2.1 ~ 2.3 µA. As predicted, same amount of oxidized Si results in same Id. Slow oxidation rate makes Ge atoms distribute evenly and then makes lower off-state current which achieves a higher On/Off ratio.

Figure 3.10 (a) Id-Vg characteristics of different oxidation rates. (b) Id-Vd characteristics.

3.3.6 Influence of Annealing after Oxidation on Electrical Properties

In the final section, annealing was performed after SiGe film oxidation.

Si0.93Ge0.07 was used in this experiment and oxidation was performed at 950^oC for 5 minutes with 3750 sccm O2 flow. Device was annealed for 6 hours after oxidation, and a non-annealing device was also fabricated. Figure 3.11 (a) depicts Id-Vg characteristics at Vd = -5 V. The On/Off ratio of 6 hrs-annealing-device was slightly improved by 1.4 times than non-annealing device. In Figure 3.11 (b), Id-Vd characteristic diagram is shown. Nearly 80% Id improvement is achieved by annealing for 6 hours, which is 3.90µA, in comparion with 2.17µA of the

non-annealing device. It is supposed that annealing at high temperature cures the defects in the SiGe channel, and facilitates evenly distribution of Ge in SiGe channel and thus improves the on-state current and the leakage current.

Figure 3.11 (a) Id-Vg characteristics of annealing applied. (b) Id-Vd characteristics.

3.4 Summary

It is found that all the electrical characteristics such as On/Off ratio, and on state current would get improvement after the SiGe channel was oxidized. This is because after oxidation, Si atoms in SiGe channel would be combined with O atoms to form SiO2 while Ge atoms would be separated from that. The more amount of Si in the SiGe film was oxidized, the more Ge atoms would exist in the SiGe channel and then

makes Ge concentration higher that results in higher hole mobility in SiGe-base p-TFT. With the amount of oxidized Si increasing, the hole mobility also increases and then better electrical performance would be achieved. Experiments of oxidation temperature, oxidation time, and oxygen flow already proved this phenomenon.

Oxidation rate was also considered in our experiment. The results show that the devices under slower oxidation rate have lower leakage current and better On/Off ratio. It is conjectured that the separated Ge atoms would distribute evenly in the SiGe channel under slow oxidation process and then a high quality channel was formed.

This is why the devices have lower leakage current. It is found that the device under annealing for 6 hours has higher on-state current, and On/Off ratio. It is presumed that high temperature would cure the defects in the channel, and thus improves electrical performance. The results will be applied into SiGe nano-wire for high performance SiGe nanowire.

Chapter 4

The Higher Current of SiGe Nanowire by Oxidation 4.1 Introduction

As the channel length of metal-oxide-semiconductor field effect transistors (MOSFETs) is deeply scaled down to sub-100 nm, enhancement of the carrier mobility in the channel is desired for improving the performance of complementary MOS (CMOS) circuits²⁸. For this purpose, Ge is a promising channel material for MOSFETs because of high mobility of both the electrons and holes. Enhanced device performances have been demonstrated by using a strained Si channel grown upon a relaxed (SiGe) substrate²⁹, where the electron mobility is increased due to the reduced intervalley phonon scattering³⁰. However, at lower Ge content, only moderate increase in hole mobility could be achieved in strained Si compared to bulk Si³¹. On the other hand, with high Ge content (83%), SiGe channel high hole mobility enhancement in PMOSFETs can be realized³². To achieve the highest enhancement, pure Ge channel is attractive.

The oxidation of SiGe thin films has been demonstrated at several laboratories^37-40. In these cases, enough Ge on the oxidation of Si had to be snow-plowed in order for oxidation enhancement to be observed. They proposed that breaking of the weaker Si-Ge bound as compared with Si-Si explain the rate enhancement. This may only be the last event, not necessarily controlling. According to the theory binary alloy oxidation^41-42, the oxide growth will depend on the alloy composition. For the case of the SiGe alloy, Si is more reactive than Ge. The reason is the large difference between the heat of formation of SiO2 (-204 kcal/mol) and GeO2 (-119 kcal/mol). For SiGe with low Ge concentration (< 50%), only silicon is oxidized initially. Ge is completed rejected from the oxide and piles up at the oxide/substrate interface. On the other hand,

oxygen concentration at the oxidation front decreases with the oxide thickness increases. Then, the decreasing oxygen concentration at the oxidation front counteracts the effect of increasing Ge concentration in the Ge-rich SiGe layer so that Ge is not oxidized during the entire oxidation process. In this chapter we tried to fabricate a SiGe nanowire with higher drive current by Ge condensation technique.

4.2 Experiment

The side-wall spacer formation is an easy process for nanowire fabrication with the advantages of high-yield and low-cost. The method only using the combination of the conventional lithography and processes technology was demonstrated without complex processes such as EBL, SPL and VLS etc. In the beginning, a p-type (100)-oriented bare silicon wafer with 1-10Ω-cm resistivity was prepared.

9. After standard RCA cleaning, 980℃ Wet Oxidation was performed for 1 hours to grow the bottom oxide as an insulator oxide by ASM/LB45 Furnace system. The thickness of the oxide is 3000Å which was shown in Figure 4.1.

10. Mask #1: Define the active area. We etched the oxide 1000 - 1500 Å by dry oxide etcher (TEL 5000) after Mask I defined. Then, a 1500 - 2000 Å oxide step was formed shown in Figure 4.2.

11. Following standard RCA clean, we deposited 150Å amorphous Si film on bottom oxide in the condition of 650℃ and 160 mTorr. The process increased adhesion between SiGe film and SiO2 layer shown in Figure 4.3.

12. Then, 500-1000 Å SiGe films with different Ge concentrations were deposited with the ultra-high-vacuum chemical vapor deposition (ANELAVA SiGe UHV-CVD) at 650℃. Also, the 800 Å poly-Si film was deposited, too. The structure is shown in Figure 4.4.

13. We defined the S/D contact regions with Mask II, and etched the whole height of

the SiGe film (20% over etched) and the poly-Si film (20% over etched) by TCP poly etcher in the follows. Only the S/D and SiGe/poly-Si deposited in the sidewall spacer were stayed. The residual SiGe film is what we want – SiGe nanowire. The structure is shown in Figure 4.5.

14. Next, we etched each pair of the parallel SiGe NW by TCP poly etcher after Mask III was defined. Thus, the poly-Si/SiGe nanowires were isolated. The structure is shown in Figure 4.6.

15. In the follows, oxidation was employed with various conditions.

16. Finally, the aluminum was then deposited with a thickness of 5000 Å by thermal coater. Mask IV was used to reserve the S/D region, and then 400℃ sintering 30 min was done shown in Figure 4.7.

17. Al sintering at 430℃ in N2 ambient for 25 minutes.

Figure 4.1 3000Å SiO2 layer was grown on Si substrate.

Figure 4.2 Definition of the active area. The height of oxide step is 1000Å

.

Figure 4.3 150Å Amorphous Si layer is deposited on SiO2 layer.

Figure 4.4 SiGe films with different Ge concentration were deposited on α-Si layer.

Figure 4.5 The definition of the S/D region and nanowire. (a) The 3-D view (b) The top view

Figure 4.6 Remove one side of the parallel SiGe spacer to cut off the leakage current (a) The 3-D view (b) The top view.

Figure 4.7 Defined Al contact pad. (a) The 3-D view (b) The top view.

4.3 Results and Discussions

The dimensions of SiGe nanowire was observed by Scanning Electron Microscope (SEM) after SiGe dry etching. Figure 4.8 (a) shows the cross-section view SEM picture of Si0.93Ge0.07 nanowire, which shows the dimension of 192 nm in height and 77.7 nm in width, (b) shows the SEM image of SiGe nanowire with 168 nm in height and 55.9 nm in width after 2 min. 900 oxidation and (℃ c) shows that with 160 nm in height and 42.8 nm in width after 2 min. 950 oxidation.℃

Figure 4.8 (a) The cross-section view of Si0.93Ge0.07 nanowire with 192 nm in height and 77.7 nm in width. (b) the SEM image of SiGe nanowire with 168 nm in height and 55.9 nm in width after 2 min. 900 oxidation and (℃ c) shows that with 160 nm in height and 42.8 nm in width after 2 min. 950 oxidation.℃

The electrical properties of SiGe nanowires were measured by an Agilent 4156C semiconductor parametric analyzer. Figure 4.9 (a) shows the current without gate voltage applied. The lower current was found after higher temperature oxidation. In order to compare conductivity of the un-oxide and oxide nanowires, we normalized the current by multiply length and divide the area. The higher conductivity was obtained for Ge condensation technique. The conductivity is 23500 (S/m) after 950℃, 2 min. oxidation which is higher than un-oxide (15900).

Figure 4.9 (a) ID-VD curve of Si0.93Ge0.07 nanowire with unoxidized, 900 ℃ 2 min.

and 950 ℃ 2 min. respectively. (b) The conductivity of Si0.93Ge0.07 nanowire with unoxidized, 900 ℃ 2 min. and 950 ℃ 2 min. respectively.

4.4 Summary

The side-wall spacer N-type SiGe nanowires after oxidation were fabricated to compare the sensitivity between the nanowires. The SEM image was used to know the dimension of nanowire with/without oxidation. The lower current appeared after oxidation. However, the higher conductivity obtained after oxidation.

Chapter 5

The Ge enhances the Sensitivity for Bio-Sensor 5.1 Introduction

Since the development of nano-technology, more and more people combine the one-dimension nano-structure with bio-molecular. Due to the large surface-to-volume ratio and quasi-1D characteristics, the Silicon nanowire (NW) sensor provides a high sensitivity in chemical detection such as pH buffer solution, protein, ions, and DNA etc^5-7. Silicon nanowires (SiNWs) are particularly appealing for sensing applications since the silicon dioxide can effectively passivate surface dangling bonds, and at the same time can be chemically modified through the well known silanol chemistry to provide surface functionalization and, therefore, selectivity for particular analytes.

Beside the Si NW nan-sensor, other materials were used to detect different materials.

Gas sensors have been fabricated by using the SnO2, In2O3, WO3 and ZnO nanowires

10-14. The responses of the sensors have been characterized for gaseous polluting species like CO and NO2. Conducting polymers have attractive features such as mechanical flexibility, easy processing, and modifiable electrical conductivity.

Polyaniline/poly-(ethylene oxide) (PANI/PEO) nanowire sensors can detect NH3 gas at concentrations as low as 0.5 ppm with rapid response and recovery time^5-16. Pd nanowires have been studied to detect hydrogen gas due to safety reasons¹⁷. The sensor was based on the resistance change of Pd nanowires upon hydrogen incorporation. The high surface-to-volume ratio of nanowires results in a strong dependence of carrier concentration on charge transfer from the surface and changes in nanowire conductance. For the study of SiGe field effect transistor¹⁹, we could found that the higher current change as the same gate voltage applied shown in Figure 5.1. However, the mechanism for the Si nanowire sensor is detecting the surface

charge as the molecular stays on it. Therefore, if we used the SiGe nanowire instead of Si nanowire, we would get higher current change at the same bio-molecular bound on the surface. In this paper, we used the sidewall spacer technique²³ to fabricate the SiGe nanowire (NW) with high carrier mobility instead of Si nanowire to investigate the sensitivity.

Figure 5.1 Drain current of N- and P-MOSFETs are improved with Si/SiGe-channel.

(Ref. 19)

5.2 Experiment

The side-wall spacer formation is an easy process for nanowire fabrication with the advantages of high-yield and low-cost. The method only using the combination of the conventional lithography and processes technology was demonstrated without complex processes such as EBL, SPL and VLS etc. In the beginning, a p-type (100)-oriented bare silicon wafer with 1-10Ω-cm resistivity was prepared.

18. After standard RCA cleaning, 980℃ Wet Oxidation was performed for 1 hours to grow the bottom oxide as an insulator oxide by ASM/LB45 Furnace system. The

thickness of the oxide is 5500Å which was shown in Figure 5.2.

19. Mask #1: Define the active area. We etched the oxide 3000 Å by dry oxide etcher (TEL 5000) after Mask I defined. Then, a 2500 Å oxide step was formed shown in Figure 5.3.

20. Following standard RCA clean, we deposited 150Å amorphous Si film on bottom oxide in the condition of 650℃ and 160 mTorr. The process increased adhesion between SiGe film and SiO2 layer shown in Figure 5.4.

21. Then, 6000 Å SiGe films with different Ge concentrations were deposited with the ultra-high-vacuum chemical vapor deposition (ANELAVA SiGe UHV-CVD) at 650℃. The structure is shown in Figure 5.5.

22. We defined the S/D contact regions with Mask II, and etched the whole height of the SiGe film (20% over etched) and the poly-Si film (20% over etched) by TCP poly etcher in the follows. Only the S/D and SiGe/poly-Si deposited in the sidewall spacer were stayed. The residual SiGe film is what we want – SiGe nanowire. The structure is shown in Figure 5.6.

23. Next, we etched each pair of the parallel SiGe NW by TCP poly etcher after Mask III was defined. Thus, the poly-Si/SiGe nanowires were isolated. The structure is shown in Figure 5.7.

24. Finally, the aluminum was then deposited with a thickness of 5000 Å by thermal coater. Mask IV was used to reserve the S/D region shown in Figure 5.8.

25. Al sintering at 430℃ in N2 ambient for 25 minutes.

Figure 5.2 3000Å SiO2 layer was grown on Si substrate.

Figure 5.3 Definition of the active area. The height of oxide step is 1000Å

.

Figure 5.4 150Å Amorphous Si layer is deposited on SiO2 layer.

Figure 5.5 SiGe films with different Ge concentration were deposited on α-Si layer.

Figure 5.6 The definition of the S/D region and nanowire. (a) The 3-D view (b) The top view

Figure 5.7 Remove one side of the parallel SiGe spacer to cut off the leakage current (a) The 3-D view (b) The top view.

Figure 5.8 Defined Al contact pad. (a) The 3-D view (b) The top view.

5.3 The Dimension of Nanowires

The dimension of SiGe nanowire was controlled by the deposition for the width and the step of oxide for the height. In order to etch the SiGe film clearly, we added the 20% over-etching at the step of dry etching. The dimensions of SiGe nanowires with different Ge concentrations were observed by Scanning Electron Microscope (SEM) after SiGe dry etching. Figure 5.9 (a) shows the cross-section view of SEM picture of Si0.93Ge0.07 nanowire, which shows the dimension of 192 nm in height and 77.7 nm in width. Figure 5.9 (b) shows the Si0.89Ge0.11 nanowire with 184 nm in height and 45.4 nm in width, (c) shows the Si0.8Ge0.2 nanowire with 159 nm in height and 65.9 nm in width, (d) shows the Si0.7Ge0.3 nanowire with 153 nm in height and 54.5 nm in width and (e) shows the Si0.6Ge0.4 nanowire with 172 nm in height and 53.4 nm in width respectively. Because of the hardly-controlled deposition of SiGe film and dry etching for different SiGe film, we made the different dimensions of SiGe nanowires.

Figure 5.9 (a) The cross-section view of Si0.93Ge0.07 nanowire with 192 nm in height (H) and 77.7 nm in width (W). (b) The Si0.89Ge0.11 nanowire with H = 184 nm and W = 45.4 nm (c) The Si0.8Ge0.2 nanowire with H = 159 nm and W = 65.9 nm. (d) The Si0.7Ge0.3 nanowire with H = 153 nm and W = 54.5 nm. (e) The Si0.6Ge0.4 nanowire with H = 172nm and W = 53.4 nm.

5.4 Results and Discussions

The electrical properties of SiGe nanowires were measured by an Agilent 4156C semiconductor parametric analyzer. We swept the ID-VD from –10 V to 10 V, and changed the bottom gate VG = –15, 0V and 15V respectively. The ID-VD curve of Si0.93Ge0.07 nanowire is shown in Figure 5.10 (a), and the diagram is shown below the curve. It is observed that the bottom gate has less influence on the drive current for too thick insulation oxide. In order to make sure that the measured-current came from the nanowire, we made a test structure below the Figure 5.10 (b). It is seen that only few pA current obtained for two isolated pads. Also, the effect of bottom gate is few pA current which could not measure in Figure 5.10 (a). Other currents of SiGe nanowires with different Ge concentrations have the same phenomenon.

Figure 5.10 (a) The ID-VD curve of Si0.93Ge0.07 nanowire. (b) The cut-off current between the two contact pads.

As the discussion in the introduction, the powerful application of nanowire is used for the nano-sensor. For comparing the sensitivity between the SiGe nanowires with different Ge concentrations, we chose the 3-amino-propyl-trime-thoxy-silane (APTS)

to modify the surface condition of silicon dioxide layer around the SiGe NWs. The hydroxyl molecules were replaced by the methoxy side of the APTS molecules that the surface voltage changed from negative to positive, shown in Figure 5.11 (a). This change of the surface condition resulted in accumulating state for N-type Si0.93Ge0.07

nanowires that ID on accumulated state had higher current than un-modified, which is shown in Figure 5.11 (b). We calculate the conductance for the comparison of the change with/without APTS on the SiGe nanowire. The normal symbol shows the conductance in the beginning and the APTS symbol shows the conductance after APTS modified. It is observed that the higher conductance obtains after APTS modified, the amounts of the APTS molecules binding on the oxide surface performed like a constant voltage applied on the Si0.93Ge0.07 nanowire. For clearly proving the result, the bis-sulfo-succinimidyl suberate (BS3) was applied to link the APTS molecule shown in Figure 5.11 (a). In Figure 5.11 (b), we could observe that the conductance of BS3 became lower after BS3 linked. The reason for the BS3 molecules only link with APTS molecules that the total amounts of BS3 molecules were limited by APTS molecules. In addition, the BS3 molecule was easier to release the sodium ion or to break the single bond between the carbon atom and the oxygen atom that these two results all caused the negative gate voltage, which depleted the N-type SiGeNWs.

Fig. 5.11 (a) The mechanism image of the 3-amino-propyl-trime-thoxy-silane APTS and bis-sulfo-succinimidyl suberate BS3 molecular linkage on the nanowire. (b) The conductance of N-type Si0.93Ge0.07 nanowire with/without APTS and BS3 modified.

The conductance increases for positive charge of APTS and decreases for the negative charge of BS3.

Figure 5.12 (a) shows the conductance of Si0.89Ge0.11 nanowire with/without ATPS and BS3 modified. We also found that the conductance increased after APTS modified (accumulation) and decreased after BS3 modified (depletion). Figure 5.12 (b), (c) and (d) show the conductance of Si0.8Ge0.2, Si0.7Ge0.3 and Si0.6Ge0.4 nanowire respectively. The similar phenomenon is also observed in other SiGe nanowires with different Ge concentrations.

Figure 5.12 (a) The conductance of N-type Si0.89Ge0.11 nanowire with/without APTS

Figure 5.12 (a) The conductance of N-type Si0.89Ge0.11 nanowire with/without APTS