CHAPTER 1 INTRODUCTION
1.2 T HESIS O RGANIZATION
The thesis is divided into seven chapters detailed as follow:
Chapter 2
This chapter reviews the state-of-the-art ADCs suitable for high-speed operation. The basic principles of design methodologies and requirements of these architectures as introduced. And, the advantages and disadvantages of various architectures are also studied in this chapter.
Chapter 3
This chapter analyzes various types of high speed flash architectures. The suitable flash ADC architecture for ultra high speed operation is reported. The advantages of this architecture and the disadvantages of other architectures are described in this chapter.
Chapter 4
Firstly, we design a 4-bit flash ADC which typically operates at 3.125 GSps and maximally at 4 GSps. The basic block and circuit diagrams are detailed. The key ideas in improving the sampling rate and resolution bandwidth are also presented in this chapter.
Chapter 5
Secondly, we design 5-bit flash ADCs based on the 4-bit architecture presented in chapter 4. The 5-bit flash ADCs have the same specification in speed.
The key ideas in improving the accuracy are also presented in this chapter.
Chapter 6
The simulated results of these flash ADCs are discussed in this chapter, which
include the static performance in time domain analysis and the dynamic performance in frequency domain analysis.
Chapter 7
This chapter compares our works with the researches of others in resent years and gives the conclusions.
Chapter 2
Review of High Speed CMOS ADC Architectures
In resent year, there are several architectures to implement high-speed analog-to-digital converters. Each has advantages and disadvantages with a particular combination of speed, accuracy, and power consumption. They all fit into a particular application. These various architectures are based on the search technique used to find appropriate digital representation of the analog input level. The design methodologies for full flash, interpolating, time interleaved, pipelined, and folding architectures will be described in this chapter.
2.1 Full Flash ADC
The full flash architecture is the simplest and fastest analog-to-digital converter.
In a full flash analog-to-digital converter, the analog input signal is simultaneously compared to reference values by a bank of comparator circuits. The differences between the input and reference values are amplified to digital levels and generate thermometer code, as shown in Figure 2.1. The thermometer code is easily encoded into binary or gray code. The reference voltages are usually provided by tapping from a resistor reference ladder to generate the monotonic increase of reference voltages from zero to the input full scale. Preamplifiers are often added in front of comparators
to reduce the overall input-referred offset by lowering the impact of comparator dynamic offset with preamplifier gain.
Figure 2.1 Full flash ADC architecture.
For a N-bit flash ADC, 2N −1 comparators and 2N resistors are needed.
Although flash ADC can achieve high speed, but the amount of comparators and resistors depend on the resolution of ADC and this quantity grows exponentially with resolution. Relatively, the resulting circuit is typically very large and consumes a great deal of power. So that, most flash ADC studies have been focused on resolution lower than 8-bit. However, the objective of this work is to design 4GSps 4-bit and 5-bit Nyquist Rate ADC in a 0.18-um CMOS process. Since speed is the top priority,
high
Vref,
V in
Binary Output
low
Vref,
2.2 Interpolating ADC
The full flash ADC is considered to realize the highest conversion rate but it suffers from not only larger chip size and larger power dissipation, but also lower dynamic performance due to large input capacitance. Consequently, interpolating conception alleviates the effect drastically. The diagram of interpolating architecture is shown in Figure 2.2. Amplitude quantization can be viewed as a collection of zero crossings. The front-end preamplifiers can be followed by differential pairs to perform 2-times interpolation, thereby creating additional zero crossings and increasing the resolution.
Figure 2.2 Interpolating ADC architecture.
+1
Interpolation reduces the number of the pre-stages. In other words, interpolation relaxes a number of tradeoffs in the design of the front-end. The preamplifiers typically suffer from the most stringent requirements in terms of input common-mode range, input capacitance, power dissipation, overdrive recovery speed, voltage gain, and capacitive feed-through to the reference ladder. Hence, it is desirable to reduce the number of preamplifiers through the use of interpolation. Another aspect of interpolation is that it does not require precise gain in any of the stages because only the zero crossings carry the information.
2.3 Time Interleaved ADC [8]
The time-interleaved technique can be used in nearly any type of ADCs. It consists of M ADCs operating at different clock phases. The corresponding digital multiplexer selects the digital output of each ADC periodically and forms a high speed ADC output as shown in Figure 2.3.
Figure 2.3 Time interleaved ADC architecture and timing.
Although the clock speed of such a architecture can be very high by just extending the parallel paths, the mismatch issue will then cause the fundamental
t
limitations. Among those are the gain mismatch, the offset mismatch, and the timing mismatch. As shown in Figure 2.4, these problems introduce some distortions, centered around multiples of channel sampling rate as sideband components for channel gain mismatch and timing skew, and at multiples of channel sampling rate as tones for channel offset mismatch. Embedding a track-and-hold circuit in front of each channel can effectively reduce the effects. The clock for the track-and-hold circuit must be operating at the overall ADC speed. When the parallel pipelined architecture has a single track-and-hold circuit, the timing mismatch among the channels is not an issue. Because track-and-hold circuit is distributing sampled signals instead of dynamic signals.
Figure 2.4 Spectrum of a reconstructed sinusoid for a four-way converter array.
f in fs/4 fs /2
f dB
f in fs/4 fs /2 f in fs/4 fs /2
dB dB
f f
Perfect Match
Gain Mismatch &
Timing Skew
Offset Mismatch
2.4 Pipelined ADC
The large input capacitive loading of the full ash ADC can be avoided by using one resolution per stage configuration, leading to the pipelined approach. Basically, the pipelined ADC can inherently have better dynamic performance due to the reduced loading per stage and inter-stage track-and-hold operation. The general block diagram of a pipelined ADC is shown in Figure 2.5.
Figure 2.5 Pipelined ADC architecture.
As shown in the figure, the pipelined ADC is basically a residue processing system. The residue contains the required information as well as the imperfections, including offset errors, inter-stage gain errors, inter-stage DAC nonlinearity, and operational amplifier settling-time errors. With digital correction, the effects of offset error, gain error are reduced, while the inter-stage DAC nonlinearity and operational amplifier settling-time errors limit the performance of pipelined ADC. Another drawback is the long latency of pipelined ADC which avoids its application in a closed-loop linear feedback system, however, this is not a problem in wireless communication systems.
2.5 Folding ADC [9]
The folding ADC, unlike the pipelined ADC which serially output the digital codes, output them in two parallel paths called coarse and fine quantization, respectively. Therefore, the speed approaching the full flash ADCs is possible with careful design. Typically, it is beyond the pipelined ADC. Figure 2.6 shows the block diagram of a folding ADC of 8-bit resolution associated with its transfer curve.
Figure 2.6 Folding ADC architecture and the transfer curve of a folding circuit in comparison with the full flash ADC.
Coarse ADC
Fine ADC V in
Folding Circuit
3 MSBs
5 LSBs
Vout
Vin
Full Flash Full Flash
256 Levels
Folding 32 Levels Folding
000 001 010 011 100 101 110 111
difference is the encoding method. As a result, the comparator count for the folding converter is 32 for fine and 8 for coarse with a total of 40. It is much less than 255 required by a full flash ADC.
Folding architectures exhibit low power and low latency as well as the ability to run at a higher sampling rate. The drawback is the limited dynamic performance due to input frequency multiplication and bandwidth limitation of the folding circuitry.
Chapter 3
Design Techniques of Flash ADC
There are several techniques to design a flash ADC. After reviewing many methods which were provided to design a flash ADC in resent years, we propose the most suitable architecture to meet our speed target. In Section 3.1, a detail description about averaging concepts is given. Section 3.2 describes the interpolation concepts.
Section 3.3 analyzes several architectures which were provided in resent years.
Section 3.4 shows the architectures which are used in our 4-bit ADC and 5-bit ADC circuit design.
3.1 Averaging Technique
In continuous time systems, offsets of amplifiers are the main limitation to increase the converter resolution above 6 bits. However, it has been shown already that sizing the input devices results in a reduction in the offset voltage. This transistor sizing, however, is limited and introduces disadvantages like large input capacitance, large die size and high power dissipation. To partially overcome this problem, an averaging scheme will be introduced. This averaging scheme uses the outputs of more active input pairs to increase the effective gate area and in this way reduce the offset voltages [10].
3.1.1 Resistive Averaging
In Figure 3.1 a system using resistive averaging is shown. The figure shows three differential amplifiers with load resistors R1 as part of the input amplifier chain used in a flash analog-to-digital converter. Averaging is obtained by coupling the outputs of the differential amplifiers via averaging resistors R0. This average resistor chain continues to couple more input stages. As long as the input amplifiers are active and operate in the linear signal range, the output signals of these active amplifiers contribute via the averaging resistors to a differential amplifier operating around the
“zero crossing” level. The differential pair M3, M4 is the zero crossing one. It is affected by both left and right neighbors.
Figure 3.1Resistive averaging scheme [11]
As long as the neighboring amplifiers are in the linear region, it looks like that the zero crossing amplifier consists of a much bigger device with a size equal to the sum of the areas of the active linear amplifiers. As a result, a very rough estimation of the reduction in offset voltage compared to a non-coupled single differential amplifier equals to Nactive is obtained. Here Nactive is the number of linear active amplifier stages contributing to the output signal of the zero crossing stage.
Furthermore the signal amplitude increases with a value equal to Nactive while the Vrefn-1
noise increases with Nactive . As a result, the signal-to-noise ratio improves with
active
N , and the offset voltage reduces with the same ratio.
3.1.2 Active Averaging
Figure 3.2 shows the circuit diagram of such a system. Again, an averaging construction is shown using three differential pairs. The input pairs in this system are split up into three parts. An equal split is one of the possibilities that can easily be implemented. Starting with the middle pairs consisting of M1 to M6, the output current of M1 and M4 go directly to the load resistors R1 and R2, M2 and M5 to the right, and M3 and M6 to the left. As fro the center stage, the output signal is obtained as the sum of the three neighboring pairs. Therefore, the linearity is improved. Only two extra pairs are required at both ends of the reference ladder. A drawback of this system is that more accurate elements are required to minimize the influence on the offset and linearity.
Figure 3.2 Active averaging scheme M3M2M1 M4M5M6
VinB NVinB VinA NVinA VinC NVinC
R1 R1 R1
R1 R1 R1
3.2 Interpolation
The output signals from the input amplifiers have a finite slope. Furthermore the difference between the signals is limited. As a result it is possible to accurately interpolate between two reference levels and obtain an accurate zero crossing of the differential output signal. The number of input amplifiers can be reduced depending on the number of times an interpolation takes place [10].
3.2.1 Resistive Interpolation
In Figure 3.3 shows a resistor interpolation circuit. As shown in this figure, the signal VoutnInt is interpolated between Voutn and Voutn+1. An extra zero crossing is obtained in this way without an input amplifier.
Figure 3.3 Resistive interpolation scheme V in
3.2.2 Active Interpolation
An alternative to resistive interpolation is the active interpolation. In this system amplifier transistors are split up into two equal devices as shown in Figure 3.4. As shown in the figure, all transistors have equal size. A size of 0.5 is given relative to the input differential pairs. At the gates of transistors M1 and M2 the output signal from pairs A is applied, while at the gates of transistors M3 and M4 the output signal of pairs B is introduced. These signals show a delay in time as can be seen from Figure 3.4. The drain currents of M1 and M3 are added as has been done for M2 and M4 too. And these combined drain currents flow through the load resistors R1 and R2.
The output signal of this stage interpolates now between the output signal of pairs A and the output signal of pairs B. With witch, the pairs A and B are averaged. As long as offset voltages and mismatches are small as compared to the required interpolation accuracy, this interpolation method will not show any interaction between the stages.
It performs well even at high signal frequencies.
Figure 3.4 Active interpolation scheme VinB
VinA
Vout T
Vout
VinB
M1 M2
R1 R2
M3VinA NVinAM4 NVinB
V
3.3 Comparison of Different Design Techniques
3.3.1 6-bit Flash ADC with Auto-zero Technique [12]
Figure 3.5 shows an example of a high-speed flash architecture utilizing auto-zero technique. A specific feature of disk-drive read-channel systems is that the conversion cycles are interrupted regularity and an auto-zero function can be performed. During this time, reference levels and comparator offsets are stored on the sampling capacitors C+ and C-. During normal operation the comparators determine the position of the input signal relative to the reference levels. Each comparator is composed of two wide-bandwidth preamplifiers P1 and P2, followed by three latch stages L1, L2, and S-R latch.
Figure 3.5 6-bit flash ADC with auto-zero technique
Auto-zero has two drawbacks. It needs series-input capacitors that limit resolution bandwidth, and also requires ”idle time” for offset cancellation. The
P1 P2 L1 L2 SR
alternative application of this work is intended for DVD playback that requires no
“idle time”.
3.3.2 6-bit Flash ADC with Sample-and-Hold and Auto-zero Technique [13]
The resolution bandwidth and conversation rate degradation due to the series-input capacitors in flash auto-zero architecture can be improved by adding a sample-and-hold circuit. The top level block schematic of this ADC is shown in Figure 3.6. The input is sampled and held by the S/H. An important feature of this architecture is that it uses two interleaved S/H circuits operating at half the sampling frequency. The interleaving has two advantages. First, the acquisition time available for each S/H is twice that which would be available if a single S/H circuit were used.
Second, the final output of the S/H is held for an entire clock interval. This dramatically eases the design of the output buffer that drives the comparator array.
The output from the S/H is fed into the comparator array which converts the input signal into a digital thermometer code, which is then converted to a 1-of-64 code by the bubble correction logic. This in turn is fed into a ROM type encoder that generates the final 6-bit digital output.
The sample-and-hold preceding the series-input capacitors improves the ADC’s resolution bandwidth and sampling rate. However, the improvement will not be as effective as eliminating the input capacitors entirely.
Figure 3.6 6-bit flash ADC with S/H and auto-zero technique
3.3.3 6-bit Flash ADC with Background Digital Calibration [14]
To improve the ADC linearity, series-input capacitors are essential for auto-zero architecture to store and therefore to cancel random offsets of the comparators, which cost speed degradation. Accuracy improvement can also be achieved, without input capacitors, by digital calibration. A block diagram of this ADC is shown in Figure 3.7. The ADC consists of a T/H circuit, 63 preamplifiers, 63 comparators, each having offset calibration circuit, and an interleaved encoder capable of error correction.
Figure 3.7 6-bit flash ADC with background digital calibration
T/H circuits overcome the sampling time skews and the aperture time differences in the comparators to improve the ADC’s conversion rate and resolution bandwidth. The comparator uses three stages to achieve high-speed and low power consumption at the same time. Each offset in the preamplifier and comparator is calibrated by the OFC. The OFC, consisting of an up/down-counter and current sources controlled by the counter outputs, detects the preamplifier and the comparator offsets using the 3rd stage comparator output. These current sources are fed back to the first stage comparator without affecting the comparator speed.
Improvement in resolution bandwidth due to T/H circuit is clearly shown on measurements. The background digital calibration allows smaller transistors in analog signal path to achieve high conversion rate without accuracy degradation but costs half of the active die area. Bandwidth limitations on preamplifier and comparator stages seem to limit the maximum achievable speed of this architecture.
C2 C3
3.3.4 6-bit Flash ADC with Distributed T/Hs and Resistive Interpolation [15][16]
The analog preprocessing circuitry is shown in Figure 3.8. The analog preprocessing circuit converts the differential input signal into 65 parallel signals which are connected to the comparator inputs. The gain in this analog preprocessing block is realized by a cascade of amplifier stages. A sampling operation is inserted after the first stage. The analog bandwidth of the first amplifiers up to the sampling switches determines the analog signal bandwidth of the converter, while the bandwidth of the amplifiers after the sampling switch relates to the sampling rate and the required settling time. Only the first stage operates in continuous-time mode, demanding linear behavior over the complete input signal bandwidth in the cascade of subsequent amplifier stages.
Figure 3.8 6-bit flash ADC with distributed T/H and resistive interpolation
The first set of amplifiers A1 through A11 are connected to a reference resistor ladder and to the differential signal input. The first and last amplifiers in combination with the reduced resistors R1-R2 implement the termination circuit. The averaging resistors also implement a first interpolation: the averaging resistors are divided in
CLK
two parts, each with a value of R2/2. After sampling, the signals are amplified (B1…B19) and interpolated again, generating 34 parallel differential outputs. These outputs act as inputs for the third amplification (C1…C34) and interpolating stage.
The combination of the fourth amplifier stage and the comparator stage generates 65 parallel digital output signals which are clocked through 65 flip-flops.
Even though the distributed T/H circuits improve the conversion rate by pipelining the analog path, they suffer dynamic inaccuracies due to skews in the clock signals distributed across the array like any parallel scheme. A single front-end T/H with sufficient linearity outperforms the distributed T/H at high input frequencies. The cascaded amplifier stage with averaging, which is necessary to alleviate the comparator offset, degrades the conversion rate and resolution bandwidth due to its limited overall signal bandwidth.
3.3.5 6-bit Flash ADC with Resistive Averaging [17]
Figure 3.9 shows a flash ADC with balanced circuits in the T/H, reference ladder, and other preamplifiers for second-order distortion cancellation. The T/H is designed for 8-bit linearity with the highest possible bandwidth. The preamplifier array with a gain of 3 senses the difference between the differential input signal and the differential threshold to drive the latched comparator. However, the preamplifiers in the array suffer from random offsets. Collective averaging of the preamplifier outputs across a properly designed resistor network lowers the impact of the offsets,
Figure 3.9 shows a flash ADC with balanced circuits in the T/H, reference ladder, and other preamplifiers for second-order distortion cancellation. The T/H is designed for 8-bit linearity with the highest possible bandwidth. The preamplifier array with a gain of 3 senses the difference between the differential input signal and the differential threshold to drive the latched comparator. However, the preamplifiers in the array suffer from random offsets. Collective averaging of the preamplifier outputs across a properly designed resistor network lowers the impact of the offsets,