A VERAGING

In order to reduce the random offsets of preamplifiers, the averaging is a popular technique. Especially in our 5-bit resolution ADC, it is needed to improve the accuracy. The reason is that the preamplifiers of 5-bit ADC have more random offset sources than those of 4-bit ADC, and a 5-bit ADC needs twice the accuracy as compared to a 4-bit ADC.

The averaging technique generally includes two methods, resistive averaging and active averaging. Although the resistive averaging is more popular in resent year, there are two reasons that it is not suitable in this work. First, the preamplifier is more suitable for using active averaging than resistive averaging. Second, although the resistive averaging shows a positive effect on random offset, however, non-linearity is found at the edge. This error is caused by the unequal amount of averaging amplifiers that contribute to the zero crossing of the “end point” amplifiers. In practice, a usable input range is lower than 70% of the reference voltage range. To overcome the linearity problem, the optimal numbers of amplifiers are added at the top and the bottom of the signal range [17]. But, this causes more power consumption and chip area. Another method is to use band compensation resistor [16]. But, this is inaccurate in designing the resistor value. Thus, we decide to use active averaging to suppress the random offsets of the preamplifiers.

Figure 5.4 shows the active averaging method of our preamplifiers architecture.

The preamplifier can be separated into two parts, four inputs continuous time differential part and current mirror latch with reset part. We use the second part to average the random offsets of four input transistors in the first part. Thus, it needs to add two dummy amplifiers on the top and bottom. In our work, 5-bit ADC needs 33 amplifiers and 31 latches.

Figure 5.4 Active averaging method of preamplifiers

5.3 Interpolation

In order to reduce the number of preamplifiers, the interpolation is a popular technique, especially in our 5-bit resolution ADC. If we want to improve one bit resolution without doubling the power consumption and area, it is needed to use the interpolation technique. Because of each preamplifier of 5-bit ADC have more power consumption and transistor number than those of 4-bit ADC. Another advantage of interpolation is that it has a positive effect on the differential non-linearity.

The interpolation technique generally includes three methods, capacitive interpolation, resistive interpolation, and active interpolation. The capacitive interpolation is usually used in discrete time sampled data system. But, it is hard to be operated at ultra high speed. Although the resistive interpolation is more popular in resent year, there are three reasons that it is not suitable in our work. It is not suitable for out preamplifiers and requires large number of dummy amplifiers, as described in the previous section. The third reason is that the direct signal path and interpolated signal path have different time constant delay. Bubble errors are induced due to signal skew of neighboring comparators by using resistive interpolation. Thus, we decide to use active interpolation to decrease power consumption and number of preamplifiers and suppress the random offsets of the preamplifiers.

Figure 5.5 shows the active interpolation method of our preamplifiers architecture. As described in Section 5.2, the preamplifier can be separated into two parts. We use the first part to interpolate the second part. Thus, it needs to add two dummy amplifiers on the top and bottom. In this work, 5-bit ADC needs 16 amplifiers and 31 latches.

Figure 5.5 Active interpolation method of preamplifiers

5.4 Summary

Part of the circuits used in 5-bit ADC is built in 4-bit ADC, for example, the track-and-hold, the first latch, the second latch, the clock generator, and the output driver. The digital encoder is extend from 4-bit ADC by adding some logic gate to extend one bit and increasing one pipeline stage to match the total signal delay. We change the preamplifier architecture to provide more voltage gain for one more bit.

Use active averaging and active interpolation to increase one more bit resolution and save power consumption is the main focus of this chapter.

Chapter 6

Simulation Results

Three architectures, a 4-bit flash ADC, a 5-bit flash ADC with averaging, and a 5-bit flash ADC with interpolation, were discusses in Chapter 4 and Chapter 5. In this chapter, the simulation results are presented. In Section 6.1, the simulation results of each block are first presented. In Section 6.2, the static performance in time domain analysis of the whole ADCs is presented. In Section 6.3, the dynamic performance in frequency domain analysis of the whole ADCs is presented. In Section 6.4, the summaries of the three ADCs are reported.

6.1 Circuits Simulation

6.1.1 Track-and-Hold Simulation

As discussed in Section 4.1, Figure 6.1 shows the speed performance of the three types of unity gain buffers as function of supply current. The speed performance depends on the positive and negative slew rate based on the same power consumption.

The linearity performance of those buffers is shown in Figure 6.2.

Push Pull

Constant Current

Constant Current & Push Pull

Push Pull

Constant Current & Push Pull

Constant Current

60%

power

Figure 6.2 Linearity performance of three type buffers SFDR=67.5dB

THD=0.044%=-67.1dB SNR=71.1dB

SFDR=48.3dB THD=0.387%=-48.2dB SNR=71.2dB

Push Pull

Constant Current &

Push Pull

SFDR=47.2dB THD=0.44%=-47.1dB SNR=70.9dB

Constant Current

Figure 6.3 shows the dynamic performance of the T/H operates at 498MHz input and varies sampling rate from 1GSps to 4GSps. The dynamic performance of the T/H operates at 3.125GSps and 3.6364GSps with different input is shown in Figure 6.4.

Figure 6.3 Dynamic performance of T/H at 498MHz input signal Dynamic Linearity @ Fin = 498MHz

1, 34.9

SDR & SFDR (dB)

SDR SFDR

Dynamic Linearity @ Fs = 3.125 GHz & Fs = 3.6364 GHz

498, 38.8

300 500 700 900 1100 1300 1500 1700 1900

Input Frequency (MHz)

SDR (dB)

Fs = 3.125 GHz Fs = 3.6364 GHz

6.1.2 Preamplifier Simulation

As discussed in Section 4.2, Figure 6.5 shows frequency response of the passive load preamplifier. The GBW is 7.7GHz which is larger than the requirement for 4-bit 4GSps.

Figure 6.5 Frequency response of the passive load preamplifier

Another issue is the random offsets of the preamplifiers. We should estimate the mismatching of differential pairs in each preamplifier. The mismatch formulas are given by [33] distance on chip between the matching transistors. W and L are the width and length of the input transistors of the differential pair. β is the current factor of the technology. The input-referred offset of the differential pair is given by

( )

₂

^{( )} ( )

²

with V_gst the gate-overdrive voltage of the input transistors. The offset voltage can DC Gain 2.97

F-3db 2.6GHz

be written in terms of the mismatch parameters

The distance effect has been neglected because of its minor contribution to the overall mismatch.

Thus, we accord the formula 6.4 and Table 6-1 to simulate the input-referred offset by using 700 times of Monte Carlo Analysis. The parameters of 0.18um CMOS technology are presumed from 2.5um to 0.25um. The input-referred offset distribution is shown in Figure 6.6. The standard deviation is 5.28mV which is 0.21 LSB in 4-bit and 0.42 LSB in 5-bit case.

Table 6-1 Mismatch parameters for several CMOS technique

Figure 6.6 Preamplifier input-referred offset distribution

6.1.3 Comparator Simulation

We combine the preamplifier described in Section 4.2, first latch described in Section 4.3, and second latch described in Section 4.4. Figure 6.7 shows the speed performance of the comparator in the worst case which is given a 0.5 LSB input step at every clock cycle of 4GHz.

Figure 6.7 speed performance of the comparator

1^st latch output

2nd latch output

6.2 Static Performance Simulation

Based on the simulation method of input-referred offset, we simulate the DNL and INL of the whole ADCs by using 30 of times Monte Carlo Analysis. Figure 6.8 shows the static performance of the 4-bit ADC. Figure 6.9 shows the static performance of the 5-bit ADC with averaging technique. Figure 6.10 shows the static performance of the 5-bit ADC with interpolation technique. The solid line means no mismatch, and star means mismatch in one Monte Carlo Analysis.

Figure 6.8 DNL and INL of the 4-bit ADC at 4GSps DNL (+0.4LSB/-0.45LSB)

INL (+0.6LSB/-0.3LSB)

Figure 6.9 DNL and INL of the 5-bit ADC at 4GSps with averaging technique DNL (+0.35LSB/-0.35LSB)

INL (+0.5LSB/-0.8LSB)

Figure 6.10 DNL and INL of the 5-bit ADC at 4GSps with interpolation technique DNL (+0.45LSB/-0.5LSB)

INL (+0.5LSB/-0.9LSB)

Figure 6.11 shows the post layout simulation of the 4-bit ADC without mismatch at 4GSps. In FF case, we find it is almost the same as in Figure 6.8. In TT case, the 4GSps is too fast to have the same performance with pre-simulation.

DNL (+0.45LSB/-0.55LSB) TT

FF

INL (+0.5LSB/-0.45LSB) TT

FF

6.3 Dynamic Performance Simulation

Figure 6.12 shows the dynamic performance of the 4-bit ADC at 3.125GSps and 4GSps. Figure 6.13 shows the dynamic performance of the 5-bit ADC with averaging technique at 3.125GSps and 4GSps. Figure 6.14 shows the dynamic performance of the 5-bit ADC with interpolation technique at 3.125GSps and 4GSps.

Figure 6.12 ENOB of the 4-bit ADC at 3.125GSps and 4GSps

Figure 6.13 ENOB of the 5-bit ADC with averaging technique at 3.125GSps and 4GSps

Figure 6.14 ENOB of the 5-bit ADC with interpolation technique at 3.125GSps and 4GSps

Dynamic Linearity

2 2.5 3 3.5 4 4.5 5

0 0.5 1 1.5 2 2.5

Input Frequency(GHz)

ENOB

3.125GS/s 4GS/s

Figure 6.15 shows the dynamic performance of the pre-simulation of the 4-bit ADC on 1.55GHz input signal at 3.125GSps. Figure 6.16 shows the dynamic performance of post-simulation of the 4-bit ADC at 3.125GSps and 1.55GHz input signal.

Figure 6.15 Dynamic performance of pre-simulation of the 4-bit ADC at 3.125GSps and 1.55GHz input signal.

SNDR 20.5 dB ENOB 3.11 bit

Figure 6.16 Dynamic performance of post-simulation of the 4-bit ADC at 3.125GSps and 1.55GHz input signal.

SNDR 17.34dB ENOB 2.59 bit

6.4 Summary

Technology CMOS 0.18um CMOS 0.18um CMOS 0.18um

Voltage Supply 1.8V 1.8V 1.8V

Input Range 0.8V_p−p 0.8V_p−p 0.8V_p−p Sampling

Frequency 4GHz 4GHz 4GHz

Resolution 4 bit 5 bit 5 bit

DNL +0.4LSB /-0.45LSB +0.35LSB /-0.35LSB +0.45LSB /-0.5LSB

INL +0.6LSB/-0.3LSB +0.5LSB/-0.8LSB +0.5LSB/-0.9LSB

SNDR

Error Reduction NO Averaging Interpolation

Average Power 180mW 270mW 243mW

Table 6-2 Performance Summary

Three cases can maximally operate at 4GSps. We find that the DNL in 4-bit case is approach the worst case (LSB=0.5b). So, it can not increase one more bit without adding error reduction. In 5-bit cases, using averaging technique can obtain better static and dynamic performances than using interpolation technique. But, it consumes more power about 27mW due to more preamplifiers number.

Chapter 7 Conclusion

According to the speed-power-accuracy trade-off, Table 7-1 compares the performance of these ADCs with other CMOS flash converters reported in recent years. It is apparent that the ADC reported here advances the state of the art.

The key features of this work are now summarized. A front-end T/H for these flash ADCs enables beyond Nyquist input up to 4GHz conversion rate. Continuous time preamplifier provides low kick back noise. Reset switches in the first latch, the second latch, and the latch part of preamplifier give fast overdrive recovery. The second latch is the fastest such CMOS circuit with rail-to-rail output. Adding current source to the active load in the preamplifier improves the gain. Replacing the ROM-based encoder with logic-based encoder and using pipeline technique in the encoder improves the operation speed. Using thermometer-Gray-binary digital encoder lowers the bubble errors.

In this work, replacing resistor averaging networks with active averaging technique improves the operation speed and reduces the number of dummy amplifiers.

Using active interpolation technique also helps to reduce the number of preamplifiers.

These ideas have led to a compact CMOS ADC with more accuracy.

Resolu -tion

Speed Supply Power Technol-ogy

Table 7-1 ADC performance comparison

According to the speed-power-accuracy trade-off, Figure of Merit (FOM) shows the comparison with the flash ADCs of others. In this work, the 4-bit case is better than others except Ref. [34], and two 5-bit cases are better than others.

According to the speed performance, in this work, 4GSps is the fastest results. Only Ref. [38] can also operate at 4GSps. But, it is implemented by CMOS 0.13um technology.

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