In this section, the optimized parameters for on-target fabrication of the 65 nm CMOS devices will be investigated. For the sake of simplicity, we focus on the results of the 65 nm N-MOSFET. The device characteristics and the fluctuation tolerance of the threshold voltage are summarized in column 2 of Table 4.1. In this investigation, the on- and off-state currents, the threshold voltage as well as the device’s fluctuation tolerance have been optimized simultaneously. With these four physical constraints, the coupled simulation and optimization methodology was self-consistently performed with the specified fitness function. The initial doping profile used in the optimization procedure is shown in Fig. 4.3.
The simulated doping of the optimized device, both with and without the reduction of the threshold voltage fluctuation, are shown in Figs. 4.4a and 4.4b, respectively. Figure 4 shows a 1-D section in the center of the device channel of the 2-D doping profile distributions shown in Figs. 4.3 and 4.4. It can be observed that the minimization of the threshold voltage fluctuation (dotted line) results in a lower doping level compared with the optimization without (dashed line). This optimization automatically achieved the target parameters. Fig.
4.6 shows the horizontal doping profile 2nm below the channel surface between the source and drain. Together with the results, shown in Fig. 4.5, the higher doping level along the channel for the device when the threshold voltage fluctuations were also optimized maintains the same device characteristics as the one where dopant fluctuations were not
Table 4.1: A comparison list of the achieved results with respect to the two different extractions. The target specification is adopted from realistic fabricated and measured data.
Target to be Result without Result with achieved σvthreduction σvthreduction
Ion (mA/µm) > 0.35 0.35 0.39
Iof f (mA/µm) < 1.5e-11 1.05e-11 1.13e-11
Vth(V) ∼ 0.436 0.442 0.432
σvth(V) ∼ 0.017 0.03 0.014
σvth/Vth (%) 3.89 6.78 3.24
considered.
-8.0e17
( cm )
-3X Y
2.44e19 4.96e197.48e191.00e20
Figure 4.3: An illustration of the initial doping profile for the explored 65 nm N-MOSFET.
(a)
(b)
-8.0e18
( cm )
-31.50e181.10e19 2.05e193.00e19
-8.0e18
( cm )
-31.50e18 1.10e19 2.05e193.00e19
X Y
Figure 4.4: The optimized 65 nm N-MOSFET doping pro le for the device (a) without and (b) with considering the
minimization of the threshold voltage fluctuation.
Table 4.2: A list of process recipe and device parameters for the device optimization w/ and w/o considering the fluctuation
reduction.
Parameters Parameters Range Result without Result with σvthreduction σvthreduction
Core VT implantation Energy: 20∼80 KeV 58 24
Dose: 1e12∼2e13 cm−2 2.7e12 1.3e13
N-LDD implantation Energy: 10∼50 KeV 28 29
Dose: 1e12∼5e13 cm−2 3.1e13 3.8e13
P-WELL implantation Energy: 200∼400 KeV 250 250
Dose: 1e13∼4e13 cm−2 2.4e13 2.4e13
Mobility model B: 2e7∼8e7 cm/s 3.5e7 3.41e7
C: 100∼500 cm5/3/(V2/3S) 160 170
Velocity saturation Vsat0: 1e6∼1e8 cm/s 9e6 9e6
Vsat1: 0.5∼1.0 0.81 0.82
The results of the optimized 65 nm N-MOSFET are summarized in Table 4.1. If the threshold voltage fluctuation minimization is not be activated in the optimization, there is 6.7% threshold voltage fluctuation, which significantly shifts the process away from the design window (3.89%). The band profiles for the devices in the on- and off-states are shown in Figs. 4.7a and 4.8a for both of the optimization cases. The optimization without minimization of the threshold voltage fluctuation has a little bit lower band edge than its counterpart due to a higher doping level (Figs. 4.7a and 4.8a). Figs. 4.7b and 4.8b, once again show the horizontal profile along channel for both optimization cases. For the opti-mization without miniopti-mization of fluctuation, both the on- and off-state bands (2 nm below the channel surface) are lower than that the optimization minimizing the fluctuations. Both
the specified target and the optimized results are shown in Fig. 4.9. The results with and without considering the threshold voltage fluctuation are very close to the specified target.
Nevertheless, the strategy of including the reduction of threshold voltage fluctuation suc-cessfully reduced the threshold voltage fluctuation and is shown in Table 4.1. A list of the process recipe and device parameters used for simulation, and the extracted parameters, with and without fluctuation reduction, are summarized in Table 4.2. It can be noted that there is a major difference between the core VT implantation and the result with and with-out σvth reduction. To verify the efficiency of the proposed method, three examinations are performed on our PC-based Linux cluster system with 16 processors. The fitness score versus the number of evolutionary generations is shown in Fig. 4.10. For the given target, it shows that the methodology with simultaneously considering the parameters of the process and device physics provides better computational efficiency.
Figure 4.5: The optimized doping profiles from the channel surface deep into the substrate. The 1-section is located at the center of device channel (x = 0).
Figure 4.6: Doping profile from the source to drain along the channel direction 2 nm below the interface between the gate oxide and the silicon substrate. The inset of the figure shows the structure of the optimized 65 nm N-MOSFET.
Figure 4.7: Plots of band profile for the optimization with and without considering the threshold voltage fluctuation under the on-state; (a) is from the surface to the substrate and (b) is along the channel direction from the source to the drain which is about 2 nm below the channel surface.
Figure 4.8: Plots of band profile for the optimization with and without considering the threshold voltage fluctuation under the off-state; (a) is from the surface to the substrate and (b) is along the channel direction from the source to the drain which is about 2 nm below the channel surface.
Figure 4.9: The achieved accuracy of the extracted I-V curves for the explored 65 nm N-MOSFET.
Figure 4.10: The performance comparisons among three different evolutionary strategies. There are totally 31 process and device parameters to be optimized in the case of the 2D process and device simulations. The total time is about 70 hours on a PC-based Linux cluster with 16 processors.
Application of UOF in VLSI Device Model Parameter Extraction
D
evice model associated with a set of optimized parameters currently plays a central role in the connection between circuit design and chip fabrication communities, as shown in Fig. 5.1. An automatic model parameter extraction system that simultaneously integrates evolutionary and numerical optimization techniques for optimal characterization of very large scale integration (VLSI) devices has recently been advanced. In this chapter, a hybrid intelligent general solution method for compact model parameter extraction is pro-posed. This solution technique combines the genetic algorithm (GA), the neural network (NN), and the Levenberg-Marquardt (LM) method for optimal I-V curves characterization,98
optimization, and parameter extraction of deep-submicron metal-oxide-semiconductor field effect transistors (MOSFETs). This unified intelligent computing technique can extract a set of corresponding optimal parameters for compact models. The well-known BSIM-4 and EKV MOSFET compact models have been studied and implemented for automatic pa-rameters extraction using the proposed intelligent architecture. The further investigation of the random number generations in the GA is also presented in this chapter.
5.1 The Equivalent Circuit Model Parameter Extraction Problems
The simulation program with integrated circuit emphasis (SPICE) models, such as BSIM, HiSIM, and PSP models characterize VLSI device’s electrical characteristics (e.g., I-V curves), which are associated with a set of optimized parameters. However, in semiconduc-tor device simulation, the setting for each construction parameter is always a complicated problem. The process that fits the simulation data as closely as possible to measured data is called the parameter extraction. For the problem of the SPICE model parameter extraction, it usually refers to several hundred I-V points. It is not only a time consuming task but also requires engineering expertise to find a proper configuration of parameters with reasonable physical meanings. Model parameter extraction techniques have been of great interest in
Model
Figure 5.1: An illustration of the equivalent circuit model in connecting the device fabrication and circuit design.
the last decade. Most of them have been proposed which include traditional numerical optimization methods and modern soft computing techniques [75–77] to solve such prob-lems with huge searching space. The model parameter extraction problem can be regarded as a multidimensional optimization problem to minimize the errors between the measured and simulated results.Various compact models have been of great interest and studied for deep-submicron and sub-100 nanometer device simulation [70–74]. An equivalent circuit model and corresponding parameter extraction intrinsically characterizes the properties of designed and fabricated devices. The model parameter extraction problem can be regarded as a multidimensional optimization problem to minimize the errors between the measured and simulated results.
The solution technique proposed in this chapter mainly consider the GA, the NN, and the LM method in optimal I-V curves characterization, optimization, and parameter ex-traction of deep-submicron MOSFETs. This unified intelligent computing technique can extract a set of corresponding optimal parameters for compact models. The well-known BSIM-4 and EKV MOSFET compact models have been studied and implemented for au-tomatic parameters extraction using the proposed intelligent architecture.