We notice that, GA is a global search optimization method based on the mechanics of natural selection and natural genetics. It works with a coded of parameters string called chromosome instead of the solutions themselves. Each chromosome represents a solution set, and the fitness functions used to measure the survival scores of all chromosomes in the population. However, the qualities of the random number generation scheme will affect the efficiency of GA. We thus examine eight different random number generation schemes in our intelligent extraction system. The selected random number generation formulations, as listed in Tab. 5.1, includes Logistic Map, Tent Map, Gauss Map, Sinusoidal Iterator, Lozi Map, Chua’s Oscillator, C/C++ Random Generator, and Chaotic Random Number Gener-ator [78–85]. The variables X1, X2, X3, ... in Tab. 5.1 represent the random number se-quence generated by the aforementioned methods. Among all schemes, the C/C++ random generator is a kind of linear congruent generator and it uses the Rand function to generate random number. The Rand function returns a value of the integer type (usually a two-byte quantity), the maximum RANDMAX value is often not so large. The other random num-ber generation methods can generate chaotic sequences. The Logistic Map [81–83] is the simplest method for generating chaotic sequences. The Tent Map [82, 84] has similar form
to the Logistic Map, which makes a little modification. The Sinusoidal Iterator [82, 84]
uses sinusoidal function to generate random number sequence. Lozi Map [82, 84] is a two-dimension map similar to the henon map but use −a × |Xk| to replace −a × Xk2. The chua’s oscillator [82, 83] is a well known chaotic oscillator. Apply suitable sampling times on Chua’s oscillator, we can derive discrete-time chaotic time series form the signals. The Chaotic Random Number Generator [85] is one of the popular methods, which can gener-ate random numbers with better randomness and longer cycle lengths in random maps. The randomness and cycle length of random numbers are the criterions of the random number generators. For better randomness and cycle length, the generated random number distrib-ution can aid the soldistrib-ution searches of GA.
To validate the function and accuracy of the proposed intelligent method, parameters of BSIM4 (BSIM version 4) model for 90 nm n-typed metal-oxide-semiconductor field effect transistors (N-MOSFETs) are extracted in our system and compared with the measured data, as shown in Fig. 5.8. The width and channel length of the target device is equal to 10 µm and 90 nm. The errors between measured and extracted I-V curves are less than 3%. For the model parameter extraction of multiple devices, we examine the following four N-MOSFET devices: (length / width) = (1.2 µm/ 10 µm), (10 µm / 10 µm), (10 µm / 1.2 µm) and (0.13 µm / 1.2 µm). Table 5.2 shows the extraction result of the four devices.
As shown in this table, RMS error of curves is strictly within 4% for all cases.
Table 5.1: Eight different random number generation schemes and their Generator and a, c are positive
Chaotic Random Zn = ((Yn−j rotr r3) + (Yn−krotr r1)) mod 2b/2 Number Generator Yn = ((Zn−j rotr r4) + (Zn−k rotr r2)) mod 2b/2
Xn= Yn+ Zn∗ 2b/2,
where k > j > i > 0, b > 4 ≥ 0. Y rotr r means the bits of Y rotated r places to the right.
Figure 5.9 demonstrates the behavior of the convergence score for a single MOSFET device using BSIM4 model parameter extraction. As shown in this figure, the most well-known C/C++ random generator or Gauss map do not have outstanding performance. Sim-ilarly, Fig. 5.10 shows the convergence score in the four devices’ extraction; it is obvious that C/C++ random generator even has the worst performance. It is found that the chaotic random number generator has superior convergence behavior for both single and multiple
Figure 5.8: The BSIM4-model extracted (solid-line) and measured (dot-lines) (a) IDS-VDS and (b) IDS-VGS curves of the MOSFET, where length = 90nm and width = 10µm. We notice that the chaotic random number generator is used in this simulation.
Table 5.2: List of the root-mean-square (RMS) errors of the extracted results compared with the measured data for the four N-MOSFET devices. The device dimension is in µm. The oxide thickness of target devices are 3.36nm and the working temperature is settled at 298.15K. The chaotic random number generator is used in this simulation.
Device Geometry (µm/µm) Error of IDS-VDS Error of IDS-VGS
L/W (1.2/10) 3.59% 3.31%
L/W (10/10) 2.92% 3.15%
L/W (1.2/10) 3.21% 3.51%
L/W (1.2/0.13) 3.24% 3.34%
Figure 5.9: Comparison of the convergence score in GA with different random number generation schemes. In this extraction experiment, GA extracts a single N-MOSFET device.
devices extraction cases. It generates the random numbers with better distribution which keeps the diversity of the extraction system, thus the best performance of the convergence score is reached. According to the numerically achieved results, it shows that the random number generation will affect the performance of GA and better generation method can improve the search for solutions in the problem of semiconductor device model parameter extraction.
Figure 5.10: Comparison of the convergence score in GA with different random number generation schemes. In this extraction experiment, GA extracts four N-MOSFET devices at the same time.
Application of UOF in VLSI Circuit Design
I
n this chapter, we introduce two approaches for design optimization of integrated cir-cuits (ICs). The first one is a simulation-based approach which is based on evolution-ary algorithms, numerical methods and circuit simulation. One of evolutionevolution-ary algorithms, such as genetic algorithm (GA), will enable us to search solution globally, the numerical methods, such as Levenberg-Marquardt (LM) method, will enhance the results of GA by performing the local optimization and the circuit simulation is used to evaluate the fitness of each individual in the GA. Another one uses a computational statistics technique for the118
circuit design. Integration of a well-known circuit simulation software and central compos-ite design method enables us to construct a second-order response surface model (RSM) for each concerned constraint. After construction of RSMs, we verify the adequacy and accuracy using the normal residual plots and their residual of squares. The constructed models are further employed for design optimization of ICs. One current mirror amplifier ICs with 0.18 µm CMOS devices are examined in this chapter. By considering the voltage gain, cutoff frequency, phase margin, common-mode rejection ratio and slew-rate, six de-signing parameters including the width and length of different transistors are selected and optimized to fit the targets. We also compare the optimized results of the computational statistics approach and the results of the simulation-based approach.
6.1 The Integrated-Circuits Design Problem
It is known that integrated circuits (ICs) design nowadays plays a crucial role for micro-electronics industry; in particular, for highly competitive consumer products [1, 2, 29, 31, 57, 86–90]. In modern ICs design flow and chip implementation, IC designers perform a series of functional examination and analysis of the characteristics by circuit simulation tools to match specifications. To meet specified electrical characteristics and performance of designed product, designers in general have to tune parameters of the passive and active devices ranging from resistors, capacitors, inductors, line width, line length, to transistor
size, etc [1, 2, 31, 38, 57, 60, 89, 90]. It thus requires experienced designers to accomplish such complicated works. Diverse approaches have been proposed to reduce this design-ing cycle, which includes numerical optimization techniques and evolutionary algorithms;
and have demonstrated their merit and validity [1, 2, 31, 46, 47, 57, 60, 89–96, 98]. Further-more, integration of circuit simulation tool, design of experiment, and response surface methodology may also provide a cost-effective way to advanced IC design optimization and sensitivity analysis of performance.
In this investigation, two different approaches are implemented and compared for the circuit design optimization. One is a simulation-based approach which is based on the in-tegration of evolutionary algorithms, numerical methods and circuit simulation. First of all, preliminary parameters as well as the netlist for circuit simulation are loaded. A cir-cuit simulation tool will be performed for the circir-cuit simulation and then the results are used in the evaluation of specification. Once the specification meets the aforementioned constraints, the optimized parameters will be outputted. Otherwise, we activate an evolu-tionary method, such as genetic algorithm, for the global optimization; in the meanwhile, a gradient-based method, such as the Levenberg-Marquardt method, searches the local op-tima according to the global searched results. The numerical optimization method does significantly accelerate the evolution process. We repeatedly call circuit simulator to com-pute and evaluate newer results until the specification is matched. Another approach uses a
computational statistics technique [35] for the ICs design optimization. Based on HSPICE circuit simulator [1, 57, 90, 107], a central composite design (CCD), and a second-order response surface model (RSM), the circuit performances can be systematically optimized with respect to different specified constraints. The investigated current mirror amplifier IC with 0.18 µm CMOS devices has the specifications that includes the voltage gain within 50∼100db, the cut-off frequency (FT) within 20∼70MHz, the common-mode rejection ra-tio (CMRR) within 60∼85db, the slew-rate (SR)+ within 20∼80V/uS, and the range of SR- is 20∼70V/uS. We firstly use the circuit simulator and the central composite design to construct the second-order response surface models. Seventy-seven experimental runs of circuit simulations are completed to generate the necessary data for construction of the quadratic response models. For validating the constructed model, the model adequacy checking and the accuracy verification are necessary [91, 97, 99–102]. With the second-order RSMs [60, 91, 97, 99, 101], some optimization approaches, such as the least squares method and desirability function approach, can be used to extract the optimal parameters to fit the specifications. In the examined current mirror amplifier IC, six parameters including the width and length of different transistors are selected and optimized to satisfy the circuit specifications.
Transistors to
Figure 6.1: Functional blocks for the proposed simulation-based hybrid optimization approach.