Compared with passive mixers, active mixers exhibit a better conversion gain (CG) with lower LO input power. However, active mixer both consumes DC power and exhibits worse linearity. Furthermore, the mixer core of this work is a double balanced mixer. With the double balanced structure, the port-to-port isolation is better than single balanced structure. The simulation bench of the mixer core M1 to M4 is shown in Fig.
3.5 and the source voltage Vs is derived from the IF stage. From the DC-IV curves shown in Fig. 3.6, the gate voltage is chosen at 1.2 V where is near to the pinch-off point to ensure the mixer core functional as LO switch. Fig. 3.7 shows the simulated CG and output power versus different IF input power for different Vd at 28 GHz. As can be tt
Fig. 3.5 Schematic of the double balanced mixer core.
Fig. 3.6 DC-IV curves of LO switching core.
Fig. 3.7 Simulated CG and output power versus different IF input power for different Vd at 28 GHz.
seen, when the drain voltage of the mixer is higher, the performance of the CG and output power is better. Therefore, the drain voltage of the proposed mixer is selected at 1.4 V and the drain current of the mixer cores is 325 A. The simulated conversion gain versus different LO power for different bias at 28 GHz is shown in Fig. 3.8. As can be seen, the conversion gain at LO power around 0 dBm is roughly the same with different bias condition of the mixer core. The device size selection of the mixer core (M1-M4) is decided according to the output power of proposed mixer. For the conversion gain of the active mixer, it can be expressed as below:
,
Fig. 3.8 Simulated conversion gain versus different LO power for different bias at 38 GHz.
Fig. 3.9 Simulated conversion gain versus LO power for different transistor fingers at 38 GHz.
Fig. 3.10 Simulated LO port input impedance at different LO power at 38 GHz.
Fig. 3.11 The Id versus Vgs with different gate width.
Fig. 3.12 Simulated conversion gain of active mixer versus different LO power at 38 GHz.
impact on the design of matching circuit, as shown in Fig. 3.9 and Fig. 3.10. In the proposed mixer design, the device size selection can be decided according to the design goal of output saturated power. From the load-line theory, the total dc current of mixer core is calculated according to the targeted saturated output power of -2 dBm. Fig. 3.11 shows the Id versus Vgs with different gate widths and the device size is chosen to fulfill the required drain current. As a result, the width of M1 to M4 is selected at 3 m per finger and the finger is 12. Fig. 3.12 shows the simulated conversion gain versus different LO power. The CG reaches maximum at the LO power near 2 dBm. Therefore, the LO power selection is at 2 dBm in the proposed design.
In LO port design, to get higher conversion gain, the transformer matching circuit is used to replace high-order transmission line matching in [37]. The LO matching network and the EM layout are shown in Fig. 3.13. Due to the large impedance transformation from 50Ωto 30-j190Ω, transformer is one of the most suitable solution.
The impedance at different ports of the transformer are demonstrated on Smith chart and shown in Fig. 3.14. Besides, the insertion loss is another important factor that would be considered in the matching circuit design. The conductor loss and I/O output return loss are shown in Fig. 3.15 and the insertion loss of the LO matching network is 3.5 dB at 29 GHz. Although the simulated results shown in Fig. 3.14 demonstrate that the impedance is very close to 50Ω with LO matching network at different LO power, insertion loss of the matching circuit is still larger than expected result. Fig. 3.16 shows the insertion loss of transmission lines using 28, 65, and 90 nm CMOS technology. The length of the transmission line is 120 m and the width of the transmission line is 12
m. Compared with 90-nm and 65-nm CMOS technology, insertion loss of transmission line with the same device size is much lower than that in 28-nm CMOS technology in
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Fig. 3.13 The EM layout of the LO matching network.
Fig. 3.14 The impedance seen before and after the LO matching circuit under different LO power at 37 GHz.
Fig. 3.15 The simulated insertion loss and I/O return loss of the EM LO matching network.
Fig. 3.16 The simulated insertion loss of transmission line of 28, 65, and 90 nm CMOS technology.
Fig. 3.17 The CG of the mixer core with and without LO matching network.
Fig. 3.18 The phase difference of the LO transformer design.
millimeter-wave frequency. Although ideal performance of the transistor in 28-nm CMOS is better, the insertion loss of matching network would offset this merit in the millimeter wave frequency. Nonetheless, the simulation result shown in Fig. 3.17 presents that the CG of active mixer core is higher with the LO matching circuit.
Besides, the differential signal can also be generated through on-chip transformer. Fig.
3.18 demonstrates the phase difference of the LO transformer design.
Similarly, the transformer matching network is also implemented in the RF port design. The RF matching circuit and the EM layout are shown in Fig. 3.19. The matching circuit is built by the transformer and the inductors. Fig. 3.20 shows the impedance of the RF matching network plotted on Smith chart which is designed for impedance matching from 10 to 50 GHz. The transformer also works as a Marchand balun to generate the differential signal.
Fig. 3.19 The EM layout of the RF matching network.
Fig. 3.20 The impedance of the RF matching circuit from 10 to 50 GHz.
3.2.3 The Design of transconductance stage and IM2 signal injection